KR20050055978A - Fin field effect transistors and methods of forming the same - Google Patents

Abstract

The present invention provides a fin field effect transistor and a method of forming the same. The fin field effect transistor has a fin that extends vertically from the substrate and whose lower part is formed of an insulator. The gate electrode crosses over the fin, and a gate insulating film is interposed between the gate electrode and the fin. Source / drain regions are disposed in the fins on both sides of the gate electrode.

Description

Fin field effect transistor and its formation method {FIN FIELD EFFECT TRANSISTORS AND METHODS OF FORMING THE SAME}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of forming the same, and more particularly to a fin field effect transistor and a method of forming the same.

In general, the field effect transistor (hereinafter referred to as a transistor) of a semiconductor device has a horizontal channel. As the high integration of semiconductor devices is intensified, the transistor having the horizontal channel is limited in scale-down due to various causes. Representative of the various causes of the short channel effect (short channel effect) and the DIBL (Drain Induced Barrier Lower) phenomenon caused by the shorter channel length.

Recently, as one of methods for solving these problems, a fin field effect transistor (hereinafter, referred to as a fin transistor), which is a type of a double gate transistor, has been proposed. The fin transistor has thin fins that protrude vertically from the substrate. A gate electrode passing through at least both side walls of the fin is disposed.

In a conventional transistor having a horizontal channel, a gate electrode is formed only on the horizontal channel over to apply an electric field asymmetrically to the horizontal channel region. As a result, the on-off of the transistor having the horizontal channel may not be effectively controlled, and the influence of the short channel effect and the DIBL phenomenon may be severe. In contrast, in the fin transistor, gate electrodes are disposed on both sidewalls of the thin channel, thereby improving controllability of the gate electrode channel. As a result, the on-off characteristic of the pin transistor is improved, and the influence of the short channel effect or the DIBL phenomenon can be suppressed.

On the other hand, in the 2002 Symposium On VLSI Technology Digest of Technical Paper, Fu-Liang Yang et al., Titled "35nm CMOS FinFETs", pins formed on buried oxide of silicon on insulator (SOI) substrate, A fin transistor comprising a gate electrode across the top has been disclosed. The reason for forming the fin transistor on the SOI substrate is to solve various problems that may occur by directly forming the fin transistor on the bulk substrate. That is, when the fin transistor is formed on the bulk substrate, the characteristics of the fin transistor may be greatly deteriorated due to leakage current between the source / drain region and the substrate or the formation of parasitic transistors by neighboring fin transistors. Accordingly, by forming the fin transistor on the buried oxide film of the SOI substrate, the leakage current can be reduced, and the formation of the parasitic transistor can be prevented to improve the characteristics of the fin transistor.

However, SOI substrates are traded at high prices due to the complexity and difficulty of manufacturing processes. In other words, by using the SOI substrate, the manufacturing cost of the semiconductor element may increase and productivity may decrease.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a fin field effect transistor capable of reducing leakage current using a bulk substrate and a method of forming the same.

Another object of the present invention is to provide a fin field effect transistor capable of preventing the formation of parasitic transistors using a bulk substrate and a method of forming the same.

Provided are a fin field effect transistor for solving the above technical problem and other technical problems. The fin field effect transistor includes a fin extending vertically from the substrate, the lower part of which is made of an insulator. A gate electrode crosses the fin, and a gate insulating film is interposed between the gate electrode and the fin. Source / drain regions are disposed in the fins on both sides of the gate electrode.

Specifically, it is preferable that a portion of the insulator extends along the surface of the substrate around the fin. The fin field effect transistor may include a liner and a main buried pattern sequentially stacked on sidewalls of the fin. The liner is formed on a portion of the sidewall of the fin to expose the upper sidewall of the fin, and the main buried pattern has a higher top surface than the liner. In this case, the gate electrode crosses the exposed upper part of the fin. An auxiliary buried pattern interposed between the liner and the substrate may be further disposed. The lower surface of the source / drain region is preferably located above the upper surface of the insulator.

Provided are a method of forming a fin field effect transistor to solve the above technical problem and other technical problems. The method includes selectively etching a substrate to form a fin that extends vertically from the substrate and forming a lower part of the fin as an insulator. A gate electrode crossing the fin is formed through a gate insulating film, and a source / drain region is formed in the fin on both sides of the gate electrode.

Specifically, the method of forming the fin and the insulator may include forming a hard mask pattern on the substrate. The fin is formed by etching the substrate using the hard mask pattern as a mask, and a sacrificial insulating layer is formed on at least a sidewall of the fin and a surface of the substrate around the fin. An anti-oxidation spacer is formed on sidewalls of the fin and hard mask patterns through the sacrificial insulating layer, and at least a portion of the sidewall of the fin is exposed by removing the sacrificial insulating layer located under the lower surface of the anti-oxidation spacer. An oxidation process is performed on the substrate to form the insulator, and at least the antioxidant spacer is removed. At least expose the upper sidewall of the pin. Before forming the insulator, the step of recessing the exposed sidewall of the fin may be further performed.

In one embodiment, prior to forming the gate insulating film, the method includes conformally forming a liner film over the substrate, and forming a main buried insulating film filling the etched region of the substrate on the liner film. And planarizing the main buried insulating film and the liner film until the upper surface of the fin is exposed, and selectively recessing the planarized liner film to expose the upper sidewall of the fin. In this case, the gate electrode crosses the exposed top of the fin. The method includes forming an auxiliary buried insulating film filling the etched region of the substrate before forming the liner film, flattening the auxiliary buried insulating film until the top surface of the fin is exposed, and the planarized auxiliary buried film The method may further include forming an auxiliary buried pattern filling the portion of the etched region by recessing the insulating layer.

In example embodiments, the forming of the source / drain regions may include implanting impurity ions using the gate electrode as a mask to form the source / drain regions. In this case, a lower surface of the source / drain region may be formed to have a height greater than or equal to an upper surface of the insulator.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein and may be embodied in other forms. Rather, the embodiments introduced herein are provided to ensure that the disclosed subject matter is thorough and complete, and that the spirit of the present invention to those skilled in the art will fully convey. In the drawings, the thicknesses of layers (or films) and regions are exaggerated for clarity. In addition, where it is said that a layer (or film) is "on" another layer (or film) or substrate, it may be formed directly on another layer (or film) or substrate or a third layer between them. (Or membrane) may be interposed. Portions denoted by like reference numerals denote like elements throughout the specification.

1 is a perspective view illustrating a fin field effect transistor according to an exemplary embodiment of the present invention, and FIG. 2 is a cross-sectional view taken along line II ′ of FIG. 1.

1 and 2, a fin transistor according to an embodiment of the present invention includes a fin 105 extending vertically from a semiconductor substrate 100 (hereinafter referred to as a substrate). The substrate 100 is preferably a bulk substrate. The substrate 100 may be a silicon bulk substrate. The pin 105 is preferably made of the same material as the substrate 100.

The lower part of the pin 105 is made of an insulator 112. The insulator 112 is preferably a thermal oxide film. A portion of the insulator 112 may extend along the surface of the substrate 100 around the fin 105. A portion of the insulator 112 formed in the pin 105 may have a top surface having a different height from the top surface of the extended portion of the insulator 112. In particular, a portion of the insulator 112 formed on the pin 105 may have a higher top surface than an extended portion of the insulator 112. The central portion of the top surface of the insulator 112 formed on the pin 105 may have a lower height than the edges thereof.

The liner 116a 'and the main buried pattern 118a are sequentially stacked on the sidewalls of the fin 105. The liner 116a ′ is formed on a portion of the sidewall of the fin 105 such that the upper side wall of the fin 105 is exposed. That is, the top surface of the liner 116a 'is lower than the top surface of the main buried pattern 118a. A groove is formed surrounded by the exposed top side wall of the fin 105a, the top surface of the liner 116a 'and the top side wall of the main buried pattern 116a. A lower edge of the liner 116a ′ may extend along an extended portion of the insulator 112. An extended portion of the liner 116a 'is interposed between the extended portion of the insulator 112 and the main buried pattern 118a.

The main buried pattern 118a may be formed of an insulating film for device isolation, and the liner 116a 'may be formed of an insulating film having an etching selectivity with respect to the main buried pattern 118a. For example, the main buried pattern 118a may be formed of a CVD oxide film, and the liner 116a may be formed of a nitride film.

An auxiliary buried pattern 114a may be disposed between the liner 116a 'and the substrate 100. Specifically, the auxiliary buried pattern 114a may be interposed between the insulator 112 and the liner 116a '. An upper surface of the auxiliary buried pattern 114a may be disposed to approach the height of the uppermost surface of the insulator 112. The auxiliary buried pattern 114a may be formed of a material having excellent gapfill characteristics. For example, the auxiliary buried pattern 114a may be formed of an SOG film formed by a spin method. Specifically, the auxiliary buried pattern 114a may be formed of a material of a HSQ film or polysilase-based material.

A sacrificial insulating layer 107 may be interposed between the liner 116a ′ and the sidewalls of the fin 105. The sacrificial insulating layer 107 may be formed of a silicon oxide layer.

A gate electrode 120 crosses the fin 105. A gate insulating layer 119 is interposed between the gate electrode 120 and the fin 105. The gate electrode 120 extends to fill the groove under the gate electrode 120. Accordingly, the gate electrode 120 passes through both sidewalls and the top surface of the upper part of the fin 105. Although not shown, a capping insulating layer (not shown) having a thickness thicker than that of the gate insulating layer 119 may be interposed between the gate electrode 120 and the upper surface of the fin 105. The gate electrode 120 may be made of a doped polysilicon, a metal, or a conductive metal compound, which is a conductive film. The gate insulating layer 119 may be formed of a silicon oxide layer, in particular, a thermal oxide layer.

A source / drain region 122 including an impurity diffusion layer is disposed in the fin 105 on both sides of the gate electrode 120. The lower surface of the source / drain region 122 may have a height greater than or equal to the upper surface of the insulator 112. That is, the bottom surface of the source / drain region 122 may be in contact with the top surface of the insulator 112 or may be positioned high. In FIG. 1, the bottom surface of the source / drain region 122 is higher than the top surface of the insulator 112.

In another embodiment, the fin transistor has the auxiliary buried pattern 114a, the liner 116a ′, and the main buried pattern 118a omitted, so that the gate electrode 120 has both sidewalls of the fin 105. It may pass through the upper part and the lower part of the whole. In this case, it is preferable that an extended portion of the insulator 112 is interposed between a portion of the gate electrode 120 positioned on both sides of the fin 105 and the substrate 100.

In the fin transistor having the above-described structure, a lower part of the fin 105 is formed of the insulator 112, and the source / drain region 122 is the fin 105 of the insulator 112. Disposed within. Accordingly, the source / drain region 122 and the substrate 100 are separated by the insulator 122. Thus, the conventional leakage current can be prevented. The source / drain regions 122 are also isolated from source / drain regions (not shown) of other adjacent pin transistors (not shown). As a result, it is possible to prevent the formation of conventional parasitic transistors and to prevent deterioration of characteristics of the fin field effect transistors. In addition, since the substrate 100 is made of a bulk substrate, the productivity of the semiconductor device may be greatly improved due to the high cost of the conventional SOI substrate.

3 through 10 are process cross-sectional views taken along line II ′ of FIG. 1 to explain a method of forming a fin field effect transistor according to an embodiment of the present invention.

Referring to FIG. 3, a hard mask layer is formed on the entire surface of the substrate 100, and the hard mask layer is patterned to form a hard mask pattern 103 on a predetermined region of the substrate 100. The substrate 100 is preferably a conventional bulk substrate widely used in semiconductor devices. The hard mask pattern 103 may be formed of a material having an etching selectivity with respect to the substrate 100. In addition, the hard mask pattern 103 is preferably formed of a material that can prevent the oxidation of the surface of the substrate 100 positioned below it. For example, the hard mask pattern 103 may include a nitride 102. In this case, the hard mask pattern 103 may further include a buffer insulating film 101 interposed between the nitride 102 and the substrate 100. The buffer insulating layer 101 may play a role of alleviating stress due to a difference in tension between the nitride 102 and the substrate 100. The buffer insulating film 101 may be formed of a silicon oxide film. Of course, the hard mask pattern 103 may be formed of another material. The nitride 102 may be formed of silicon nitride. In addition, the nitride 102 may be formed of titanium nitride, tantalum nitride, or the like.

The substrate 100 is etched using the hard mask pattern 103 as a mask to form the fin 105. The pin 105 extends vertically from the substrate 100. The pin 105 is made of the same material as the substrate 100.

Referring to FIG. 4, a sacrificial insulating layer 107 is formed on at least the sidewall of the fin 105 and the surface of the substrate 100. The sacrificial insulating layer 107 is preferably formed of a thermal oxide film. That is, the sacrificial insulating layer 107 is formed on the sidewall of the fin 105 and the surface of the substrate 100 around the fin 105 by performing a predetermined oxidation process on the substrate 100 having the fin 105. Is formed. In this case, since the hard mask pattern 103 includes an antioxidant material, the sacrificial insulating layer 107 may not be formed on the upper surface of the fin 105. Alternatively, the sacrificial insulating layer 107 may be formed of a CVD insulating layer.

Before forming the sacrificial insulating layer 107, the substrate 100 having the fins 105 may be repeatedly trimmed and oxidized at least once to reduce the width of the fins 105. The adjusting step may be further performed. In this case, the width of the pin 105 may be thinner than the width of the hard mask pattern 105.

Subsequently, a conformal antioxidant film is formed on the entire surface of the substrate 100 having the sacrificial insulating layer 107, and the fin film 105 and the hard mask pattern 103 are etched back. The anti-oxidation spacer 109 is formed on the sidewall of the substrate. The sacrificial insulating layer 107 is interposed between the antioxidant spacer 109 and the fin 105 and between the antioxidant spacer 109 and the substrate 100. The anti-oxidation spacer 109 is formed of a material for preventing oxidation. In addition, the anti-oxidation spacer 109 is formed of a material having an etching selectivity with respect to the sacrificial insulating layer 107. For example, the antioxidant spacer 109 may be formed of a nitride such as silicon nitride. The hard mask pattern 103 may include the same material as the antioxidant spacer 109.

5 and 6, an isotropic etching process is performed to remove at least the sacrificial insulating layer 107 under the anti-oxidation spacer 109 to expose a portion of the sidewall of the fin 105. At this time, due to the isotropic etching process, the sacrificial insulating layer 107 formed on the surface of the substrate 100 around the fin 105 is also removed. The anti-oxidation spacer 109 has an etching selectivity with respect to the sacrificial insulating layer 107, so that the sacrificial insulating layer 107 formed on the upper part of the fin 105 may be protected.

Subsequently, a predetermined oxidation process is performed on the substrate 100 having the exposed sidewall of the fin 105 to form a lower part of the fin 105 as an insulator 112. As a result, the insulator 112 is formed of a thermal oxide. During the oxidation process for forming the insulator 112, the surface of the substrate 100 around the fin 105 is also exposed, so that a part of the insulator 112 is formed to extend along the surface of the substrate 100. do. During the oxidation process to form the insulator 112, the upper part of the fin 105 is protected by the anti-oxidation spacer 109 and the hard mask pattern 103, thereby preventing the fin ( The upper part of 105 is prevented from oxidizing.

Prior to forming the insulator 112, it is preferable to further perform the process of recessing the exposed sidewall of the fin 105. This results in the formation of recessed regions 110 on the exposed sidewalls of the fins 105, thereby increasing the area of the exposed surface of the fins 105 in the predetermined oxidation process. As a result, the process time for forming the insulator 112 can be shortened.

An oxidation process for forming the insulator 112 is isotropic. Accordingly, the insulator 112 is isotropically formed from the exposed sidewall of the fin 105. As a result, the upper surface of the insulator 112 formed in the lower part of the fin 105 can be formed such that its central portion has a lower height than its edges. In addition, the insulator 112 formed under the fin 105 may have a higher upper surface than a portion of the insulator 112 formed on the surface of the substrate 100.

7 and 8, the antioxidant spacer 109 is removed from the substrate 100 having the insulator 112. In this case, the nitride 102 included in the hard mask pattern 103 may be removed at the same time. That is, the upper part of the fin 105 may be protected by the residues of the buffer insulating film 101 and the sacrificial insulating film 107. If the hard mask pattern 103 is formed of a material different from that of the anti-oxidation spacer 109, most of the hard mask pattern 103 may remain.

Subsequently, an auxiliary buried insulating layer 114 may be formed on the entire surface of the substrate 100. The auxiliary buried insulating layer 114 may fill an etched region of the substrate 100 for forming the fin 105. The auxiliary buried insulating layer 114 may be formed of an HSQ film formed of a spin method or an SOG film such as polysilase-based.

The auxiliary buried insulating layer 114 is planarized until the fin 105 or the buffer insulating layer 101 is exposed, and the flattened auxiliary buried insulating layer 114 is recessed to form an auxiliary buried pattern 114a. The auxiliary buried pattern 114a fills a portion of the etched region of the substrate 100. The auxiliary buried pattern 114a may be formed to be close to an upper surface of the insulator 112.

A main buried insulating film 118 is formed on the substrate 100 having the auxiliary buried pattern 114a, and a conformal liner film 116 fills the etched region of the substrate 100 on the liner film 116. ). The liner layer 116 may be formed of an insulating material having an etch selectivity with respect to the main buried insulating layer 118. For example, the main buried insulating film 118 may be formed of a silicon oxide film, and the liner film 116 may be formed of a silicon nitride film.

9 and 10, the main buried insulating layer 118 and the liner layer 116 are planarized by using an upper surface of the buffer insulating layer 101 or the fin 105 as an etch stop layer. Accordingly, the planarized liner layer 116a and the main buried pattern 118a are formed on the sidewalls of the fin 103. The main buried insulating film 118 and the liner film 116 may be planarized by a chemical mechanical polishing process.

After the planarization, the buffer insulating layer 101 may be removed to expose the upper surface of the fin 105, and the upper surface of the fin 105 may be oxidized to form a capping insulating layer (not shown). . Of course, the process of forming the capping insulating layer may be omitted.

Subsequently, the planarized liner layer 116a is selectively recessed to form a liner 116a 'on a portion of the sidewall of the fin 105 to form a sacrificial insulating layer formed on an upper part of the fin 105. 107).

The exposed sacrificial insulating layer 107 is removed to expose the upper side wall of the fin 105. As a result, a groove is formed surrounded by the upper side wall of the fin 105, the top surface of the liner 116a 'and the main buried pattern 116a'.

Subsequently, a gate insulating film 119 shown in FIGS. 1 and 2 is formed, and a gate electrode 120 that crosses the fin 105 is formed on the gate insulating film 119. The gate electrode 120 fills in a groove located below it. Thus, the gate electrode 120 passes through both upper sidewalls and the upper surface of the fin 105.

When the capping insulating layer (not shown) is formed or the hard mask pattern 103 remains, they are formed higher than the thickness of the gate insulating layer 119, thereby forming a channel region under the gate electrode 120. It may be limited to both upper side walls of the pin 105.

Subsequently, impurity ions are implanted using the gate electrode 120 as a mask to form a source / drain region 122 shown in FIG. 1. The lower surface of the source / drain region 122 may contact the upper surface of the insulator 112 formed on the fin 105 or may have a height higher than that.

In the above-described method of forming the fin field effect transistor, after forming the fin 105 by etching the substrate 100, which is a bulk substrate, the lower part of the fin 105 using the anti-oxidation spacer 109. ) Is formed of an insulator 112. The insulator 112 may isolate the source / drain regions 122 and the substrate 100, thereby preventing a conventional leakage current and preventing formation of parasitic transistors. In addition, by not using a conventional high-cost SOI substrate, it is possible to reduce the production cost of the semiconductor product to improve productivity.

As described above, according to the present invention, the bulk substrate is selectively etched to form fins, and the lower part of the fin is formed of an insulator. As a result, the source / drain regions and the substrate are separated from each other, thereby preventing the conventional leakage current and preventing the formation of the conventional parasitic transistor, thereby improving the characteristics of the fin transistor. In addition, the fin field effect transistor according to the present invention does not require an expensive SOI substrate. Therefore, productivity can be improved by reducing the production cost of the semiconductor product.

1 is a perspective view illustrating a fin field effect transistor according to an exemplary embodiment of the present invention.

FIG. 2 is a cross-sectional view taken along the line II ′ of FIG. 1.

3 through 10 are process cross-sectional views taken along line II ′ of FIG. 1 to explain a method of forming a fin field effect transistor according to an embodiment of the present invention.

Claims (11)

A pin extending vertically from the substrate, the lower part of which is made of an insulator; A gate electrode across the pin; A gate insulating layer interposed between the gate electrode and the fin; And And a source / drain region formed in the fins on both sides of the gate electrode. The method of claim 1, And a portion of the insulator extends along the substrate surface around the fin. The method of claim 1, A liner formed on a sidewall of the fin, the liner formed on a portion of the sidewall of the fin so that the upper sidewall of the fin is exposed, and a main buried pattern having a higher top surface than the liner, wherein the gate electrode includes the fin And across an exposed upper part of the fin field effect transistor. The method of claim 3, wherein And a subsidiary buried pattern interposed between the liner and the substrate. The method of claim 1, And a lower surface of the source / drain region is at a height greater than or equal to an upper surface of the insulator. Selectively etching a substrate to form a fin extending vertically from the substrate; Forming a lower part of the pin with an insulator; Forming a gate electrode across the fin via a gate insulating film; And Forming a source / drain region in the fins on both sides of the gate electrode. The method of claim 6, Forming the pins and insulators, Forming a hardmask pattern on the substrate; Etching the substrate to form the fin using the hard mask pattern as a mask; Forming a sacrificial insulating layer on at least sidewalls of the fins and a substrate surface around the fins; Forming an anti-oxidation spacer on sidewalls of the fin and hard mask pattern through the sacrificial insulating layer; Removing at least the sacrificial insulating layer located below the bottom surface of the antioxidant spacer to expose a portion of the fin sidewalls; Performing an oxidation process on the substrate to form the insulator; Removing at least the antioxidant spacer; And Exposing at least an upper sidewall of the fin. The method of claim 7, wherein Before forming the insulator, And recessing sidewalls of the exposed fins. The method of claim 6, Before forming the gate insulating film, Conformally forming a liner film on the entire surface of the substrate; Forming a main buried insulating film filling the etched region of the substrate on the liner film; Planarizing the main buried insulating film and the liner film until the upper surface of the fin is exposed; And Selectively recessing the planarized liner film to expose an upper sidewall of the fin, wherein the gate electrode crosses the exposed top of the fin. The method of claim 9, Before forming the liner film, Forming an auxiliary buried insulating film filling the etched region of the substrate; Planarizing the auxiliary buried insulating film until the upper surface of the fin is exposed; And, And recessing the planarized auxiliary buried insulating layer to form an auxiliary buried pattern filling a portion of the etched region. The method of claim 6, Forming the source / drain region may include: Implanting impurity ions using the gate electrode as a mask to form the source / drain region, wherein a lower surface of the source / drain region is formed to have a height greater than or equal to an upper surface of the insulator; Method of forming a fin field effect transistor.