KR100695486B1 - Method for fabricating semiconductor device - Google Patents

Method for fabricating semiconductor device Download PDF

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KR100695486B1
KR100695486B1 KR1020050091573A KR20050091573A KR100695486B1 KR 100695486 B1 KR100695486 B1 KR 100695486B1 KR 1020050091573 A KR1020050091573 A KR 1020050091573A KR 20050091573 A KR20050091573 A KR 20050091573A KR 100695486 B1 KR100695486 B1 KR 100695486B1
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South Korea
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active region
fin active
semiconductor device
gate
fin
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KR1020050091573A
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Korean (ko)
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이래희
장세억
임관용
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26586—Bombardment with radiation with high-energy radiation producing ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A method for manufacturing a semiconductor device is provided to prevent SCE(Shot Channel Effect) by lowering the threshold voltage in a 3-gate fin cell transistor. A fin active region(102) is formed by selectively etching a semiconductor substrate(101). Si ions are implanted into the top corners of the fin active region. A gate insulating layer(105) is then formed by thermal oxidation. The Si ion-implantation processing has a tilt condition of 45 degree and a twist condition of 90~270 degree. Also, the Si ion-implantation processing is performed to an ion implantation energy of 20~50 KeV.

Description

반도체 소자 제조 방법{METHOD FOR FABRICATING SEMICONDUCTOR DEVICE}Semiconductor device manufacturing method {METHOD FOR FABRICATING SEMICONDUCTOR DEVICE}

도 1a 내지 도 1c는 본 발명에 따른 반도체 소자의 제조 공정을 나타낸 단면도.1A to 1C are cross-sectional views illustrating a manufacturing process of a semiconductor device according to the present invention.

* 도면의 주요부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings

101 : 반도체 기판 102 : 핀 활성영역101: semiconductor substrate 102: fin active region

103 : 소자분리막 104 : 비결정 실리콘영역103: device isolation film 104: amorphous silicon region

105 : 게이트 절연막 106 : 게이트 전도막105: gate insulating film 106: gate conductive film

본 발명은 반도체 제조 기술에 관한 것으로 특히, 반도체 소자 제조 공정 중, 3게이트 핀셀 트랜지스터(3-Gate Fin Cell Transistor)의 제조 공정에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor manufacturing technology, and more particularly, to a manufacturing process of a three-gate fin cell transistor during a semiconductor device manufacturing process.

반도체 산업에서 웨이퍼(Wafer)당 생산할 수 있는 칩(Chip) 또는 다이(Die) 의 숫자가 많을수록 원가경쟁에서 우위를 점할 수 있게 됨으로써 그 숫자를 늘리려는 노력은 어느 업체어서든 끊임없이 추구되는 방향이라 할 수 있다. 이러한 추세를 구현하기 위한 가장 직접적인 방법 중의 하나가 소자의 크기를 줄이는 것이다. 다시말해, 반도체 산업계에서는 경쟁적으로 회로의 선폭을 줄이는 작업을 전개하고 있다. 그러나 선폭을 줄임으로써 생기는 폐해들로 SCE(Short Channel Effect), PTB(Punch Through Breakdown), DIBL(Drain Induced Barrier Lowering) 및 GIDL(Gate Induced Drain Leakage)이 발생하였다. In the semiconductor industry, the more chips or dies that can be produced per wafer, the more competitive it can be in cost competition. Can be. One of the most direct ways to implement this trend is to reduce the size of the device. In other words, the semiconductor industry is competing to reduce the line width of circuits. However, the shortcomings caused by reducing the line width included Short Channel Effect (SCE), Punch Through Breakdown (PTB), Drain Induced Barrier Lowering (DIBL), and Gate Induced Drain Leakage (GIDL).

상기의 폐해를 해결하기 위해 트랜지스터의 채널 또는 소스/드레인 정션 부분에 불순물의 이온주입 농도를 조절하게 되는 것이 현재의 추세이다. 그러나 상기의 해결책은 낮은 채널 전류를 가져오게 됨으로써 극복되어야 할 새로운 문제점을 안고 있다. 따라서, 상기의 문제점을 해결하기 위해 3게이트 핀셀 트랜지스터(3-Gate Fin Cell Transistor)를 형성하는데, 상기 3게이트 핀셀 트랜지스터는 채널 전류를 늘리기 위한 방안이나, 문턱전압이 낮다는 것이 새로운 문제점으로 나타나고 있다.In order to solve the above problems, it is a current trend to control the ion implantation concentration of impurities in the channel or source / drain junction portion of the transistor. However, the above solution has new problems to be overcome by bringing low channel current. Therefore, in order to solve the above problem, a three-gate fin cell transistor is formed. The three-gate fin cell transistor has a new problem of increasing the channel current or having a low threshold voltage. .

종래의 핀 형태의 3게이트 핀셀 트랜지스터의 경우, 우수한 SCE 방지 현상을 가짐과 동시에 높은 채널 전류를 확보함으로써 소자의 고집적화와 특성 열화의 방지를 동시에 기할 수 있는 기술이다. 특히, 다마신(Damascine) 방식을 이용한 BT트랜지스터(Body Tied Transistor)의 경우 게이트 전극 형성을 위한 식각 공정이 용이한 기술로서 각광받고 있는 기술이다. In the conventional pin-type three-gate pin cell transistor, it is possible to simultaneously prevent high integration and characteristic deterioration of the device by securing a high channel current while having an excellent SCE prevention phenomenon. In particular, the BT Tid Transistor using the damascene method has been spotlighted as an easy etching process for forming a gate electrode.

상기 핀 형태를 갖는 3게이트 핀셀 트랜지스터의 채널 넓이인 핀 활성영역의 두께가 얇아지게되면 SS(Subthreshold Swing), DIBL 및 GIDL 특성이 향상되므로써 누설 전류 및 SCE를 개선할 수 있으나, 문턱 전압이 낮아지는 문제점이 발생된다.When the thickness of the fin active region, which is the channel width of the three-gate fin cell transistor having the fin shape, becomes thin, the SS (Subthreshold Swing), DIBL, and GIDL characteristics are improved, thereby improving leakage current and SCE, but lowering the threshold voltage Problems arise.

종래 기술에 따른 3게이트 핀셀 트랜지스터에 바이어스 전압을 인가하게 되면, 핀 활성영역의 상부 모서리 부분에 일렉트릭 필드(Electric Field)가 집중되기 때문에, 원하는 값보다 낮은 문턱 전압이 형성되고, 상기 낮은 문턱 전압으로 인한 누설 전류가 증가된다.When a bias voltage is applied to a three-gate pin cell transistor according to the prior art, since an electric field is concentrated at an upper edge portion of the fin active region, a threshold voltage lower than a desired value is formed, and the low threshold voltage is reduced. Leakage current is increased.

상기 누설 전류를 감소시키기 위해 채널의 도핑(Doping) 농도를 증가시키는데, 이 것은 리프레쉬(Refresh) 타임의 감소를 유발시키는 문제점이 된다In order to reduce the leakage current, the doping concentration of the channel is increased, which is a problem causing a decrease in the refresh time.

본 발명은 상기한 종래기술의 문제점을 해결하기 위해 제안된 것으로서, 두께가 얇은 핀 활성영역의 형성 및 낮은 문턱 전압을 갖는 반도체 소자의 제조 방법을 제공하는 것을 그 목적으로 한다.The present invention has been proposed to solve the above problems of the prior art, and an object thereof is to provide a method for manufacturing a semiconductor device having a thin fin active region and a low threshold voltage.

상기의 목적을 달성하기 위한 본 발명의 일측면에 따르면, 반도체 기판을 선택적 식각하여 핀 활성영역을 형성하는 단계, 상기 핀 활성영역의 상부 양모서리에 Si 이온주입하는 단계 및 열산화를 수행하여 게이트 절연막을 형성하는 단계를 포함하는 반도체 소자의 제조 방법이 제공된다.According to an aspect of the present invention for achieving the above object, forming a fin active region by selectively etching the semiconductor substrate, implanting Si ions into the upper both corners of the fin active region and performing a thermal oxidation gate There is provided a method of manufacturing a semiconductor device comprising forming an insulating film.

이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부 도면을 참조하여 설명하기로 한다.Hereinafter, the preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .

도 1a 내지 도 1c는 본 발명에 따른 반도체 소자의 제조 공정을 나타낸 단면도이다.1A to 1C are cross-sectional views illustrating a manufacturing process of a semiconductor device according to the present invention.

본 발명에 따른 반도체 소자의 제조 공정은 우선, 도 1에 도시된 바와 같이, 핀 활성영역(102)이 형성된 반도체 기판(101)을 준비한다.In the process of manufacturing a semiconductor device according to the present invention, first, as shown in FIG. 1, a semiconductor substrate 101 having a fin active region 102 is prepared.

상기 핀 활성영역(102)은 상기 반도체 기판(101) 상에 패드 산화막과 패드 질화막이 순차적으로 적층된 구조의 패드층을 형성하고, 상기 패드층을 선택적 식각하여 예비 핀 활성영역을 오픈한다.The fin active region 102 forms a pad layer having a structure in which a pad oxide layer and a pad nitride layer are sequentially stacked on the semiconductor substrate 101, and selectively opens the preliminary fin active region by selectively etching the pad layer.

이어서, 상기 패드층을 식각 장벽으로 상기 반도체 기판(101)을 식각하여 상기 핀 활성영역(102)을 형성한다.Subsequently, the semiconductor substrate 101 is etched using the pad layer as an etch barrier to form the fin active region 102.

이어서, 상기 핀 활성영역(102)이 형성된 상기 반도체 기판(101)의 전체 구조 상에 버퍼 산화막, 라이너 질화막 및 절연용 산화막을 순차적으로 증착하여 상기 반도체 기판(101)의 상기 핀 활성영역(102)에 의해 형성된 트렌치를 매립한다.Subsequently, a buffer oxide film, a liner nitride film, and an insulating oxide film are sequentially deposited on the entire structure of the semiconductor substrate 101 on which the fin active region 102 is formed, so that the fin active region 102 of the semiconductor substrate 101 is deposited. A trench formed by burying is embedded.

이때, 상기 버퍼 산화막, 라이너 질화막 및 절연용 산화막을 소자분리막(103)이라 칭한다.In this case, the buffer oxide film, the liner nitride film, and the insulating oxide film are referred to as an isolation layer 103.

다음으로, 도 1b에 도시된 바와 같이, 예비 게이트 전극 형성영역에 형성된 상기 소자분리막(103)을 식각하여 리세스부를 형성한다.Next, as shown in FIG. 1B, the device isolation layer 103 formed in the preliminary gate electrode formation region is etched to form a recess.

이어서, 상기 소자분리막(103)을 식각하여 노출된 상기 핀 활성영역(102)의 상부 모서리 부분에 Si 이온주입을 실시하여 비결정 실리콘영역(104)을 형성한다.Subsequently, the device isolation layer 103 is etched to implant Si ions into the exposed upper corners of the fin active regions 102 to form amorphous silicon regions 104.

이때, 상기 Si 이온주입 공정은 45°의 틸트 조건, 90~270°의 트위스트 조건으로 수행하고, 20~50keV의 이온주입 에너지로 수행하는 것이 바람직하다. 이에 의해 핀 활성영역(102)의 상부 모서리 부분은 타 부위에 대비하여 상대적으로 강한 이온 주입을 수행되어 비결정 실리콘영역(104)이 된다. At this time, the Si ion implantation process is performed under a tilt condition of 45 °, a twist condition of 90 ~ 270 °, it is preferable to perform with an ion implantation energy of 20 ~ 50keV. As a result, a relatively strong ion implantation is performed on the upper edge portion of the fin active region 102 to form the amorphous silicon region 104.

Si 이온이 상기 반도체 기판(101)에 이온주입되면, 단결정 실리콘 기판(상기 반도체 기판(101))의 실리콘간 결합고리가 끊기거나 느슨하게 되어 비결정상태로 변화된다. When Si ions are implanted into the semiconductor substrate 101, the inter-silicon bonds of the single crystal silicon substrate (the semiconductor substrate 101) are broken or loosened, thereby changing to an amorphous state.

다음으로 도 1c에 도시된 바와 같이, 상기 핀 활성영역(102)의 양측벽 및 상부 표면에 게이트 절연막을 형성하기 위하여 열산화 공정을 수행한다.Next, as illustrated in FIG. 1C, a thermal oxidation process is performed to form a gate insulating film on both sidewalls and the upper surface of the fin active region 102.

이때, 상기 핀 활성영역(102)의 상부 표면의 상기 게이트 절연막(105)이 상기 핀 활성영역(102)의 양측벽에 형성된 상기 게이트 절연막(105)보다 두껍게 형성된다.In this case, the gate insulating layer 105 on the upper surface of the fin active region 102 is formed thicker than the gate insulating layer 105 formed on both sidewalls of the fin active region 102.

이것은, 상기 Si 이온주입 공정으로 인하여 형성된 비결정 실리콘영역(104)과 Si 이온주입 공정을 수행하지 않은 일반적인 단결정 실리콘영역(상기 비결정 실리콘영역(104)을 제외한 상기 핀 활성영역(102))이 상기 열산화 공정시 성장 속도의 차이에 의해 두께 차이가 발생하는 것이다.This is because the amorphous silicon region 104 formed by the Si ion implantation process and the general single crystal silicon region (the fin active region 102 except for the amorphous silicon region 104) that do not perform the Si ion implantation process are the heat. The difference in thickness is caused by the difference in growth rate during the oxidation process.

즉, 상기 단결정 실리콘영역 보다 상기 비결정 실리콘영역(104)의 상기 열산화막(게이트 절연막)의 성장 속도가 빨라 상기 핀 활성영역(102)의 상부 표면의 상기 열산화막(게이트 절연막)이 두껍게 형성되는 것이다.That is, the thermal oxide film (gate insulating film) on the upper surface of the fin active region 102 is formed thicker than the single crystal silicon region because the growth rate of the thermal oxide film (gate insulating film) of the amorphous silicon region 104 is faster. .

여기서, 상기 핀 활성영역(102)의 상부 모서리 부분은 상기 핀 활성영역(102) 형성을 위한 식각 공정시 손상을 많이 받는 부분이라 스트레스가 집중되어 종래의 문제점인 낮은 문턱 전압의 제공처가 되기 때문에 상기 핀 활성영역(102) 상부 표면에 두껍게 형성된 상기 게이트 절연막(105)은 상기 문턱 전압을 상승시키는데 결론적으로 전체 소자의 문턱전압을 상승시키는 효과를 갖는다.Here, since the upper edge portion of the fin active region 102 is a damaged part during the etching process for forming the fin active region 102, stress is concentrated and thus provides a low threshold voltage which is a conventional problem. The gate insulating layer 105 thickly formed on the upper surface of the fin active region 102 increases the threshold voltage, and consequently has an effect of increasing the threshold voltage of the entire device.

이어서, 상기 게이트 절연막(105)을 덮고, 상기 핀 활성영역(102)와 교차되며, 상기 소자분리막(103)의 리세스부 상에 게이트 전도막(106)을 형성한다.Subsequently, the gate insulating layer 105 is covered, intersects with the fin active region 102, and a gate conductive layer 106 is formed on the recess portion of the device isolation layer 103.

이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes can be made in the art without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.

이상에서 살펴본 바와 같이, 본 발명은 SCE(Short Channel Effect) 방지 및 채널 전류량을 동시에 만족시키는 3게이트 핀셀 트랜지스터에서의 낮은 문턱 전압을 향상시켜 종래의 플레너(Planar) 트랜지스터에서 보여주는 문턱전압과 동일한 수준을 보여줌으로써 소자의 회로 구동 시 제품의 경제성을 만족시켜 줄 수 있게 된다. As described above, the present invention improves the low threshold voltage of the three-gate pin cell transistor that simultaneously satisfies the short channel effect (SCE) prevention and channel current amount, thereby achieving the same level as the threshold voltage shown in the conventional planar transistor. By showing, it is possible to satisfy the economics of the product when driving the circuit of the device.

Claims (3)

반도체 기판을 선택적 식각하여 핀 활성영역을 형성하는 단계;Selectively etching the semiconductor substrate to form a fin active region; 상기 핀 활성영역의 상부 양모서리에 Si 이온주입하는 단계; 및Implanting Si ions into the upper edges of the fin active region; And 열산화를 수행하여 게이트 절연막을 형성하는 단계Thermal oxidation to form a gate insulating film 를 포함하는 반도체 소자의 제조 방법.Method for manufacturing a semiconductor device comprising a. 제1항에 있어서,The method of claim 1, 상기 Si 이온주입 공정은 45°의 틸트 조건, 90~270°의 트위스트 조건으로 수행하는 것을 특징으로 하는 반도체 소자의 제조 방법.The Si ion implantation process is a semiconductor device manufacturing method, characterized in that carried out under a tilt condition of 45 °, twist conditions of 90 ~ 270 °. 상기 Si 이온주입 공정은 20~50keV의 이온주입 에너지로 수행하는 것을 특징으로 하는 반도체 소자의 제조 방법.The Si ion implantation process is a method of manufacturing a semiconductor device, characterized in that performed by the ion implantation energy of 20 ~ 50keV.
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Publication number Priority date Publication date Assignee Title
KR20040110817A (en) * 2003-06-20 2004-12-31 삼성전자주식회사 Dram memory cell having a gate channel extending vertically from a substrate and method of fabricating the same

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20040110817A (en) * 2003-06-20 2004-12-31 삼성전자주식회사 Dram memory cell having a gate channel extending vertically from a substrate and method of fabricating the same

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