JP3624629B2 - Bipolar level shift circuit - Google Patents

Bipolar level shift circuit Download PDF

Info

Publication number
JP3624629B2
JP3624629B2 JP15139997A JP15139997A JP3624629B2 JP 3624629 B2 JP3624629 B2 JP 3624629B2 JP 15139997 A JP15139997 A JP 15139997A JP 15139997 A JP15139997 A JP 15139997A JP 3624629 B2 JP3624629 B2 JP 3624629B2
Authority
JP
Japan
Prior art keywords
potential
circuit
type mosfet
electrode
low
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP15139997A
Other languages
Japanese (ja)
Other versions
JPH10341149A (en
Inventor
正美 橋本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP15139997A priority Critical patent/JP3624629B2/en
Publication of JPH10341149A publication Critical patent/JPH10341149A/en
Application granted granted Critical
Publication of JP3624629B2 publication Critical patent/JP3624629B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Landscapes

  • Logic Circuits (AREA)

Description

【０００１】
【発明の属する技術分野】
本発明は絶縁ゲート電界効果型トランジスタ（以下ＭＯＳＦＥＴと略す）を用いた半導体集積回半導体集積回路装置、もしくは該部品を用いた装置において、負極性および正極性の計４電位以上の電源を用い、各回路において異なる電位の低電圧系（小振幅）の信号を高電位系（大振幅）の信号に変換するレベルシフト回路の構成に関する。
【０００２】
【従来の技術】
従来の代表的なレベルシフト回路は図６の特公昭５７−５９６９０号公報の如く、片側の信号レベルのみの変換回路であった。あるいは小振幅を大振幅に変換するという意味においては図７のようにコンパレータ回路、もしくはオペアンプ回路で小振幅を電源の電位まで増幅して変換していた。
【０００３】
【発明が解決しようとする課題】
さて、前述した従来の片側のレベル信号レベルのみの変換回路では４電位以上の多電源の回路には適用できないという問題点があった。またコンパレータ回路もしくはオペアンプ回路による方法では常時、多大な電流が流れ続けるという問題点があった。
【０００４】
そこで本発明はこのような問題点を解決するもので、その目的とするところは４電位以上の多電源回路における低電位系（小振幅）の信号を高電位系（大振幅）の信号に、つまり正極性側も負極性側も同時に変換し、かつ一度変換された後にはリーク電流が存在しない回路構成、つまり低消費電力のレベルシフト回路を提供することである。
【０００５】
【課題を解決するための手段】
本発明の両極性レベルシフト回路は、低電位系の電源に接続され、かつ出力端子にダイオード手段を有した低電位系信号駆動回路と、高電位系の電源に接続され、インバータ回路をたすきがけした高電位系ラッチ回路からなり、前記低電位系信号駆動回路の信号を前記高電位系ラッチ回路に直接加えたことを特徴とする。
【０００６】
【作用】
本発明の上記の構成によれば、高電位系ラッチ回路はインバータ回路のたすきがけで出来ているので、低電位系信号駆動回路の信号によって高電位系のラッチ回路を反転することができる。また、低電位系信号駆動回路の出力端子にはダイオード手段を有しているので高電位系の電源から低電位系の電源への逆流が防げる。以上によりリーク電流のない低消費電力の両極性のレベル変換ができる。
【０００７】
【発明の実施の形態】
以下、実施例により本発明の詳細を示す。図１は本発明の第１の実施例を示す回路図である。図１において破線２０に囲まれた中の回路は低電位系信号駆動回路である。低電位系信号駆動回路２０は−ＶＳＳ１、＋ＶＤＤ１の電源を用いている。破線２３に囲まれた回路は高電位系ラッチ回路である。高電位系ラッチ回路２３は−ＶＳＳ２、＋ＶＤＤ２の電源を用いている。ここで−ＶＳＳ２、−ＶＳＳ１、＋ＶＤＤ１、＋ＶＤＤ２の各電源電位の関係を図示したのが図２である。図２において−ＶＳＳ２は負極性の第２電源電位、−ＶＳＳ１は負極性の第１電源電位、＋ＶＤＤ１は正極性の第１電源電位、＋ＶＤＤ２は正極性の第２電位である。さて、図１の破線２０の中において１１、１２はＰ型ＭＯＳＦＥＴであり、１３、１４はＮ型ＭＯＳＦＥＴである。Ｐ型ＭＯＳＦＥＴ１１のソース電極は＋ＶＤＤ１に接続され、ドレイン電極はＰ型ＭＯＳＦＥＴ１２のソース電極に接続されている。Ｐ型ＭＯＳＦＥＴ１２のゲート電極とドレイン電極は互いに接続されている。Ｎ型ＭＯＳＦＥＴ１３のソース電極は−ＶＳＳ１に接続され、ドレイン電極はＮ型ＭＯＳＦＥＴ１４のソース電極に接続されている。Ｎ型ＭＯＳＦＥＴ１４のゲート電極とドレイン電極は互いに接続され、かつＰ型ＭＯＳＦＥＴ１２のドレイン電極に接続されているとともに低電位系信号駆動回路２０の出力端子２２となっている。またＰ型ＭＯＳＦＥＴ１１とＮ型ＭＯＳＦＥＴ１３のそれぞれのゲート電極は互いに接続されれ、かつ低電位系信号駆動回路２０の入力端子２１となっている。なお、ＭＯＳＦＥＴ１１、１２、１５、１６、１７、１８の基板電位はソース電位と同一電位となるように接続されているが、ＭＯＳＦＥＴ１２、１４は例外であって、Ｐ型ＭＯＳＦＥＴ１２の基板は＋ＶＤＤ２に、Ｎ型ＭＯＳＦＥＴ１４の基板は−ＶＳＳ２に接続されている。また、破線２３の中において、１５、１６はＰ型ＭＯＳＦＥＴであり、Ｎ型ＭＯＳＦＥＴ１７、１８はＮ型ＭＯＳＦＥＴである。Ｐ型ＭＯＳＦＥＴ１５、１６のソース電極は＋ＶＤＤ２に接続されている。Ｎ型ＭＯＳＦＥＴ１７、１８のソース電極は−ＶＳＳ２に接続されている。Ｐ型ＭＯＳＦＥＴ１５とＮ型ＭＯＳＦＥＴ１７のゲート電極とドレイン電極はともにそれぞれ接続され、第１のインバータ回路を形成している。またＰ型ＭＯＳＦＥＴ１６とＮ型ＭＯＳＦＥＴ１８のゲート電極とドレイン電極はともにそれぞれ接続され、第２のインバータ回路を形成している。また第１のインバータ回路の出力端子は高電位系ラッチ回路２３の反転出力端子２４となっているとともに第２のインバータ回路のゲート入力端子に接続されている。また第２のインバータ回路の出力端子は高電位系ラッチ回路２３の出力端子２５となっているとともに第１のインバータ回路のゲート入力端子に接続されている。
【０００８】
さて、低電位系信号駆動回路２０の入力端子２１に正の極性の信号が入力したとすると、出力端子２２には−ＶＳＳ１もしくはＮ型ＭＯＳＦＥＴ１４のスレッショルド電圧分だけ降下（上昇）した電位が発生し、高電位系ラッチ回路２３の反転出力端子２４に加わる。このとき、Ｐ型ＭＯＳＦＥＴ１５の駆動能力より、Ｎ型ＭＯＳＦＥＴ１３、１４の駆動能力を充分に高く設定しておくと、Ｐ型ＭＯＳＦＥＴ１６とＮ型ＭＯＳＦＥＴ１８からなる第２のインバータ回路は反転して出力端子２５に＋ＶＤＤ２を出力するとともにＰ型ＭＯＳＦＥＴ１５とＮ型ＭＯＳＦＥＴ１７からなる第１のインバータ回路も反転して反転出力端子２４は−ＶＳＳ２となる。なお、このときＮ型ＭＯＳＦＥＴ１４のソース電極とドレイン電極に−ＶＳＳ２と−ＶＳＳ１が加わることになるが、ゲート電極が接続されている電極側に−ＶＳＳ２が加わっているので電流が流れることはない。低電位系信号駆動回路２０の入力端子２１に負の極性の信号が入力した場合には以上のほぼ逆なことが起こり、出力端子２５には＋ＶＤＤ２が出力され、Ｐ型ＭＯＳＦＥＴ１２のソース電極とドレイン電極に＋ＶＤＤ２と＋ＶＤＤ１が加わることになるが、ゲート電極が接続されている電極側に＋ＶＤＤ２が加わっているので電流が流れることはない。以上より、−ＶＳＳ１、＋ＶＤＤ１の低電位系信号駆動回路２０の信号が高電位系ラッチ回路２３を経ることにより、−ＶＳＳ２、＋ＶＤＤ２の信号に置き変わり、かつ静止状態においてはリーク電流の生じない両極性のレベルシフト回路となっていることが解る。
【０００９】
図３は本発明の第２の実施例である。図３の破線で示す低電位系信号駆動回路３０の中の３２、３４はＰ＋拡散とＮ＋拡散からなるダイオードであり、図１のＭＯＳＦＥＴ１２、１４を置き換えたものである。
【００１０】
図４は本発明の第３の実施例である。図４において、４０、４１はともに低電位系信号駆動回路である。第１の低電位系信号駆動回路４０は図１の回路と同様であるが、図４の第２の低電位系信号駆動回路４１の入力端子にはインバータ回路４９を通した反転信号が加えられ、出力端子４６は高電位系ラッチ回路４３の出力端子４５に加えられている。この回路手法では高電位系ラッチ回路４３に二本の差動信号が入力するので応答性が高まる特長がある。
【００１１】
図５は本発明の第４の実施例である。図５においては図４のインバータ回路４９を省略して第１の低電位系信号駆動回路５０から第２の低電位系信号駆動回路５１の入力信号を得ている。この回路は図４の回路に比較して若干素子数が減少する特長がある。
【００１２】
また、以上は計４電位の場合を説明してきたが、５電位以上であってその間のレベル変換であってもよい。
【００１３】
【発明の効果】
以上、述べたように本発明によれば、低電位系（小振幅）の信号を高電位系（大振幅）の信号に正極側と負極側同時に変換できるという効果がある。
【００１４】
また、動作が終了した静止状態においてはリーク電流が流れず、低消費電力であるという効果がある。
【図面の簡単な説明】
【図１】本発明の第１の実施例を示す回路図である。
【図２】本発明が使用される多電源系の各電位の関係を示した電位関係図である。
【図３】本発明の第２の実施例を示す回路図である。
【図４】本発明の第３の実施例を示す回路図である。
【図５】本発明の第４の実施例を示す回路図である。
【図６】従来例のレベルシフト回路を示す回路図である。
【図７】従来例の小振幅を大振幅に変換する回路例を示す回路図である。
【符号の説明】
１１、１２、１５、１６・・・Ｐ型ＭＯＳＦＥＴ
１３、１４、１７、１８・・・Ｎ型ＭＯＳＦＥＴ
２０、３０、４０、４１、５０、５１・・・低電位系信号駆動回路
２１、２２、２４、２５、４５、４６・・・端子
２３、４３・・・高電位系ラッチ回路
４９・・・インバータ回路[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor integrated circuit semiconductor integrated circuit device using an insulated gate field effect transistor (hereinafter abbreviated as MOSFET), or a device using the component, using a power source having a total of four or more potentials of negative polarity and positive polarity, The present invention relates to a configuration of a level shift circuit that converts a low voltage (small amplitude) signal having a different potential into a high potential (large amplitude) signal in each circuit.
[0002]
[Prior art]
A conventional typical level shift circuit is a conversion circuit only for a signal level on one side as disclosed in Japanese Patent Publication No. 57-59690 in FIG. Alternatively, in the sense of converting a small amplitude to a large amplitude, the small amplitude is amplified and converted to the potential of the power source by a comparator circuit or an operational amplifier circuit as shown in FIG.
[0003]
[Problems to be solved by the invention]
The conventional conversion circuit having only one level signal level described above cannot be applied to a multi-power supply circuit having four or more potentials. Further, the method using the comparator circuit or the operational amplifier circuit has a problem that a large current always flows.
[0004]
Therefore, the present invention solves such a problem, and its object is to convert a low potential system (small amplitude) signal in a multi-power supply circuit of 4 potentials or more into a high potential system (large amplitude) signal. That is, it is to provide a circuit configuration in which both the positive polarity side and the negative polarity side are converted at the same time, and there is no leakage current after the conversion, that is, a level shift circuit with low power consumption.
[0005]
[Means for Solving the Problems]
The bipolar level shift circuit of the present invention is connected to a low potential power supply and has a diode means at the output terminal, and is connected to a high potential power supply to bypass the inverter circuit. The low potential signal driving circuit is directly applied to the high potential latch circuit.
[0006]
[Action]
According to the above configuration of the present invention, the high-potential latch circuit is made of an inverter circuit, so that the high-potential latch circuit can be inverted by a signal from the low-potential signal drive circuit. Further, since the output terminal of the low-potential signal driving circuit has diode means, it is possible to prevent a back flow from the high-potential power supply to the low-potential power supply. As described above, it is possible to perform bipolar power level conversion with low power consumption and no leakage current.
[0007]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, details of the present invention will be described by way of examples. FIG. 1 is a circuit diagram showing a first embodiment of the present invention. In FIG. 1, a circuit surrounded by a broken line 20 is a low potential signal driving circuit. The low-potential signal drive circuit 20 uses power sources of −V SS1 and + V DD1 . A circuit surrounded by a broken line 23 is a high potential latch circuit. The high potential system latch circuit 23 uses power sources of −V SS2 and + V DD2 . Here, FIG. 2 shows the relationship between the power supply potentials of −V SS2 , −V SS1 , + V DD1 , and + V DD2 . In FIG. 2, −V SS2 is a negative second power supply potential, −V SS1 is a negative first power supply potential, + V DD1 is a positive first power supply potential, and + V DD2 is a positive second potential. In the broken line 20 in FIG. 1, 11 and 12 are P-type MOSFETs, and 13 and 14 are N-type MOSFETs. The source electrode of the P-type MOSFET 11 is connected to + V DD1 , and the drain electrode is connected to the source electrode of the P-type MOSFET 12. The gate electrode and the drain electrode of the P-type MOSFET 12 are connected to each other. The source electrode of the N-type MOSFET 13 is connected to −V SS1 , and the drain electrode is connected to the source electrode of the N-type MOSFET 14. The gate electrode and the drain electrode of the N-type MOSFET 14 are connected to each other, are connected to the drain electrode of the P-type MOSFET 12, and serve as the output terminal 22 of the low potential signal drive circuit 20. The gate electrodes of the P-type MOSFET 11 and the N-type MOSFET 13 are connected to each other and serve as the input terminal 21 of the low-potential signal driving circuit 20. The substrate potentials of the MOSFETs 11, 12, 15, 16, 17, and 18 are connected so as to be the same potential as the source potential. However, the MOSFETs 12 and 14 are an exception, and the substrate of the P-type MOSFET 12 is at + V DD2 . The substrate of the N-type MOSFET 14 is connected to −V SS2 . Moreover, in the broken line 23, 15 and 16 are P-type MOSFETs, and N-type MOSFETs 17 and 18 are N-type MOSFETs. The source electrodes of the P-type MOSFETs 15 and 16 are connected to + V DD2 . The source electrodes of the N-type MOSFETs 17 and 18 are connected to −V SS2 . The gate electrode and the drain electrode of the P-type MOSFET 15 and the N-type MOSFET 17 are both connected to form a first inverter circuit. Further, the gate electrode and the drain electrode of the P-type MOSFET 16 and the N-type MOSFET 18 are respectively connected to form a second inverter circuit. The output terminal of the first inverter circuit is the inverting output terminal 24 of the high-potential latch circuit 23 and is connected to the gate input terminal of the second inverter circuit. The output terminal of the second inverter circuit is the output terminal 25 of the high-potential latch circuit 23 and is connected to the gate input terminal of the first inverter circuit.
[0008]
If a positive polarity signal is input to the input terminal 21 of the low potential signal drive circuit 20, a potential that is lowered (increased) by the threshold voltage of −V SS1 or the N-type MOSFET 14 is generated at the output terminal 22. Then, it is applied to the inverting output terminal 24 of the high potential system latch circuit 23. At this time, if the drive capability of the N-type MOSFETs 13 and 14 is set sufficiently higher than the drive capability of the P-type MOSFET 15, the second inverter circuit composed of the P-type MOSFET 16 and the N-type MOSFET 18 is inverted and the output terminal 25 is inverted. + V DD2 is output to the first inverter circuit composed of the P-type MOSFET 15 and the N-type MOSFET 17 and the inverted output terminal 24 becomes −V SS2 . At this time, −V SS2 and −V SS1 are added to the source electrode and the drain electrode of the N-type MOSFET 14, but a current flows because −V SS2 is added to the electrode side to which the gate electrode is connected. There is no. When a negative polarity signal is input to the input terminal 21 of the low-potential signal drive circuit 20, almost the reverse of the above occurs, and + V DD2 is output to the output terminal 25, and the source electrode of the P-type MOSFET 12 Although + V DD2 and + V DD1 are added to the drain electrode, current does not flow because + V DD2 is added to the electrode side to which the gate electrode is connected. As described above, the signal of the low potential signal drive circuit 20 of −V SS1 and + V DD1 passes through the high potential system latch circuit 23 to be replaced with the signals of −V SS2 and + V DD2 , and leak current in a stationary state. It can be seen that this is a bipolar level shift circuit that does not cause the above.
[0009]
FIG. 3 shows a second embodiment of the present invention. Reference numerals 32 and 34 in the low-potential signal drive circuit 30 indicated by broken lines in FIG. 3 are diodes composed of P + diffusion and N + diffusion, which replace the MOSFETs 12 and 14 in FIG.
[0010]
FIG. 4 shows a third embodiment of the present invention. In FIG. 4, 40 and 41 are both low-potential signal drive circuits. The first low-potential signal drive circuit 40 is the same as the circuit of FIG. 1, but an inverted signal through the inverter circuit 49 is applied to the input terminal of the second low-potential signal drive circuit 41 of FIG. The output terminal 46 is added to the output terminal 45 of the high potential latch circuit 43. This circuit technique has an advantage that the response is improved because two differential signals are input to the high potential latch circuit 43.
[0011]
FIG. 5 shows a fourth embodiment of the present invention. In FIG. 5, the inverter circuit 49 of FIG. 4 is omitted, and the input signal of the second low potential signal driving circuit 51 is obtained from the first low potential signal driving circuit 50. This circuit has a feature that the number of elements is slightly reduced as compared with the circuit of FIG.
[0012]
Further, the case of a total of 4 potentials has been described above, but the level conversion between 5 potentials or more may be used.
[0013]
【The invention's effect】
As described above, according to the present invention, there is an effect that a low potential system (small amplitude) signal can be simultaneously converted into a high potential system (large amplitude) signal on the positive electrode side and the negative electrode side.
[0014]
In addition, there is an effect that the leakage current does not flow in the stationary state after the operation is completed, and the power consumption is low.
[Brief description of the drawings]
FIG. 1 is a circuit diagram showing a first embodiment of the present invention.
FIG. 2 is a potential relationship diagram showing a relationship between potentials of a multi-power supply system in which the present invention is used.
FIG. 3 is a circuit diagram showing a second embodiment of the present invention.
FIG. 4 is a circuit diagram showing a third embodiment of the present invention.
FIG. 5 is a circuit diagram showing a fourth embodiment of the present invention.
FIG. 6 is a circuit diagram showing a conventional level shift circuit.
FIG. 7 is a circuit diagram showing a circuit example for converting a small amplitude into a large amplitude in the conventional example.
[Explanation of symbols]
11, 12, 15, 16 ... P-type MOSFET
13, 14, 17, 18 ... N-type MOSFET
20, 30, 40, 41, 50, 51... Low-potential signal drive circuit 21, 22, 24, 25, 45, 46... Terminals 23, 43. Inverter circuit

Claims (5)

ａ）第１、第２、第３、第４の各電位の電源電位を有する絶縁ゲート電界効果型トランジスタ（以下ＭＯＳＦＥＴと略す）を用いた半導体集積回路装置において、
ｂ）第４電位の電源にソース電位を接続した第１、第２Ｐ型ＭＯＳＦＥＴと第１電位の電源にソース電位を接続した第１、第２Ｎ型ＭＯＳＦＥＴとからなり、前記第１Ｐ型ＭＯＳＦＥＴと第１Ｎ型ＭＯＳＦＥＴのそれぞれのゲート電極、およびドレイン電極は互いに接続され第１インバータ回路を形成し、前記第２Ｐ型ＭＯＳＦＥＴと第２Ｎ型ＭＯＳＦＥＴのそれぞれのゲート電極、およびドレイン電極は互いに接続され第２インバータ回路を形成し、該第１、第２インバータ回路の入力端子となるゲート電極と出力端子となるドレイン電極はそれぞれ互いにたすきがけに接続されている以上の構成からなる高電位系ラッチ回路と、
ｃ）第３電位の電源にソース電極を接続した第３Ｐ型ＭＯＳＦＥＴと、前記第３Ｐ型ＭＯＳＦＥＴのドレイン電極に正側の電極を接続した第１のダイオード手段と、前記第１のダイオード手段の負側の電極に正側の電極を接続した第２のダイオード手段と、前記第２のダイオード手段の負側の電極にドレイン電極を接続し、かつソース電極は第２電位の電源に接続した第３Ｎ型ＭＯＳＦＥＴとからなり、前記第３Ｐ型ＭＯＳＦＥＴと第３Ｎ型ＭＯＳＦＥＴのゲート電極は互いに接続され低電位系の信号入力端子となり、前記第１のダイオードと第２のダイオードの接続点が出力端子となっている以上の構成からなる低電位系信号駆動回路とからなり、
ｄ）前記低電位系信号駆動回路の出力端子が前記高電位系ラッチ回路の反転出力端子に接続されていることを特徴とする両極性レベルシフト回路。a) In a semiconductor integrated circuit device using an insulated gate field effect transistor (hereinafter abbreviated as MOSFET) having power supply potentials of first, second, third and fourth potentials,
b) First and second P-type MOSFETs having a source potential connected to a fourth potential power source and first and second N-type MOSFETs having a source potential connected to a first potential power source. Each gate electrode and drain electrode of the 1N-type MOSFET are connected to each other to form a first inverter circuit, and each gate electrode and drain electrode of the second P-type MOSFET and the second N-type MOSFET are connected to each other to form a second inverter. A high-potential latch circuit having the above-described configuration, in which a circuit is formed, and a gate electrode serving as an input terminal and a drain electrode serving as an output terminal of the first and second inverter circuits are connected to each other.
c) a third P-type MOSFET having a source electrode connected to a power supply of a third potential; a first diode means having a positive electrode connected to the drain electrode of the third P-type MOSFET; and a negative polarity of the first diode means. A second diode means having a positive electrode connected to the side electrode; a third N having a drain electrode connected to the negative electrode of the second diode means and a source electrode connected to a power supply of a second potential; A gate electrode of the third P-type MOSFET and the third N-type MOSFET are connected to each other to serve as a low-potential signal input terminal, and a connection point between the first diode and the second diode serves as an output terminal. It consists of a low-potential signal drive circuit with the above configuration,
d) A bipolar level shift circuit characterized in that an output terminal of the low potential signal driving circuit is connected to an inverting output terminal of the high potential latch circuit. 請求項１記載のダイオード手段がゲート電極とドレイン電極を互いに接続したＭＯＳＦＥＴからなることを特徴とする両極性レベルシフト回路。2. The bipolar level shift circuit according to claim 1, wherein the diode means comprises a MOSFET having a gate electrode and a drain electrode connected to each other. ａ）第１、第２、第３、第４の各電位の電源電位を有する絶縁ゲート電界効果型トランジスタ（以下ＭＯＳＦＥＴと略す）を用いた半導体集積回路装置において、
ｂ）第４電位の電源にソース電位を接続した第１、第２Ｐ型ＭＯＳＦＥＴと第１電位の電源にソース電位を接続した第１、第２Ｎ型ＭＯＳＦＥＴとからなり、前記第１Ｐ型ＭＯＳＦＥＴと第１Ｎ型ＭＯＳＦＥＴのそれぞれのゲート電極、およびドレイン電極は互いに接続され第１インバータ回路を形成し、前記第２Ｐ型ＭＯＳＦＥＴと第２Ｎ型ＭＯＳＦＥＴのそれぞれのゲート電極、およびドレイン電極は互いに接続され第２インバータ回路を形成し、該第１、第２インバータ回路の入力端子となるゲート電極と出力端子となるドレイン電極はそれぞれ互いにたすきがけに接続されている以上の構成からなる高電位系ラッチ回路と、
ｃ）第３電位の電源にソース電極を接続した第３Ｐ型ＭＯＳＦＥＴと、前記第３Ｐ型ＭＯＳＦＥＴのドレイン電極に正側の電極を接続した第１のダイオード手段と、前記第１のダイオード手段の負側の電極に正側の電極を接続した第２のダイオード手段と、前記第２のダイオード手段の負側の電極にドレイン電極を接続し、かつソース電極は第２電位の電源に接続した第３Ｎ型ＭＯＳＦＥＴとからなり、前記第３Ｐ型ＭＯＳＦＥＴと第３Ｎ型ＭＯＳＦＥＴのゲート電極は互いに接続され低電位系の信号入力端子となり、前記第１のダイオードと第２のダイオードの接続点が出力端子となっている以上の構成からなる第１低電位系信号駆動回路と、
ｄ）第３電位の電源にソース電極を接続した第４Ｐ型ＭＯＳＦＥＴと、前記第４Ｐ型ＭＯＳＦＥＴのドレイン電極に正側の電極を接続した第３のダイオード手段と、前記第３のダイオード手段の負側の電極に正側の電極を接続した第４のダイオード手段と、前記第４のダイオード手段の負側の電極にドレイン電極を接続し、かつソース電極は第２電位の電源に接続した第４Ｎ型ＭＯＳＦＥＴとからなり、前記第４Ｐ型ＭＯＳＦＥＴと第４Ｎ型ＭＯＳＦＥＴのゲート電極は互いに接続され低電位系の信号入力端子となり、前記第３のダイオードと第４のダイオードの接続点が出力端子となっている以上の構成からなる第２低電位系信号駆動回路とからなり、
ｅ）前記第２低電位系信号駆動回路の入力端子には前記第１低電位系信号駆動回路の入力端子とは反転した信号が加えられ、前記第１低電位系信号駆動回路の出力端子が前記高電位系ラッチ回路の反転出力端子に接続され、前記第２低電位系信号駆動回路の出力端子が前記高電位系ラッチ回路の出力端子に接続されていることを特徴とする両極性レベルシフト回路。a) In a semiconductor integrated circuit device using an insulated gate field effect transistor (hereinafter abbreviated as MOSFET) having power supply potentials of first, second, third and fourth potentials,
b) First and second P-type MOSFETs having a source potential connected to a fourth potential power source and first and second N-type MOSFETs having a source potential connected to a first potential power source. Each gate electrode and drain electrode of the 1N-type MOSFET are connected to each other to form a first inverter circuit, and each gate electrode and drain electrode of the second P-type MOSFET and the second N-type MOSFET are connected to each other to form a second inverter. A high-potential latch circuit having the above-described configuration, in which a circuit is formed, and a gate electrode serving as an input terminal and a drain electrode serving as an output terminal of the first and second inverter circuits are connected to each other.
c) a third P-type MOSFET having a source electrode connected to a power supply of a third potential; a first diode means having a positive electrode connected to the drain electrode of the third P-type MOSFET; and a negative polarity of the first diode means. A second diode means having a positive electrode connected to the side electrode; a third N having a drain electrode connected to the negative electrode of the second diode means and a source electrode connected to a power supply of a second potential; A gate electrode of the third P-type MOSFET and the third N-type MOSFET are connected to each other to serve as a low-potential signal input terminal, and a connection point between the first diode and the second diode serves as an output terminal. A first low-potential signal drive circuit having the above configuration;
d) a fourth P-type MOSFET having a source electrode connected to a power supply of a third potential; a third diode means having a positive electrode connected to the drain electrode of the fourth P-type MOSFET; and a negative polarity of the third diode means. A fourth diode means in which a positive electrode is connected to a side electrode; a fourth N means having a drain electrode connected to the negative electrode of the fourth diode means and a source electrode connected to a power supply of a second potential; A gate electrode of the fourth P-type MOSFET and the fourth N-type MOSFET are connected to each other to serve as a low-potential signal input terminal, and a connection point between the third diode and the fourth diode serves as an output terminal. A second low-potential signal driving circuit having the above configuration,
e) A signal inverted from the input terminal of the first low potential signal driving circuit is applied to the input terminal of the second low potential signal driving circuit, and the output terminal of the first low potential signal driving circuit is Bipolar level shift characterized in that it is connected to the inverting output terminal of the high potential system latch circuit and the output terminal of the second low potential system signal drive circuit is connected to the output terminal of the high potential system latch circuit. circuit. 請求項３記載のダイオード手段がゲート電極とドレイン電極を互いに接続したＭＯＳＦＥＴからなることを特徴とする両極性レベルシフト回路。4. The bipolar level shift circuit according to claim 3, wherein the diode means comprises a MOSFET having a gate electrode and a drain electrode connected to each other. 請求項３記載の第２低電位系信号駆動回路の入力端子に加えられる信号が第１低電位系信号駆動回路から形成されることを特徴とする両極性レベルシフト回路。4. The bipolar level shift circuit according to claim 3, wherein a signal applied to an input terminal of the second low potential signal drive circuit is formed from the first low potential signal drive circuit.
JP15139997A 1997-06-09 1997-06-09 Bipolar level shift circuit Expired - Fee Related JP3624629B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15139997A JP3624629B2 (en) 1997-06-09 1997-06-09 Bipolar level shift circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15139997A JP3624629B2 (en) 1997-06-09 1997-06-09 Bipolar level shift circuit

Publications (2)

Publication Number Publication Date
JPH10341149A JPH10341149A (en) 1998-12-22
JP3624629B2 true JP3624629B2 (en) 2005-03-02

Family

ID=15517747

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15139997A Expired - Fee Related JP3624629B2 (en) 1997-06-09 1997-06-09 Bipolar level shift circuit

Country Status (1)

Country Link
JP (1) JP3624629B2 (en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3469838B2 (en) * 2000-01-26 2003-11-25 三洋電機株式会社 Level shift circuit
JP4249597B2 (en) * 2003-11-13 2009-04-02 新日本無線株式会社 Level shift circuit
US7049876B2 (en) 2004-10-25 2006-05-23 Delphi Technologies, Inc. Level shift circuits and related methods
JP4923886B2 (en) * 2006-09-08 2012-04-25 富士電機株式会社 Level shift circuit and DC-DC converter
CN106899289B (en) * 2017-02-23 2019-01-29 电子科技大学 A kind of controllable type level displacement circuit

Also Published As

Publication number Publication date
JPH10341149A (en) 1998-12-22

Similar Documents

Publication Publication Date Title
KR940001251B1 (en) Voltage control circuit
US4994886A (en) Composite MOS transistor and application to a free-wheel diode
CN101826794A (en) Reverse current prevention circuit and power supply switching apparatus
US20080218250A1 (en) Charge pump circuit
KR19990044929A (en) Semiconductor integrated circuit device
JPS58119232A (en) Signal generating circuit
JP2701546B2 (en) Charge transfer device having signal charge detection circuit
JP3624629B2 (en) Bipolar level shift circuit
JPH08204536A (en) Interface circuit and level conversion circuit
US6586981B2 (en) Dynamic flip flop
CN112803721A (en) Voltage converter
JP3036423B2 (en) Semiconductor device
JP3626083B2 (en) Charge transfer device
JP3624630B2 (en) Bipolar level shift circuit
JP3698040B2 (en) Bipolar level shift circuit
JP3864526B2 (en) Semiconductor device and electronic equipment
JPS62160750A (en) Substrate-voltage generating circuit
CN220492858U (en) Push-pull type output circuit for preventing reverse input electric leakage
JP3666184B2 (en) Pass transistor logic semiconductor device
JPH04304011A (en) Interface circuit for isolator
JPH06224735A (en) Output interface circuit
JPH098638A (en) Cmos input/output buffer circuit
JPH0666608B2 (en) Non-inverting relay amplifier for use in semiconductor interconnect circuits.
JP3666214B2 (en) Pass transistor logic circuit
KR890005033Y1 (en) Cmos accumulation of opposite electric current output circuit

Legal Events

Date Code Title Description
A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20041014

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20041109

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20041122

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20081210

Year of fee payment: 4

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20091210

Year of fee payment: 5

LAPS Cancellation because of no payment of annual fees