JP3666214B2 - Pass transistor logic circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor integrated circuit device having a pass transistor logic circuit, wherein a pass transistor tree circuit constituting a logic in the pass transistor logic circuit and a buffer circuit for a signal input to the pass transistor tree circuit are reduced in number of transistors. The present invention relates to a circuit configuration for realizing the number of wirings.
[0002]
[Prior art]
First, a typical example of a single rail system in a conventional pass transistor logic circuit is shown in FIG. FIG. 8 is a method called SPL (Single Rail Pass-Transistor Logic), which is a method announced by Kobe University in 1995. In the circuit example of FIG. 8, the function of the calculation result of the carry of the full adder is configured by a pass transistor logic, which is composed of a pass transistor tree circuit 801 and a potential compensation circuit 802. The pass transistor tree circuit 801 is all N-type. It is composed of an insulated gate field effect transistor (hereinafter abbreviated as MOSFET).
[0003]
Note that FIG. 8 is published as a reference in the IEICE Technical Report Technical Report of IEICE. VLD95-115 (1995-12).
[0004]
A typical example of a conventional pass transistor logic circuit having a potential compensation circuit of a double rail system that outputs two signals of a logic function and an inverted logic function of the logic function is shown in FIGS. Shown in FIG. 9 is called SRPL (Swing Restored Pass-transistor Logic), which is a method announced by Toshiba in 1994. FIG. 10 is a method called DCVSPG (Differential Cascodes Voltage Switch with Pass-Gate), which is a method announced by IBM in 1993. The circuit examples of FIGS. 9 and 10 both have the function of the addition result of the full adder configured by pass transistor logic, and pass transistor tree circuits 931 (FIG. 9), 1041 (FIG. 10) and potential compensation circuit 932 (FIG. 9) and 1042 (FIG. 10), and the pass transistor tree circuit is composed of N-type MOSFETs. In addition, as a reference about the outline of FIG. 9 and FIG. 10 and a general pass transistor logic circuit, technical white paper pages 98-104 of 1994 Nikkei BP, separate edition “Low Power LSI” edited by Nikkei Microdevices. is there.
[0005]
[Problems to be solved by the invention]
Since the pass transistor tree circuits shown in FIGS. 8, 9, and 10 are all formed of N-type MOSFETs, the gates of the N-type MOSFETs have their respective inverted signals in addition to signals A and B. It was also necessary to input the signal (-A) and the signal (-B). Therefore, there is a problem that the number of MOSFETs of the inverting circuit and the wiring for the inverting signal are large.
[0006]
In addition, since there are many extra circuits and wiring, there is a problem that signal delay and power consumption increase.
[0007]
The present invention solves such problems, and an object of the present invention is to provide a pass transistor logic circuit having a small number of transistors and a small number of wires.
[0008]
As a result, a pass transistor logic circuit with low signal delay and low power consumption is provided.
[0009]
[Means for Solving the Problems]
In the pass transistor logic circuit of the present invention, in the pass transistor tree circuit, or in the pass transistor logic circuit and the potential compensation circuit, the use of the inverted signal in the gate input signal is achieved by using a positive logic element in addition to the MOSFET that is originally an inverting element. It is characterized by having reduced.
[0010]
[Action]
According to the above configuration of the present invention, in the pass transistor tree circuit, when the inverted signal is input to the gate by the conventional N-type MOSFET, the signal is replaced by the N-type positive logic element and the original signal is used for the gate input. The number of is halved. Further, since it is not necessary to create an inverted signal, an inverter circuit for creating an inverted signal is not necessary. In addition, signal delay and power consumption are reduced due to the reduction of wiring and circuits.
[0011]
Further, by using a positive logic element for the potential compensation circuit, the latch circuit configuration is simplified and the number of transistors is reduced.
[0012]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, details of the present invention will be described by way of examples. First, it is an important key of the present invention. The positive logic element will be described first.
[0013]
FIG. 5 is a sectional view of an element showing an embodiment of a positive logic element used in the present invention. In FIG. 5, 51 is a first gate electrode connected to the input signal. 52 and 53 are made of a P-type diffusion layer and serve as a source electrode or a drain electrode. Further, the source electrode side is connected to a positive power source directly or via another element. 54 and 55 are second gates of so-called floating gates which are not directly connected to signals, and 54 is formed on the channel 56 between the diffusion layers 52 and 53, and 55 is a channel The part which is not on the top is shown. Reference numerals 57 and 58 denote insulating layers mainly composed of silicon dioxide. The channel 56 is made of a thin N-type diffusion layer. When a positive potential is applied to the first gate 51, a negative charge is induced in the portion 54 on the channel of the second gate because it is directly under the first gate. Since the charge of the second gate itself is zero as a whole, the same amount of positive charge as the negative charge induced at 54 is induced at the portion 55 not on the channel at the second gate. As a result, the second gate portion 54 on the channel is charged with a negative potential including the lower portion. Therefore, a positive charge is induced in the channel 56, and the source and drain electrodes 52 and 53 are turned on (conductive). This state is shown in FIG. As a result, a positive potential output is obtained with respect to a positive potential input signal. Further, when a negative potential is applied to the first gate 51, the charges + and-in FIG. 6 are all reversed, and the source and drain electrodes 52 and 53 are turned off (non-conductive). This is shown in FIG. Therefore, it can be seen that the element of FIG. 5 is a positive logic element. Since the P type is used for the diffusion layer, this case will be referred to as a P type positive logic element in the following.
[0014]
In FIG. 5, 52 and 53 are P-type diffusion layers, and 56 is a thin N-type diffusion layer. However, 52 and 53 are N-type diffusion layers and 56 is a thin P-type diffusion layer. In this case, when a negative potential is applied to the first gate electrode 51, the source electrodes or drain electrodes 52 and 53 are turned on (conductive), and when a positive potential is applied to the first gate electrode 51, 52 and 53. Realizes elements that are turned off (non-conducting). Since the N type is used for the diffusion layer, this case is hereinafter referred to as an N type positive logic element.
[0015]
FIG. 1 is a circuit diagram showing a first embodiment of the present invention. In FIG. 1, a circuit surrounded by a broken line 1 is a pass transistor tree circuit, and a circuit surrounded by a broken line 2 is a potential compensation circuit. In the broken line 1, 10, 12, and 14 are N-type positive logic elements, and 11, 13, and 15 are N-type MOSFETs. The source (drain) electrode of the N-type positive logic element 12 is connected to the input terminal 5 to which a potential of + V _DD is applied, and the drain (source) electrode is connected to the source (drain) electrode of the N-type positive logic element 10. Yes. The drain (source) electrode of the N-type positive logic element 10 is connected to the output terminal 8 of the pass transistor tree circuit 1. The source (drain) electrode of the N-type positive logic element 14 is connected to the input terminal 6 to which the inverted signal (−C) of the signal C is input, and the drain (source) electrode is connected to the source (drain) electrode of the N-type MOSFET 11. ing. The drain (source) electrode of the N-type MOSFET 11 is connected to the output terminal 8 of the pass transistor tree circuit 1. The source (drain) electrode of the N-type MOSFET 13 is connected to the input terminal 6, and the drain (source) electrode is connected to the source (drain) electrode of the N-type positive logic element 10. Source (drain) electrode of the N type MOSFET15 are connected to the input terminal 7 given _{-V SS,} drain (source) electrode is connected to the source (drain) electrode of the N-type MOSFET 11. The gate electrodes of the N-type positive logic element 10 and the N-type MOSFET 11 are connected to the input terminal 3 to which the A signal is input. The gate electrodes of the N-type positive logic elements 12 and 14 and the N-type MOSFETs 13 and 15 are connected to the input terminal 4 to which the B signal is input.
[0016]
At this time, for each of the signals A, B, and C, an inverted signal of the carry to the upper bits of the addition result of (A + B) is output to the output terminal 8 with C as the lower digit carry. Inverted and a normal carry signal is output to the output terminal 9.
[0017]
Now, when the signal of the input terminal 5 or 6 or 7 is transmitted to the output terminal 8 at this time, the pass transistor tree circuit 1 is composed of an N-type MOSFET or an N-type positive logic element. There is no particular problem when _SS is transmitted, but when the positive power supply + V _DD passes through the N-type MOSFET or N-type positive logic element, a voltage drop corresponding to the threshold voltage of the N-type MOSFET or N-type positive logic element occurs. . The potential compensation circuit 2 corrects the potential of this signal to a normal + V _DD potential, which will be described next.
[0018]
In the broken line 2 indicating the potential compensation circuit, 16 is a P-type positive logic element. The source electrode of the P-type positive logic element 16 is connected to the positive power supply terminal + V _DD , and the gate electrode and the drain electrode are connected to each other and to the output terminal 8. When a −V _SS signal is received at the output terminal 8, the P-type positive logic element 16 remains off (OFF), and a positive signal having a voltage drop from + V _DD by the threshold voltage is received. In this case, the P-type positive logic element 16 is turned on (ON), and the potential of the output terminal 8 is corrected to + V _DD so as not to cause the leakage of the next-stage transistor. Note that the role of the P-type positive logic element 16 is to correct the potential, and the signal at the output terminal 8 should not be disturbed. In the case of the circuit of FIG. 1, since the pass transistor tree circuit 1 is configured to output the inverted signal of the carry of the adder circuit to the output terminal 8, the original signal is inverted by the inverter 17 in order to extract a regular signal. Output to the output terminal 9.
[0019]
The circuit of FIG. 1 is obtained by changing a part of the MOSFET of the pass transistor tree circuit in the circuit of FIG. That is, among the N-type MOSFETs 810, 811, 812, 813, 814, and 815 in the broken line 801 in FIG. 8, the N-type MOSFETs 810, 812, and 814 are respectively N-type positive logic elements 10 in the circuit of the embodiment of FIG. , 12 and 14. The (−A) signal is applied to the gate electrode of the N-type MOSFET 810 in FIG. 8, but the logic is maintained by changing the signal to the A signal in the gate electrode of the N-type positive logic element 10 replaced in FIG. 1. Yes. Similarly, the (-B) signal is applied to the gate electrodes of the N-type MOSFETs 812 and 814 in FIG. 8, but the signal is changed to the B signal on the gate electrodes of the N-type positive logic elements 12 and 14 replaced in FIG. To keep the logic.
[0020]
As a result of the above, comparing FIG. 1 and FIG. 8, it can be seen that the present invention eliminates the need for the number of wirings and a circuit for generating an inverted signal, and simplifies the configuration of the potential compensation circuit. It can also be seen that the reduction in the number of wirings and the number of circuits reduces the parasitic capacitance, thereby reducing signal delay and power consumption.
[0021]
FIG. 2 is a circuit diagram showing a second embodiment of the present invention. The first embodiment shown in FIG. 1 is a circuit that is converted by utilizing the circuit of FIG. 8 of the conventional example as much as possible for ease of understanding. However, since the potential compensation circuit is different, the output terminal 8 of FIG. Inverted function (−f) is output to the inverter circuit 17, and therefore an unnecessary inverter circuit 17 is added. In the second embodiment of FIG. 2, the function f is output directly to the output of the pass transistor tree circuit, and the number of inverter circuits is further reduced.
[0022]
In FIG. 2, a circuit surrounded by a broken line 1 is a pass transistor tree circuit, and a circuit surrounded by a broken line 2 is a buffer circuit. The configuration in the pass transistor tree circuit 1 in FIG. 2 and the input signals A and B are the same as those in FIG. 1, but the input terminals 5, 6, and 7 are added with signals in an inverted relationship with FIG. That is, −V _SS is added to the input terminal 5, a C signal is added to the input terminal 6, and + V _DD is added to the input terminal 7. As a result, the function f of the carry result to the upper part of the adder circuit is output to the output terminal 8 of the pass transistor tree circuit. Thereby, of course, the number of transistors is further reduced as compared with the circuit of FIG. 1 as compared with the circuit of FIG.
[0023]
FIG. 3 is a circuit diagram showing a third embodiment of the present invention. 1 and 2 are examples of a single rail system, and FIG. 3 is an example of a double rail system. In FIG. 3, a circuit surrounded by a broken line 1 is a pass transistor tree circuit, and a circuit surrounded by a broken line 2 is a potential compensation circuit. In the broken line 1, 21, 23, 25 and 27 are N-type positive logic elements, and 22, 24, 26 and 28 are N-type MOSFETs. The source (drain) electrode of the N-type MOSFET 26 is connected to the input terminal 35 for inputting the signal B, and the drain (source) electrode is connected to the source (drain) electrode of the N-type positive logic element 21. The drain (source) electrode of the N-type positive logic element 21 is connected to the inverting output terminal 38 of the pass transistor tree circuit 1. The source (drain) electrode of the N-type MOSFET 28 is connected to the input terminal 36 for receiving the inverted signal (−B) of the signal B, and the drain (source) electrode is connected to the source (drain) electrode of the N-type positive logic element 23. ing. The drain (source) electrode of the N-type positive logic element 23 is connected to the output terminal 39 of the pass transistor tree circuit 1. The source (drain) electrode of the N-type positive logic element 25 is connected to the source (drain) electrode of the N-type MOSFET 28, and the drain (source) electrode is connected to the drain (source) electrode of the N-type MOSFET 26. The source (drain) electrode of the N-type positive logic element 27 is connected to the source (drain) electrode of the N-type MOSFET 26, and the drain (source) electrode is connected to the drain (source) electrode of the N-type MOSFET 28. The source (drain) electrode of the N-type MOSFET 22 is connected to the source (drain) electrode of the N-type positive logic element 23, and the drain (source) electrode is connected to the drain (source) electrode of the N-type positive logic element 21. The source (drain) electrode of the N-type MOSFET 24 is connected to the source (drain) electrode of the N-type positive logic element 21, and the drain (source) electrode is connected to the drain (source) electrode of the N-type positive logic element 23. The gate electrodes of the N-type positive logic elements 25 and 27 and the N-type MOSFETs 26 and 28 are connected to an input terminal 34 to which an A signal is input. The gate electrodes of the N-type positive logic elements 21 and 23 and the N-type MOSFETs 22 and 24 are connected to an input terminal 33 to which a C signal is input.
[0024]
At this time, for each of the signals A, B, and C, the addition result of (A + B) is output to the output terminal 39 of f with C as the lower digit carry, and the inverted signal (−f) of f is inverted. It is output to the output terminal 38. When the signal of the input terminal 35 or 36 is transmitted to the output terminal 39 or the inverting output terminal 38, the positive power supply + V _DD passes through the N-type MOSFET or the N-type positive logic element, and the N-type MOSFET or the N-type positive A voltage drop corresponding to the threshold voltage of the logic element occurs. The potential compensation circuit 2 corrects this. In the potential compensation circuit 2, the inverter circuit is overridden and the output signal 39 of the pass transistor tree circuit and the inverted output signal 38 are input, and either of them is the threshold voltage with respect to the positive potential + V _DD. Even if the voltage drops, the voltage is corrected to + V _DD and the latch circuit changes to a stable state. At this time, either the positive power supply potential + V _DD or the negative power supply potential −V _SS is output to the output terminal 39 and the inverted output terminal 38. Therefore, it can be understood that the circuit does not flow a leak current at rest.
[0025]
The circuit shown in FIG. 3 is obtained by changing some of the MOSFETs from the circuit shown in FIG. That is, in FIG. 9, N-type MOSFETs 921, 923, 925, and 927 are replaced with N-type positive logic elements 21, 23, 25, and 27 in the circuit of the embodiment of the present invention in FIG. The (-C) signal is applied to the gate electrodes of the N-type MOSFETs 921 and 923 in FIG. 9, but the signal is changed to a C signal in the gate electrodes of the N-type positive logic elements 21 and 23 replaced in FIG. Keep the logic. Similarly, the (-A) signal is applied to the gate electrodes of the N-type MOSFETs 925 and 927 in FIG. 9, but the signal is changed to the A signal at the gate electrodes of the N-type positive logic elements 25 and 27 replaced in FIG. To keep the logic. From the above, it can be seen that the number of wirings is reduced.
[0026]
FIG. 4 shows a fourth embodiment of the present invention. In FIG. 4, 41 is a pass transistor tree circuit, and 42 is a potential compensation circuit. The circuit of FIG. 4 is obtained by converting an N-type positive logic element in the circuit of FIG. 10 of the conventional example, and can also be seen as an example in which the potential compensation circuit of FIG. 3 is replaced.
[0027]
As described above, in the embodiments of FIGS. 1, 2, 3, and 4, the example of the adder circuit is used as the pass transistor tree circuit. However, if the logic of each connection of the MOSFET and the positive logic element changes, Therefore, the present invention can be applied to various logic circuits.
[0028]
In the above embodiment, the pass transistor tree circuit is composed of an N-type MOSFET and an N-type positive logic element, but may be composed of a P-type MOSFET and a P-type positive logic element.
[0029]
【The invention's effect】
As described above, according to the present invention, there is an effect that a pass transistor logic circuit can be configured with a small number of transistors and a small number of wires.
[0030]
As a result, a pass transistor logic circuit with low signal delay and low power consumption can be provided.
[Brief description of the drawings]
FIG. 1 is a circuit diagram showing a first embodiment of the present invention.
FIG. 2 is a circuit diagram showing a second embodiment of the present invention.
FIG. 3 is a circuit diagram showing a third embodiment of the present invention.
FIG. 4 is a circuit diagram showing a fourth embodiment of the present invention.
FIG. 5 is a cross-sectional view showing a configuration of a positive logic element used in the pass transistor logic circuit of the present invention.
FIG. 6 is a charge distribution diagram showing the operation of the positive logic element used in the pass transistor logic circuit of the present invention.
FIG. 7 is a charge distribution diagram showing the operation of the positive logic element used in the pass transistor logic circuit of the present invention.
FIG. 8 is a circuit diagram showing an example of a conventional single rail type pass transistor logic circuit;
FIG. 9 is a circuit diagram showing an example of a conventional double rail type pass transistor logic circuit;
FIG. 10 is a circuit diagram showing an example of a conventional double rail type pass transistor logic circuit;
[Explanation of symbols]
1, 31, 41, 801, 931, 1041... Pass transistor tree circuit 2, 32, 42, 802, 932, 1042... Potential compensation circuit 3, 4, 5, 6, 7, 33, 34, 35 36, 43, 44, 45, 46, 803, 804, 805, 806, 807, 933, 934, 935, 936, 949, 950, 1043, 1044, 1045, 1046, 1050, 1059, ..., input terminal 8 , 9, 38, 39, 48, 49, 808, 809, 938, 939, 1048, 1049... Output terminals 10, 12, 14, 21, 23, 25, 27... N-type positive logic element 11, 13, 15, 22, 24, 26, 28, 810, 811, 812, 813, 814, 815, 921, 922, 923, 924, 925, 926, 927, 928 ·· N-type MOSFET
16 P-type positive logic element 816 P-type MOSFET
17, 817, 818... Inverter circuit 51... First gate electrode 52, 53... Source electrode or drain electrode 54 made of diffusion layer... Second gate electrode 55 on channel. Second gate electrode 56 not on channel ... Channel 57, thin layer of diffusion layer, 58 ... Insulating film made of silicon dioxide

Claims (3)

a) A path comprising a single-rail type pass transistor tree circuit that outputs a signal of a logical function or an inverted logical function of the logic, and a potential compensation circuit that corrects an output signal that has dropped through the pass transistor tree circuit to a power supply potential. In transistor logic circuits,
b) In addition to the insulated gate field effect transistor and the element, a first electrode and a second electrode that are formed of a diffusion layer and serve as a source electrode or a drain electrode, a first gate electrode to which an input signal is applied, and directly And a second gate electrode of a floating gate not connected to a signal, the first gate electrode being located above a channel between the first electrode and the second electrode made of the diffusion layer, A part of the two gate electrodes is located between the channel between the first electrode and the second electrode made of the diffusion layer and the first gate electrode, and the remaining part is a positive electrode made up of a structure located outside the channel. In a semiconductor integrated circuit device comprising a logic element,
c) The pass transistor tree circuit includes both the first conductivity type insulated gate field effect transistor and the first conductivity type positive logic element, and the logic is configured by combining in parallel or in multiple stages. Pass transistor logic circuit. 2. A pass transistor logic circuit comprising a second conductivity type positive logic element having a gate electrode and a drain electrode connected to each other in the potential compensation circuit according to claim 1. a) A double-rail type pass transistor tree circuit that outputs two signals of a logic function and an inverted logic function of the logic, and a potential compensation circuit that corrects an output signal that has dropped through the pass transistor tree circuit to a power supply potential. In the pass transistor logic circuit consisting of
b) In addition to the insulated gate field effect transistor and the element, a first electrode and a second electrode that are formed of a diffusion layer and serve as a source electrode or a drain electrode, a first gate electrode to which an input signal is applied, and directly And a second gate electrode of a floating gate not connected to a signal, the first gate electrode being located above a channel between the first electrode and the second electrode made of the diffusion layer, A part of the two gate electrodes is located between the channel between the first electrode and the second electrode made of the diffusion layer and the first gate electrode, and the remaining part is a positive electrode made up of a structure located outside the channel. In a semiconductor integrated circuit device comprising a logic element,
c) The pass transistor tree circuit includes both the first conductivity type insulated gate field effect transistor and the first conductivity type positive logic element, and the logic is configured by combining in parallel or in multiple stages. Pass transistor logic circuit.

Images