JP2001267910A - Multi-value logic semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve problems of a conventional multi-value logic semiconductor device that causes a huge amount of consumed currents when a multi-value (quaternary or over) logic circuit is configured by bipolar transistors(TRs) and deteriorates its response due to a back gate effect and a forward voltage drop of a diode when the multi-value (quaternary or over) logic circuit is configured by conventional bulk CMOS TRs adopting multiple power supplies. SOLUTION: The multi-value logic circuit consists of positive and network power supplies having a plurality of voltage levels and of P-channel and N-channel MOSFET groups with a plurality of different threshold voltages on an SOI substrate, where a complementary circuit consisting of a combination of P and N-channel MOSFETs with the highest threshold voltage connected to the positive power supply with the highest voltage level and the negative power supply with the lowest voltage level are supplied, and similar complementary circuits are formed through the combinations of succeeding rankings, and the respective outputs are connected via a MOS diode whose gate, drain and body are connected to obtain an output terminal. Thus, the multi-value logic circuit with a high information efficiency and a high integration efficiency, at a low cost and with low power consumption can be realized with the CMOS configuration providing an excellent operation characteristic.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit using a silicon-on-insulator (SOI) substrate.

[0002]

2. Description of the Related Art In conventional semiconductor integrated circuits, in particular, MOS integrated circuits, binary logics of 1 and 0 have been mainly used. In a multi-valued logic circuit, multi-valued data is expressed by I ² L or E
There is an example realized by the current amount by CL. Or. As disclosed in JP-A-06-276087, an insulated gate field effect transistor (hereinafter abbreviated as MOSFET) is used.
There is also an example in which a conventional MOS integrated circuit having a bulk structure is used.

[0003]

The above-mentioned 1, 0
In binary logic, the information processing efficiency as an integrated circuit is poor,
There has been a problem that the chip area increases and the cost increases.

[0004] Even in a multi-valued logic circuit, I ² L or E
A large current consumption and a large amount of power are required for the configuration using the CL, and an enormous amount of heat is generated with an increase in the scale of the gate.

[0005] Further, as shown in FIG.
In the case of No. 087, the MOSFET (Metal Oxide Semico
nductor Field Effect Transistor) is disclosed, but the substrate is usually bulk, and the substrate is common, so using a different potential power supply, either on the positive potential side or on the negative potential side, M with back gate effect
The effective threshold of the OSFET 1301 or the MOSFET 1302 is increased, and there is still a problem in terms of improving the operation speed. Diode means 1305, 1306, etc. are used so as not to short-circuit when connecting output terminals of different power supply systems. Generally, depending on the process, a diode in which P diffusion and N diffusion are joined together has a voltage of 0.5 V in the forward direction. There is a problem that there is a relatively large voltage drop of about 0.8 V and an expected output potential cannot always be obtained.

Therefore, the present invention solves such a problem, and an object of the present invention is to increase the efficiency of signal wiring and reduce the scale of a logic circuit by making the logic of an integrated circuit multi-valued. It is intended to support large-scale gates at low cost.

It is another object of the present invention to realize a large-scale gate circuit with low current consumption, low power consumption and low heat generation by realizing the multi-valued logic circuit by a MOS integrated circuit.

Further, by improving the above-mentioned Japanese Patent Application Laid-Open No. 06-276087 and forming a MOSFET of a different power supply system on the SOI substrate, the back gate effect and the forward voltage drop of the diode are reduced, and the characteristics are good. It is an object of the present invention to provide a multi-valued logic circuit that can operate at high speed.

[0009]

According to the present invention, there is provided a multilevel logic semiconductor device comprising: a) a SOI substrate; b) a plurality of power supplies having 2M different potential levels, where M is a positive integer of 2 or more;
c) M types of P-type MOSFs having different threshold voltages
ET group and d) N different threshold voltages of M kinds
E) counting the 2M power supplies from the higher potential, and setting the K-th (1 ≦ K ≦ M) power supply from the higher absolute value of the M kinds of different threshold voltages to K The K-th power supply is connected to the source electrode of the P-th MOSFET and the K-th power supply is counted from the lower potential, and the K-th power supply is counted from the higher absolute value of the M different threshold voltages. A logic element connected to a source electrode of a MOSFET, wherein the P-type and N-type MOSFETs are configured to be complementary to each other, and a drain electrode is connected to each other as an output terminal; and f) a source electrode, a drain electrode, and a gate are controlled. An insulated gate field effect transistor having a gate electrode connected to the body and a body electrode connected to a body formed immediately below the channel, wherein the drain electrode and the gate electrode And it consists of a MOS diode consists of connecting the body electrode to each other, g) in the plurality of logic elements, K = K1 th logical element and K =
The output terminal of the K2th logic element has a combined logic element connected via the MOS diode.

The insulated gate field effect transistor on the silicon-on-insulator substrate is of a partially depleted layer type.

According to the above-mentioned structure of the present invention, since a multi-power supply is combined with a plurality of P-type MOSFETs and N-type MOSFETs having different threshold voltages, a logic circuit having multi-valued (four or more) output values can be obtained. .

Further, since a complementary circuit configuration can be obtained with a MOS integrated circuit, a multi-valued logic circuit with low power consumption can be obtained.

Further, since the device is formed on an SOI substrate,
Even if MOSFETs of different power supplies are combined, there is no deterioration in characteristics due to the back gate effect, and as a diode means interposed when connecting output terminals having different output potentials, a MOS diode whose body potential is equal to the gate potential is used. A forward voltage drop is reduced, and a multi-valued logic circuit with good electrical characteristics such as high-speed response is realized.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail with reference to examples. FIG. 1 is a diagram showing a circuit diagram and a truth table when applied to a quaternary inverter circuit according to a first embodiment of the present invention. The circuit in FIG. 1A is configured on an SOI substrate. In FIG. 1A, a positive first power supply + VDD1, a positive second power supply + VDD2, a negative first power supply -VSS1, and a negative second power supply.
There are four types of power supplies-power supply-VSS2. 101 is a P-type MOSFET having a threshold voltage VTP1.
103 is a P-type MOSFET having a threshold voltage VTP2 higher than VTP1. Reference numeral 102 denotes an N-type MOSFET having a threshold voltage VTN1. 104 is a threshold voltage VT higher than VT1
It is an N-type MOSFET having N2. Reference numeral 105 denotes a MOS diode formed by connecting the gate, the drain, and the body of the P-type MOSFET. 106 is N-type M
This is a MOS diode formed by connecting the gate, the drain, and the body of the OSFET. P-type MOSFET
The source electrode of 101 is connected to + VDD1, the drain electrode is connected to the positive electrode which is the source of the MOS diode 105, and the negative electrode which is the drain of the MOS diode 105 is connected to the output terminal 108. N-type MOSFET 10
2 has a source electrode connected to -VSS1 and a drain electrode connected to M
Connected to the negative electrode that is the source of the OS diode 106,
The positive electrode, which is the drain of the MOS diode 106, is connected to the output terminal 108. The source electrode of the P-type MOSFET 103 is connected to + VDD2, and the drain electrode is connected to the output terminal 108. The source electrode of the N-type MOSFET 104 is connected to -VSS2, and the drain electrode is connected to the output terminal 108. MOSFET 101, 10
The gate electrodes 2, 103 and 104 are connected to each other and to the input terminal 107. Now, in the threshold voltage VTP1 of the P-type MOSFET 101, there is a relation of VDD1 + VSS1>VTP1> 0 as + VDD2> + VDD1>0>-VSS1> -VSS2, and the gate potential of the P-type MOSFET 101 is
Both are turned on at -VSS2 and -VSS1, and + VDD2, + VDD2
Both are turned off (OFF) at VDD1. P-type MOSFET1
The threshold voltage VTP2 of 03 is set to a value higher than VTP1, and there is a relation of VDD2 + VSS2>VTP2> VDD2 + VSS1. That is, the P-type MOSFET 103 turns on when the gate potential is -VSS2, but does not turn on at -VSS1,
It remains off. As a matter of course, it is off at + VDD2 and + VDD1. At the threshold voltage VTN1 of the N-type MOSFET 102, there is a relation of VDD1 + VSS1>VTN1> 0, and the gate potential of the N-type MOSFET 102 is
Both are turned on at + VDD2 and + VDD1, and are turned off at -VSS2 and -VSS1. The threshold voltage VTN2 of the N-type MOSFET 104 is set to a value higher than VTN1, and there is a relationship of VDD2 + VSS2>VTN2> VDD1 + VSS2. Therefore, the N-type MOSFET 104 turns on when the gate potential is + VDD2, but does not turn on at + VDD1 and remains off. Also, naturally -VSS2, -VS
It is off in S1.

As described above, when the potential of + VDD2 is applied to the input terminal 107, the N-type MOSFET 102 and the N-type MOSFET
104 is turned on, and -VSS1
, And −VSS2 are supplied from the N-type MOSFET 104 to the output terminal 108, respectively.
6, the output terminal 108 has the potential of -VSS2. When the potential of + VDD1 is applied to the input terminal 107, only the N-type MOSFET 102 is turned on.
8 becomes the potential of -VSS1. Also, -VS is applied to the input terminal 107.
The P-type MOSFET 10 turns on when the potential of S1 is applied.
Since it is only 1, the output terminal 108 has the potential of + VDD1. When a potential of -VSS2 is applied to the input terminal 107, P
The MOSFET 101 and the P-type MOSFET 103 are turned on, and + VDD1 is output from the P-type MOSFET 101 and + VDD2 is output from the P-type MOSFET 103, respectively.
The output terminal 108 has a potential of + VDD2 because of the presence of the diode 105. FIG. 1B is a diagram in which the above is organized into a truth table.

Although there are generally no restrictions as follows,
For simplicity, if VDD1 = VSS1 = E1 VDD2 = VSS2 = E2, then + VDD1 = + E1-VSS1 = -E1 + VDD2 = + E2-VSS2 = -E2, and FIG. FIG. 1C is obtained by rewriting b). Looking at the truth table of FIG.
It can be seen that the circuit of (a) is a quaternary inverter circuit.

In the above description, each MOSFET is S
The body is formed on each MOSF
It is independent for each ET, and it is not necessary to use a common substrate as in the conventional bulk CMOS.
Even if ET is mixed on the chip, the substrate potential does not become higher than the source potential. Therefore, the threshold voltage does not increase due to the back gate effect, and good operation can be expected.

In the above circuit, the MOS diodes 105 and 106 are used. However, in order to perform the above-described multi-valued function under good electric characteristics, the forward voltage drop of the diode means must be small. Is an important point. Therefore, the MOS diode used in the present invention will be described in detail with reference to FIGS.

FIG. 8 is a circuit diagram of a MOS diode circuit used in the present invention. 8, 801 is a source electrode, 802 is a drain electrode, 803 is a gate electrode, 80
Reference numeral 4 denotes a body located immediately below the channel and a body electrode for extracting a potential. Here, the gate electrode 8
03 and the body electrode 804 are connected to each other and to the drain electrode 802. Further, the MOSFETs constituting the MOS diode circuit of FIG. 8 are formed on an SOI substrate having a buried oxide film. This will be described below with reference to FIG. FIG. 9 shows an MOI on an SOI substrate.
It is sectional drawing which comprised SFET. In FIG. 9, 90
5 is a buried oxide film layer mainly composed of silicon dioxide (S _i O _2). Reference numeral 901 denotes a source electrode, and reference numeral 902 denotes a source electrode.
3 is a gate electrode. FIG. 9 shows a partially depleted layer type SOI. Reference numeral 904 denotes a body made of an N-type lightly doped diffusion layer. Reference numeral 906 denotes a substrate. Also,
907 is an insulating layer a selective oxide film layer mainly composed of silicon dioxide _{(S i O 2) (LOCOS} ). Body 9
Reference numeral 04 is located immediately below the channel of the MOSFET, and usually corresponds to a well of a substrate in a bulk MOSFET. However, in the SOI substrate, the buried oxide film 90
Since there are five insulating layers, the body 904 is electrically independent as it is. FIG. 10 shows the MOSF of FIG.
FIG. 10 is a plan view of the ET as viewed from above, and shows an example of a case where the potential of the body 904 shown in FIG. 9 is extracted. In FIG. 10, 1001 is composed of P-type diffusion,
A source electrode 1002 is made of P-type diffusion, and a drain electrode 1003 is a gate electrode. In FIG. 10, the body 904 shown in FIG. 9 is not visible because it exists below the gate 1003. However, it exists immediately below the channel of the gate 1003 and reaches just below the contact hole 1007.
Then, the body 904 and the gate electrodes 903 and 1003 in FIGS. 9 and 10 are electrically connected by performing a deep N-type diffusion on the contact hole and covering the contact hole with an aluminum wiring layer. In addition, the drain electrodes 902 and 1002
And the gate electrodes 903 and 1003 are connected to the contacts in the step of aluminum wiring, so that the MO shown in FIG.
An S diode circuit can be configured. FIG. 9 shows the MOSF
Since the sectional view at the center of the ET is shown, the above-described configuration in the contact hole 1007 of FIG. 10 located at the end of the MOSFET is not shown.

In FIG. 8, the MOSFET is a gate.
Source electrode and drain electrode are connected, so the source electrode
If 801 is higher than the gate electrode 803, the saturation area
Operating in the range, and the conductance constant of the MOSFET
β_PAnd the threshold voltage to V_TH, Between gate and source
Voltage to V_GS(In the circuit of FIG. 8, the voltage between drain and source
V _DS, And voltage V between power supplies_DDEqual to, V_GS= V_DDToo
And the current flowing between the source and drain_DSTomorrow
If I_DS= 1/2 · β_P(V_DD-V_TH)^Two Becomes This equation is the power supply voltage V for the forward voltage._DD
With respect to the threshold voltage V_THVoltage drops by minutes
Which indicates that. In addition, the gate electrode 803 is a source
In the opposite direction where the potential is higher than the electrode 801, the current is
Not flowing.

The threshold voltage of the MOSFET is influenced by the potential of the body. Common use of P-type MOSFET of normal bulk often used conventionally the substrate (corresponding to the body) to the power supply + V _DD
Connect to This is because the substrate is usually not independent for each MOSFET in a bulk MOSFET, and widely used for other MOSFETs.
This is because it is natural to use the FET in common with the FET and fixed at the power supply potential from the viewpoint of the stability of the element and the integration efficiency.
Further, the threshold voltage of the MOSFET is defined in a state where the substrate (corresponding to the body) is connected to + V _{DD of} the power supply or the source electrode. On the other hand, when the body (substrate) potential is set to a potential other than the source electrode, the threshold voltage of the MOSFET is affected by which potential the body takes. This is called the back gate effect. The variation of the threshold voltage due to the back gate effect is approximately expressed as follows.

ΔV _TH = {(2ε _si ε _o · q · N _SUB ) ^1/2 / C
_{o} · {(2Φ f +} V) 1/2 - in (2Φ _f) ^1/2} where, epsilon _si is the dielectric constant of silicon, epsilon _o is the vacuum dielectric constant, q is the electron charge quantity, N _SUB Is the impurity concentration of the body,
_Co is the gate capacitance per unit area, V is the power supply voltage, Φ _f
Is the Fermi potential generated between the insulator silicon and the impurity according to the impurity concentration of the body.

As can be seen from the above equation, the change in the threshold voltage due to the back gate effect varies depending on the power supply voltage and the process parameters. Can often be expected to be comparable to

Now, when the body is connected to the gate as in the circuit of FIG. 8, the gate turns on the MOSFET (O
In the case of a low potential (Low), which is the potential in the case of N), the body also has a low potential, which is different from the case where the body potential in the conventional normal usage is a high potential (High). In the case of the circuit of FIG. 8, the back gate effect changes to a low threshold voltage that makes it easier to turn on.

The gate turns off the MOSFET (OF
F), a high potential (Hi) in the circuit of FIG.
gh), the body also has a high potential, which is the same as the normal potential (High). In this case, there is no back gate effect, the threshold does not change, and a leak current occurs due to such connection. There is no such thing. Therefore, in the circuit shown in FIG. 8, while the reverse leakage current is maintained at the same level, the forward current is more likely to flow as much as the threshold is lowered, and the forward voltage drop is equivalently reduced. FIG. 12 shows this state, in which the characteristics of a conventional circuit are compared to 1200.
Then, in the MOS diode circuit used in the present invention in FIG. 8, the characteristic shown by 1201 in FIG. 12 is obtained. From the above, it can be understood that a MOS diode element having a small forward voltage drop can be obtained.

FIG. 11 shows a MOS in the case of an N-type MOSFET.
It is a circuit diagram of a diode circuit. In FIG. 8, a P-type MOSF
In contrast to the ET example, FIG.
This figure shows a case where the transistor is composed of T, and the principle and the effect that the voltage drop in the forward direction is small although there is a difference between the P type and the N type are the same. This N-type MOS diode is shown in FIG.
Are used for the MOS diode 106 in FIG.

FIG. 2 shows a circuit diagram and a truth table when applied to a six-valued inverter circuit according to a second embodiment of the present invention. In FIG. 2A, a positive first power source
+ VDD1, a positive second power supply + VDD2, and a positive third power supply + VDD3
There are six power supplies: a first power supply -VSS1 for the negative electrode, a second power supply -VSS2 for the negative electrode, and a third power supply -VSS3 for the negative electrode. 201 is a P-type MOSFET having a threshold voltage VTP1. 203 is a threshold voltage VT higher than VTP1
It is a P-type MOSFET having P2. 205 is VTP
1. A P-type MOSFET having a threshold voltage VTP3 higher than VTP2. Reference numeral 202 denotes an N-type MOSFET having a threshold voltage VTN1. 204 is a higher threshold voltage VT compared to VTN1
It is an N-type MOSFET having N2. 206 is VTN
1. An N-type MOSFET having a higher threshold voltage VTN3 than VTN2. MOS diodes 207 and 209 are P-type MOSFETs. Reference numerals 208 and 210 denote MOS diodes using N-type MOSFETs.

The source electrode of the P-type MOSFET 201 is
VDD1 and the drain electrode is MOS diode 2
The negative terminal of the MOS diode 207 is connected to the output terminal 212. N-type MOSFET
The source electrode of 202 is connected to -VSS1, the drain electrode is connected to the negative electrode of MOS diode 208, and the positive electrode of MOS diode 208 is connected to output terminal 212. The source electrode of the P-type MOSFET 203 is connected to + VDD2, the drain electrode is connected to the positive electrode of the MOS diode 209, and the negative electrode of the MOS diode 209 is connected to the output terminal 212. The source electrode of the N-type MOSFET 204 is connected to -VSS2, the drain electrode is connected to the negative electrode of the MOS diode 210,
The positive electrode of 10 is connected to the output terminal 212. P type M
The source electrode of the OSFET 205 is connected to + VDD3, and the drain electrode is connected to the output terminal 212. N type M
The source electrode of the OSFET 206 is connected to -VSS3, and the drain electrode is connected to the output terminal 212. MOS
FETs 201, 202, 203, 204, 205, 20
6 are connected to each other and the input terminal 211
It is connected to the.

+ VDD2, + VDD1, -VSS1, -VSS2 and P-type M
OSFET 201 threshold voltage VTP1, P-type M
OSFET203 threshold voltage VTP2, N-type M
OSFET 202 threshold voltage VTN1, N-type M
The relationship between the threshold voltage VTN2 of the OSFET 204 is based on the MOSFET in the four-valued inverter circuit shown in FIG.
The relationship is the same as 101, 103, 102, 104.
Now, at the newly added threshold voltage VTP3 of the P-type MOSFET 205, + VDD3> + VDD2> + VDD1>0>-VSS1> -VS
There is a relationship of VDD3 + VSS3>VTP3> VDD3 + VSS2 as S2> -VSS3, and the gate potential of the P-type MOSFET 205 is
It turns on at -VSS3, but does not turn on at -VSS2 and -VSS1, and remains off. Also, of course, + VDD3, + VDD
It is off at D2 and + VDD1. N-type MOSFET 206
In the threshold voltage VTN3, there is a relation of VDD3 + VSS3>VTN> VDD2 + VSS3, and the N-type MOSFET 206 has a gate potential of
It turns on at + VDD3, but does not turn on at + VDD2 and + VDD1, and remains off. Also, naturally -VSS3, -VS
It is off in S2 and -VSS1. With the above configuration, the relationship between the potential of the input terminal and the potential of the output terminal becomes the relationship of the diagram of the truth table of FIG. 2B for the same reason as in the quaternary inverter circuit of FIG. = VSS1 = E1 VDD2 = VSS2 = E2 VDD3 = VSS3 = E3 FIG. 2 (b) is as shown in FIG. 2 (c). FIG.
Looking at the truth table of (c), it can be seen that the circuit of FIG. 2A is a six-valued inverter circuit.

FIG. 3 shows a circuit according to a third embodiment of the present invention when applied to a quaternary NOR circuit (non-OR circuit, hereinafter abbreviated as NOR circuit). In FIG. 3A, there are + VDD2, + VDD1, -VSS1, and -VSS2 as power sources. P-type MO
The threshold voltage of the SFETs 301 and 302 is VTP1
It is. The threshold voltages of the N-type MOSFETs 303 and 304 are VTN1. P-type MOSFET 305, 3
The threshold voltage of 06 is VTP2. N-type MOS
The threshold voltages of the FETs 307 and 308 are VTN2. Now, the source electrode of the P-type MOSFET 301 is + VD
D1 and the drain electrode is a P-type MOSFET 302
The drain electrode of the P-type MOSFET 302 is connected to the positive electrode of the MOS diode 309, and the negative electrode of the MOS diode 309 is connected to the output terminal 319. The source electrodes of the N-type MOSFETs 303 and 304 are both connected to -VSS1, their drain electrodes are connected to each other, and are connected to the negative electrode of the MOS diode 310. The positive electrode of the MOS diode 310 is connected to the output terminal 319. P-type MOSF
Gate electrode 311 of ET301 and N-type MOSFET 30
3 are both connected to the first input terminal A, and the gate electrode 312 of the P-type MOSFET 302 and the gate electrode 314 of the N-type MOSFET 304 are both connected to the second input terminal B.

The above P-type MOSFETs 301, 302,
In the configuration of the N-type MOSFETs 303 and 304, the P-type MOSFETs 301 and 302 having the input terminals A and B are configured in series, and the N-type MOSFETs 303 and 304 are configured in parallel. I have. Figure 3 shows a well-known symbol
The configuration of (b) is adopted. Note that VTP1 and VTN1 have the relationship of VDD1 + VSS1>VTP1> 0 VDD1 + VSS1>VTN1> 0 as described in the example of the quaternary inverter circuit in FIG. 1, so that the input terminals A and B have + VDD1. , + VDD2
Is high potential, -VSS1 and -VSS2 are low potential, and output terminal 3
A NOR circuit 19 outputs + VDD1 or -VSS1. Now, the source electrode of the P-type MOSFET 305 is connected to + VDD2, and the drain electrode is the P-type MOSFET.
306 connected to the source electrode of the P-type MOSFET 30
The drain electrode 6 is connected to the output terminal 319.
The source electrodes of the N-type MOSFETs 307 and 308 are both-
VSS2, the respective drain electrodes are connected to each other, and to the output terminal 319. Also P
Gate electrode 315 of N-type MOSFET 305 and N-type MOS
The gate electrode 317 of the FET 307 is connected to the first input terminal A, and the gate electrode 3
16 and the gate electrode 318 of the N-type MOSFET 308 are both connected to the second input terminal B. Above P-type MO
SFETs 305 and 306, N-type MOSFETs 307 and 3
08, a P-type MOSF having input terminals A and B
The ETs 305 and 306 are configured in series, and an N-type MOSFE
Since T307 and 308 are configured in parallel, they have a complementary NOR circuit as a whole, that is, a configuration having the function of FIG. 3B. However, VTP2 and VTN2 have the relationship of VDD2 + VSS2>VTP2> VDD2 + VSS1 VDD2 + VSS2>VTN2> VDD1 + VSS2 as described in the example of the four-valued inverter circuit in FIG. + VDD as high potential
2. If -VSS2 is input as a low potential, +
It is a NOR circuit that outputs VDD2 or -VSS2. However, when only + VDD1 and -VSS1 are input to the input terminals A and B, VTP2 and VTN2 are too high, so that the MOSFET is not turned on and + VDD2 or -VSS2 is not output to the output terminal 319. Now, P-type MOSFETs 301 and 302 having a threshold voltage of VTP1 using + VDD1 and -VSS1 as power supplies.
N-type MOSFET with threshold voltage of VTN1
NOR circuit composed of 303 and 304 and + VDD2,-
P with a threshold voltage of VTP2 using VSS2 as a power supply
The outputs of the NOR circuit composed of the MOSFETs 305 and 306 and the N-type MOSFETs 307 and 308 having the threshold voltage of VTN2 are both output terminals 319 and are common. Therefore, the output terminal 319 has + VD
Although D2 and + VDD1 may be output at the same time, + VDD2 becomes the output potential of the output terminal 319 by the MOS diode 309. In some cases, -VSS2 and -VSS1 are simultaneously output to the output terminal 319.
By 0, -VSS2 becomes the output potential of the output terminal 319.
Now, with the above configuration, the input terminal A of the circuit of FIG.
FIG. 4 shows a truth table of B and the output terminal 319.
(A). In general, there is no restriction as follows, but FIG. 4A is rewritten as + VDD1 = + E1 -VSS1 = -E1 + VDD2 = + E2 -VSS2 = -E2 for easy understanding. b). In general, in a logic circuit having two or more values, the OR circuit becomes MAX (A, B) and the NOR circuit becomes -MAX (A, B). Therefore, referring to FIG. Since OUT = -MAX (A, B), it is clear that the circuit is an extended four-valued NOR circuit.

FIG. 5 is a circuit diagram showing a fourth embodiment of the present invention when applied to a quaternary NAND circuit (non-logical product). In FIG. 5A, the power supplies are + VDD2, + VDD1,
There are -VSS1 and -VSS2. P-type MOSFETs 501, 50
2, the threshold voltage is VTP1, and the N-type MOSF
The threshold voltage of the ETs 503 and 504 is VTN1, the threshold voltage of the P-type MOSFETs 505 and 506 is VTP2, and the threshold voltage of the N-type MOSFETs 507 and 508 is VTN2. Now + VDD1 and -VSS
P-type M with threshold voltage VTP1 using 1 as power supply
OSFETs 501 and 502 have input terminals A and B, respectively, and are connected in parallel. N-type MOSFETs 503, 504 having a threshold voltage VTN1 have input terminals A, B, respectively, and are connected in series with each other. + VDD1, + VDD2 to high potential, -VSS
1. This is a NAND circuit having the function shown by the symbol in FIG. 5B for outputting + VDD1 or -VSS1 to the output terminal 519 by setting -VSS2 to a low potential. Also, a P-type MOSFET having a threshold voltage VTP2 using + VDD2 and -VSS2 as power supplies.
The ETs 505 and 506 have input terminals A and B, respectively.
And are connected in parallel with each other and have a threshold voltage VTN2
N-type MOSFETs 507 and 508 having input terminals A and B, respectively, and having a configuration in which they are connected in series with each other, have a high potential of + VDD2 and a low potential of -VS.
When S2 is input, + VDD2 or
It is a NAND circuit that outputs -VSS2. + VDD1 and
-VSS1 is the power supply for the NAND circuit is MOS diode 5
09 and 510 to the output terminal 519, and
Both NAND circuits powered by + VDD2 and -VSS2 are connected to the output terminal 519. With the above configuration, FIG.
FIG. 6A shows a truth table of the input terminals A and B and the output terminal 519 of the circuit of FIG. FIG. 6B is a rewrite of FIG. 6A with + VDD1 = + E1-VSS1 = -E1 + VDD2 = + E2-VSS2 = -E2 for simplicity. In general, in a logic circuit having two or more values, the AND circuit is MIN (A, B) and the NAND circuit is -MIN (A, B). Therefore, referring to FIG. Since OUT = −MIN (A, B), it is clear that the circuit is an extended four-valued NAND circuit.

FIG. 7 is a circuit diagram of a fifth embodiment of the present invention applied to a composite logic circuit. In FIG. 3, four values N
Although an example of an OR circuit and a four-valued NAND circuit is shown in FIG. 5, a general four-valued composite logic circuit is shown below with an example of an OR-NAND circuit as shown in FIG. 7B.

In FIG. 7A, the power supply is + VDD2,
+ VDD1, -VSS1, and -VSS2. P-type MOSFET 70
The threshold voltages of 1, 702 and 703 are VTP1, the threshold voltages of N-type MOSFETs 704, 705 and 706 are VTN1 and the P-type MOSFET 70
The threshold voltages of 7, 708 and 709 are VTP2, and the threshold voltages of N-type MOSFETs 710, 711 and 712 are VTN2. Well P-type MOSFET7
01, 702, 703 and N-type MOSFETs 704, 70
Complementary OR between + VDD1 and -VSS1 between 5 and 706
-Construct a NAND circuit and use P-type MOSFETs 707 and 7
08, 709 and N-type MOSFETs 710, 711, 71
Complementary OR / NAN between + VDD2 and -VSS2 power supplies
A circuit D is formed, the outputs of the two OR / NAND circuits are connected in common to form an output terminal 727, and + VDD2 and + VDD
A MOS diode 713 is provided to avoid the collision of D1,
MOS diode 7 to avoid collision between -VSS2 and -VSS1
14 are provided. With the above configuration, FIGS.
For the same reason as described above, the circuit of FIG.
-It is a NAND circuit.

Further, in the above embodiments it has been an example of using a substrate of silicon-on-insulator having a buried oxide film layer mainly composed of silicon dioxide (S _i O ₂₎ as the insulator (SOI), Below the MOSFET is the insulating layer,
In the case of a semiconductor integrated circuit having a structure in which the body is isolated, the same means as in the present invention can be used, and the same effect can be obtained. Therefore, silicon with an insulating layer of sapphire (Al ₂ O ₃ )
It may be on sapphire (SOS) or another insulating material such as diamond.

[0035]

As described above, according to the present invention, there is an effect that a multi-valued logic circuit having four or more values can be constituted by a CMOS integrated circuit with low current consumption.

Further, by making the logic of the integrated circuit multi-valued, the information efficiency of the signal wiring is remarkably improved, the scale of the logic circuit including the signal wiring is reduced, and a low-cost large-scale gate integrated circuit is realized. There is an effect that can be realized.

Further, since the scale of the logic circuit including the signal wiring is reduced by the multi-valued logic circuit, there is an effect that a large-scale gate circuit with low current consumption, low power consumption and low heat generation is realized.

Further, by forming the MOS of the different power supply system on the SOI substrate, the back gate effect and the forward voltage drop of the diode can be reduced to provide a high-speed and multi-valued logic circuit with good characteristics. There is.

Further, by using a partially depleted layer type SOI, a structure in which the depletion layer of the FET does not reach the vicinity of the insulating layer is obtained, and it is not necessary to largely change the conventional manufacturing technology.

[Brief description of the drawings]

FIG. 1 is a circuit diagram and a truth table illustrating a first embodiment of the present invention. FIG. 1A is a circuit diagram of a quaternary inverter circuit, and FIGS. 1B and 1C are diagrams of a truth table showing circuit operations.

FIG. 2 is a circuit diagram and a truth table illustrating a second embodiment of the present invention. FIG. 2A is a circuit diagram of a six-valued inverter circuit, and FIGS. 1B and 1C are diagrams of a truth table showing circuit operations.

FIG. 3 is a circuit diagram and a logic symbol diagram showing a third embodiment of the present invention. FIG. 3A is a circuit diagram of a quaternary NOR circuit, and FIG. 3B is a diagram of a logical symbol indicating a circuit operation.

FIG. 4 is a diagram of a truth table showing actual operation of the circuit of FIG. 3A of the present invention. FIG. 4A shows the signal potential + VDD2,
FIG. 4 is a diagram of a truth table between + VDD1, -VSS1, and -VSS2.
(B) is a diagram of a truth table when VDD1 = VSS1 = E1 and VDD2 = VSS2 = E2.

FIG. 5 is a circuit diagram and a logical symbol diagram showing a fourth embodiment of the present invention. FIG. 5A is a circuit diagram of a four-level NAND circuit, and FIG. 5B is a diagram of a logical symbol indicating a circuit operation.

FIG. 6 is a diagram of a truth table showing actual operation of the circuit of FIG. 5A according to the present invention. FIG. 6A shows the signal potential + VDD2,
FIG. 6 is a diagram of a truth table between + VDD1, -VSS1, and -VSS2.
(B) is a diagram of a truth table when VDD1 = VSS1 = E1 and VDD2 = VSS2 = E2.

FIG. 7 is a circuit diagram and a diagram of a logical symbol showing a fifth embodiment of the present invention. FIG. 7A is a circuit diagram of a four-level OR / NAND circuit, and FIG. 7B is a diagram of a logical symbol indicating a circuit operation.

FIG. 8 is a circuit diagram of a MOS diode using a P-type MOSFET used in the present invention.

FIG. 9 shows M of a MOS diode used in the present invention.
FIG. 3 is a cross-sectional view of an OSFET.

FIG. 10 is a plan view of a MOSFET of a MOS diode used in the present invention.

FIG. 11 is a circuit diagram of a MOS diode using an N-type MOSFET used in the present invention.

FIG. 12 shows a MOS diode used in the present invention,
FIG. 11 is a characteristic diagram showing an example of current characteristics of a conventional MOS diode.

FIG. 13 is a circuit diagram of a conventional normal bulk CMOS multi-valued logic circuit.

[Explanation of symbols]

101, 103, 201, 203, 205, 301, 3
02, 305, 306, 501, 502, 505, 506, 701, 702, 7
03, 707, 708, 709, 1301, 1303 ... P-type MOSFE
T 102, 104, 202, 204, 206, 303, 3
04, 307, 308, 503, 504, 507, 50
8, 704, 705, 706, 710, 711, 71
2, 1302, 1304: N-type MOSFET 207, 209, 309, 509: P-type MOS
Diodes 208, 210, 310, 510 N-type MOS
Diodes 1305, 1306 ... Diodes 107, 211, 311, 312, 313, 314, 3
15, 316, 317, 318, 511, 512, 51
3, 514, 515, 516, 517, 518, 71
5, 716, 717, 718, 719, 720, 72
1,722,723,724,725,726,130
7 ... input terminal 108, 212, 319, 519, 727, 1308
... output terminals 801, 901, 1001, 1101 ... sources 802, 902, 1002, 1102 ... drains 903, 1003, 1103 ... gate electrodes 904, 1104 ... body 905 ... Film layer 906 Substrate 907 Selective oxide film layer 1007 Contact hole 1201 Current characteristics of MOS diode used in the present invention 1200 Current characteristics of conventional MOS diode

Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat II (Reference) H01L 27/08 331 29/786

Claims (2)

[Claims] 1. A) a semiconductor integrated circuit device using a silicon-on-insulator substrate; b) a plurality of power supplies of 2M different potential levels, where M is a positive integer of 2 or more; A group of P-type insulated gate field effect transistors with different threshold voltages; d) a group of N-type insulated gate field effect transistors with M different threshold voltages; e) counting the 2M power supplies from the higher potential A K-th (1 ≦ K ≦ M) power supply is connected to the source electrodes of the K-th P-type insulated gate field-effect transistors from the highest absolute value of the M different threshold voltages, and the 2M power supplies are connected. Are counted from the lower potential, and the K-th power supply is connected to the K-th N-type insulated gate field-effect transistor from the higher absolute value of the M different threshold voltages. A P-type and N-type insulated-gate field-effect transistor connected to a source electrode of a transistor, wherein the P-type and N-type insulated-gate field-effect transistors are configured to be complementary to each other, and a drain electrode is connected to each other as an output terminal; And an insulated gate field effect transistor having a gate electrode controlling a gate and a body electrode connected to a body formed immediately below the channel, wherein the drain electrode, the gate electrode, and the body electrode are connected to each other. G) wherein, in the plurality of logic elements, the output terminals of the K = K1st logic element and the K = K2th logic element are connected via the MOS diode. A multi-valued logic semiconductor device having a logic element. 2. The multilevel logic semiconductor device according to claim 1, wherein said insulated gate field effect transistor on said silicon-on-insulator substrate is of a partially depleted layer type.