JP2005198226A - Multi-valued logic circuit, multi-valued specific value logic circuit, multi-valued specific value determining circuit, multi-value specified value not circuit, and circuit, and nand circuit, multi-value and circuit, and multi-value specified value or circuit, nor circuit, over circuit, nover circuit, and/over ciruit, nand/over circuit, or/over circuit, nor/over circuit, under circuit, nunder circuit, and/under circuit, nand/under circuit, or/under circuit, nor/under circuit, and and/nunder circuit, or the like - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a multi-valued logic circuit which can be constituted even without using a normally-on insulating gate type FET and in which the relationship of input and output voltages is not restricted, and a multi-valued specific value logic circuit of which a function is known from a multi-valued logic circuit name given by the present inventor. <P>SOLUTION: For example, a multi-valued specific value determining circuit of a common embodiment uses a bidirectional switch (connection body of transistors 21, 24 and diodes 10, 12) in which the section between an output side switch terminal and a driving part is turned off in a bidirectional manner during off driving by a first invention. The concept of "specific value" is introduced into a multi-valued logic by a second invention to be limited to a function that "it is decided whether or not the numerical value of an input potential is equal to the numerical value (m) of a specific potential Vm, the specific potential Vm is outputted when they are equal to each other, or an output is opened when not". Thus, the multi-valued logic can be constituted even when it is a normally-off type, eliminates harmful defects (said restriction) in the use of normally-on type FET and can be represented in human words in the second invention. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  In the first and second inventions, a multi-value logic circuit (or multi-adic system) in which each value of multi-value (≧ 3) corresponds one-to-one with the potential or voltage of each potential supply means (eg, power supply line). Logic circuit). These multi-value logic circuits and the like are converted into multi-value arithmetic circuits (or multi-adic arithmetic circuits), multi-value computers (or multi-adic computers, in particular 4, 8, “10”, 16, 32, 64, “100”, 128-ary computer) or multi-value control means (or multi-adic control means).

In the case of the first invention, a normally-on gate-isolated FET (eg, depletion mode) is used by using “bidirectional switching means in which the switch terminal and drive unit are bidirectionally turned off during off-drive” for the output unit. (Although it can be configured even if it is used), the voltage output method is not limited by the input voltage and is free.
In the case of the second invention, the present inventor brings the concept of “specific value” to the multi-value logic, and determines whether “the input numerical value is relative to the specific value, whether it is large, small, equal or not equal. The function is limited to a function of performing a multi-value logic process and outputting a specific potential or a specific voltage corresponding to the specific value according to the processing result or releasing the output. Therefore, the multi-value logic function can be expressed in human language, and the function can be known from the multi-value logic circuit name named by the present inventor. For example, the circuit name means the following function. "Judgment" is "determining whether it is equal to a specific value", "NOT" is the complementary output opposite to "determination", "AND" is "all is", "NAND" is the opposite of "AND""OR" is "at least one is ~", "NOR" is the complementary output opposite to "OR", "OVER" is "is greater than a specific value", "NOVER ( "Nober)" is the opposite of "OVER", that is, "is it less than or equal to a specific value", "Under" is "is less than a specific value", "NUNDER" is "UNDER" Is the opposite output, that is, “is greater than or equal to a specific value”. Furthermore, each of “AND” and “OR” can be combined with “OVER”, “UNDER”, “NOVER”, and “NUNDER”. The specific details are as follows.
In both the first and second inventions, unless different output voltages are output at the same time, output means (eg, output terminals, etc.) of a plurality of multi-value logic circuits are connected to each other {, depending on circumstances, input means (eg, input terminals). Etc.) can also be connected to develop and enhance logic functions. Both inventions have such a degree of freedom, and are free-open, advanced multi-value logic circuits.

In the multi-value logic circuit named by the present inventor as "multi-value specific value determination circuit", the "input numerical value corresponding to the input potential or input voltage" is the same as the specific value (preset integer value) of the circuit The “specific potential (or specific voltage) corresponding to the specific value” is output, otherwise the output is opened. It should be noted that the multi-value number (N of N values. For example, 10 for 10 values, hereinafter referred to as this) N is (N−1) ≧ specific value ≧ 0. For 10 values, 9 ≧ specific value ≧ 0.
Example: FIGS. 1-5, 31-35.
A circuit that negates this judgment output, that is, a “complementary output circuit in which the output of the specific potential is opposite to the output of the output, is the opposite” is a multi-value logic circuit that the present inventor named “multi-value specific value NOT circuit”. .
Example: FIGS. 6-8, 36. FIG.
The multi-value logic circuit named by the present inventor as a “multi-value specific value AND circuit” indicates that when all of “a plurality of input numerical values corresponding to a plurality of input potentials or voltages” are the same as the specific value of the circuit, A specific potential (or a specific voltage) corresponding to the specific value is output. Otherwise, the output is released.
Example: FIGS. 9 to 10 and FIGS. 37 to 38.
The circuit that negates the AND output, that is, the “complementary output circuit in which the output of the specific potential and the output release are the opposite of each other” is a multi-value logic circuit named by the present inventor as a “multi-value specific value NAND circuit”. Example: FIGS. 11-12.
The multi-value logic circuit named “multi-value AND circuit” by the present inventor is a circuit that combines a plurality of “multi-value specific value AND circuits”. Output potential or voltage, otherwise open the output.
A multi-value logic circuit named by the present inventor as a “multi-value specific value OR circuit” has at least one of “a plurality of input numerical values corresponding to a plurality of input potentials or input voltages” as a specific value of the circuit. When they are the same, a “specific potential (or specific voltage) corresponding to the specific value” is output, and when not, the output is released.
Example: FIG.
The circuit that negates the OR output, that is, the “complementary output circuit in which the output of the specific potential is opposite to the output of the output, is the opposite” is a multi-value logic circuit named by the present inventor as a “multi-value specific value NOR circuit”. .
Example: FIG.

A multi-value logic circuit named by the present inventor as a “multi-value specific value OVER (over) circuit” has a “input value corresponding to an input potential or input voltage” larger than a specific value of the circuit. "Corresponding specific potential (or specific voltage)" is output, otherwise the output is opened.
Example: FIG. 15 {However, the magnitude of the on / off threshold voltage of the transistor 2 is larger than the difference between the two power supply potentials Vm · V (m−1), and the transistor 2 is off when the input numerical value ≦ the specific value m. The output is released. }
Example: FIG. 18 {However, the on / off threshold voltage of the transistor 1 is smaller than the difference between the two power supply potentials V (m + 1) · Vm, and the transistor 1 is on when the input numerical value ≦ the specific value m. 40 is off and its output is opened. }
A circuit that negates this OVER output, that is, a “complementary output circuit in which the output of the specific potential is opposite to the output of the specific output” is the multi-value logic named by the present inventor as the “multi-value specific value NOVER circuit”. Circuit. This circuit outputs its specific potential when the input numerical value is smaller than or equal to the specific value of the circuit, and opens its output otherwise.
Example: FIG. 16 {However, the magnitude of the on / off threshold voltage of the transistor 1 is smaller than the difference between the two power supply potentials V (m + 1) · Vm, and when the input numerical value ≦ the specific value m, the transistor 1 is on. A specific potential Vm is output. }
Example: FIG. 17 {However, the magnitude of the on / off threshold voltage of the transistor 2 is larger than the difference between the two power supply potentials Vm · V (m−1), and the transistor 2 is off when the input value ≦ the specific value m. The transistor 39 is on and a specific potential Vm is output. }

In the multi-value logic circuit named “multi-value specific value AND / OVER circuit” by the present inventor, all of “a plurality of input numerical values corresponding to a plurality of input potentials or input voltages” are larger than the specific value of the circuit. At that time, a “specific potential (or a specific voltage) corresponding to the specific value” is output, otherwise the output is opened.
Example: FIG. 19 {However, the on / off threshold voltages of the transistors 2a to 2d are larger than the difference between the two power supply potentials Vm · V (m−1), and at least one input numerical value ≦ specific value m At this time, the transistors 2a to 2d are off and their outputs are opened. }
Example: FIG. 26 {However, the magnitude of each on / off threshold voltage of the transistors 1a to 1d is smaller than the difference between both power supply potentials V (m + 1) · Vm, and at least one input numerical value ≦ a specific value m At least one of them is on, the transistor 40 is off, and its output is open. }
A circuit that negates the AND / OVER output, that is, a “complementary output circuit in which the output of the specific potential is opposite to the output of the output is the opposite” is a multi-value that the inventor named “multi-value specific value NAND / OVER circuit”. It is a logic circuit. This circuit outputs the specific potential when at least one of a plurality of input numerical values is smaller than or equal to the specific value of the circuit, and opens the output otherwise.
Example: FIG. 20 {However, the on / off threshold voltages of the transistors 2a to 2d are larger than the difference between both power supply potentials Vm · V (m−1), and at least one input numerical value ≦ specific value m At this time, the transistors 2a to 2d are off, the transistor 39 is on, and the specific potential Vm is output. }
Example: FIG. 25 {provided that the on / off threshold voltages of the transistors 1a to 1d are smaller than the difference between both power supply potentials V (m + 1) · Vm, and at least one input numerical value ≦ a specific value m At least one of them is on, and a specific potential Vm is output. }

A multi-value logic circuit named by the present inventor as a “multi-value specific value OR / OVER circuit” has at least one of “a plurality of input numerical values corresponding to a plurality of input potentials or input voltages”. When the value is larger than the value, “a specific potential (or a specific voltage) corresponding to the specific value” is output, and when not, the output is released.
Example: FIG. 23 {However, the on / off threshold voltages of the transistors 2a to 2d are larger than the difference between the two power supply potentials Vm · V (m−1), and all input numerical values ≦ specific value m Transistors 2a-2d are off and their outputs are opened. }
Example: FIG. 22 {However, the on / off threshold voltages of the transistors 1a to 1d are smaller than the difference between the two power supply potentials V (m + 1) · Vm, and all the input numerical values ≦ the specific value m. ˜1d is on, transistor 40 is off, and its output is open. }
The circuit that negates the OR / OVER output, that is, the “complementary output circuit in which the output of the specific potential is opposite to the output of the specific output” is the multi-value that the present inventor named “multi-value specific value NOR / OVER circuit”. It is a logic circuit. The circuit outputs the specific potential when all of the plurality of input numerical values are smaller than or equal to the specific value of the circuit, and opens the output otherwise.
Example: FIG. 24 {However, the magnitudes of the on / off threshold voltages of the transistors 2a to 2d are larger than the difference between the two power supply potentials Vm · V (m−1), and all input numerical values ≦ specific value m The transistors 2a to 2d are off, the transistor 39 is on, and the specific potential Vm is output. }
Example: FIG. 21 {However, the on / off threshold voltages of the transistors 1a to 1d are smaller than the difference between the two power supply potentials V (m + 1) · Vm, and all the input numerical values ≦ the specific value m. ˜1d is on, and a specific potential Vm is output. }

The multi-value logic circuit named “multi-value specific value UNDER (under) circuit” by the present inventor is “corresponding to the specific value” when the “input numerical value corresponding to the input potential or voltage” is smaller than the specific value of the circuit. Output a specific potential (or specific voltage) ", otherwise open the output.
Example: FIG. 16 {However, the magnitude of the on / off threshold voltage of the transistor 1 is larger than the difference between the two power supply potentials V (m + 1) · Vm, and when the input numerical value ≧ the specific value m, the transistor 1 is off. Its output is released. }
Example: FIG. 17 {However, the magnitude of the on / off threshold voltage of the transistor 2 is smaller than the difference between the two power supply potentials Vm · V (m−1), and the transistor 2 is on when the input numerical value ≧ the specific value m. Transistor 39 is off and its output is opened. }
The circuit that negates the UNDER output, that is, the circuit of the complementary output in which the output of the specific potential is opposite to the output of the output is the multi-value logic named by the present inventor as the “multi-value specific value NUNDER circuit”. Circuit. This circuit outputs its specific potential when the input value is greater than or equal to the specific value of the circuit, and opens its output otherwise.
Example: FIG. 15 {However, the magnitude of the on / off threshold voltage of the transistor 2 is smaller than the difference between the two power supply potentials Vm · V (m−1), and the transistor 2 is on when the input numerical value ≧ the specific value m. Thus, the specific potential Vm is output. }
Example: FIG. 18 {However, the magnitude of the on / off threshold voltage of the transistor 1 is larger than the difference between the two power supply potentials V (m + 1) · Vm, and the transistor 1 is off when the input numerical value ≧ the specific value m. 40 is ON, and a specific potential Vm is output. }

In the multi-value logic circuit named “multi-value specific value AND / UNDER circuit” by the inventor, all of “a plurality of input numerical values corresponding to a plurality of input potentials or input voltages” are smaller than the specific value of the circuit. At that time, a “specific potential (or a specific voltage) corresponding to the specific value” is output, otherwise the output is opened.
Example: FIG. 21 {However, the on / off threshold voltages of the transistors 1a to 1d are larger than the difference between both power supply potentials V (m + 1) · Vm, and at least one input numerical value ≧ specific value m Transistors 1a-1d are off and their outputs are opened. }
Example: FIG. 24 {However, the on / off threshold voltages of the transistors 2a to 2d are smaller than the difference between the power supply potentials Vm · V (m−1), and at least one input numerical value ≧ specific value m At least one of them is on, the transistor 39 is off, and its output is open. }
The circuit that outputs the negative of the AND / UNDER output, that is, the “complementary output circuit in which the output of the specific potential is opposite to the output of the specific output” is named as “multi-value specific value NAND / UNDER circuit” by the present inventor. It is a multi-value logic circuit. This circuit outputs a specific potential when at least one of a plurality of input numerical values is greater than or equal to a specific value of the circuit, and opens the output otherwise.
Example: FIG. 22 {However, the on / off threshold voltages of the transistors 1a to 1d are larger than the difference between both power supply potentials V (m + 1) · Vm, and at least one input numerical value ≧ specific value m The transistors 1a to 1d are off, the transistor 40 is on, and the specific potential Vm is output. }
Example: FIG. 23 {However, the on / off threshold voltages of the transistors 2a to 2d are smaller than the difference between the two power supply potentials Vm · V (m−1), and at least one input numerical value ≧ specific value m At least one of them is on, and a specific potential Vm is output. }

A multi-value logic circuit named by the present inventor as a “multi-value specific value OR / UNDER circuit” has at least one of “a plurality of input numerical values corresponding to a plurality of input potentials or input voltages”. When the value is smaller than the value, “a specific potential (or a specific voltage) corresponding to the specific value” is output, and when not, the output is released.
Example: FIG. 25 {However, the on / off threshold voltages of the transistors 1a to 1d are larger than the difference between both power supply potentials V (m + 1) · Vm, and all input numerical values ≧ specific value m, the transistor 1a ˜1d is off and its output is open. }
Example: FIG. 20 {However, the on / off threshold voltages of the transistors 2a to 2d are smaller than the difference between the two power supply potentials Vm · V (m−1), and all input numerical values ≧ specific value m Transistors 2a-2d are on, transistor 39 is off, and its output is open. }
The circuit that outputs the negative of the OR / UNDER output, that is, the “complementary output circuit in which the output of the specific potential is opposite to the output of the specific output” is named by the present inventor as “multi-value specific value NOR / UNDER circuit”. It is a multi-value logic circuit. The circuit outputs the specific potential when all of the plurality of input numerical values are greater than or equal to the specific value of the circuit, and opens the output otherwise.
Example: FIG. 26 {However, the on / off threshold voltages of the transistors 1a to 1d are larger than the difference between the two power supply potentials V (m + 1) · Vm, and the number of inputs is equal to or greater than the specific value m. 1a to 1d are off, the transistor 40 is on, and the specific potential Vm is output. }
Example: FIG. 19 {However, the on / off threshold voltages of the transistors 2a to 2d are smaller than the difference between the two power supply potentials Vm · V (m−1), and all the input values ≧ specific value m When the transistors 2a to 2d are on, the specific potential Vm is output. }

Note that “AND”, “NAND”, “OR” or “NOR” and “NOVER” or “NUNDER” can be combined, but each of these combination circuits and each of the above combination circuits is as follows. The actual functions are the same one by one.
a) Multi-value specific value AND / NUNDER circuit = Multi-value specific value NOR / UNDER circuit b) Multi-value specific value NAND / NUNDER circuit = Multi-value specific value OR / UNDER circuit c) Multi-value specific value OR / NUNDER circuit = Multi Value specific value NAND / UNDER circuit d) Multi-value specific value NOR / NUNDER circuit = Multi-value specific value AND / UNDER circuit e) Multi-value specific value AND / NOVER circuit = Multi-value specific value NOR / OVER circuit f) Multi-value specific Value NAND / NOVER circuit = multi-value specific value OR / OVER circuit g) multi-value specific value OR / NOVER circuit = multi-value specific value NAND / OVER circuit h) multi-value specific value NOR / NOVER circuit = multi-value specific value AND / OVER circuit

The multi-value logic circuit named by the inventor as “multi-value specific value AND / OVER-OR-AND / UNDER circuit” is a circuit in which “a plurality of numerical values corresponding to a plurality of input potentials or input voltages” are all circuits. When the value is larger or smaller than the specified value, “a specific potential (or a specific voltage) corresponding to the specific value” is output, and when not, the output is released.
Example: FIG. 28 {however, the on / off threshold voltages of the transistors 1a to 1c are smaller than the difference between the power supply potentials Vm and V (m-1), and the transistors 2a to 2c are turned on. The magnitude of the off threshold voltage is smaller than the difference between both power supply potentials V (m + 1) · Vm, and “when all input numerical values> specific value m” or “when all input numerical values <specific value m” transistor 2a .About.2c or transistors 1a.about.1c are on and a specific potential Vm is output. }
The circuit that outputs the negation of the AND / OVER-OR-AND / UNDER output, that is, the “complementary output circuit in which the output of the specific potential and the output opening are opposite to each other” is “the multi-value specific value NAND. It is a multi-value logic circuit named “OVER-OR-NAND • UNDER circuit”. This circuit releases its output when all of a plurality of input numerical values are larger or smaller than a specific value of the circuit, and outputs its specific potential otherwise.
Example: FIG. 27 {However, the on / off threshold voltages of the transistors 1a to 1c are smaller than the difference between the power supply potentials V (m + 1) and Vm, and the on / off states of the transistors 2a to 2c. The magnitude of the threshold voltage is smaller than the difference between the two power supply potentials Vm · V (m−1), and “when all input numerical values> specific value m” or “when all input numerical values <specific value m” transistor 1a ˜1c or transistors 2a-2c are off and their outputs are open. }
Embodiment: FIGS. 29 to 30 {However, the conditions of the magnitudes of the on / off threshold voltages of the transistors 1a to 1c and 2a to 2c are the same as those of the circuit of FIG. The logic processing operation is the same as that of the circuit of FIG. }

In the multi-value logic circuit disclosed in Japanese Patent Application Laid-Open No. 2003-204259, basically two switching means are connected in series between both ends of a power source, and furthermore, both input driving units are completely independent, thereby causing a power supply short circuit due to simultaneous ON. It cannot be used with combinations of input signals and input variables, and it is necessary to pay particular attention to the usage. Moreover, the potential difference (= voltage) between the power supply potential and the power supply potential corresponding to the numerical values is not constant, that is, the potential differences are not equal. Therefore, even in a binary logic circuit, there is a common noise margin (noise margin). It is not taken into consideration and is incomplete as a logic circuit.
For example, in the case of ternary 3 inputs (FIG. 1 of this prior patent), there are only 4 combinations in the truth table (FIG. 2 of this prior patent) even though there are 27 combinations of input variables. It is not described and is extremely inefficient as a multi-value logic processing function. Further, the power supply potentials corresponding to the three values are “0”, “3.0”, and “3.5” volts, and the potential differences are not equal and are offset, and malfunctions easily occur due to noise. Furthermore, the combinations of input variables that cause a power supply short circuit occupy nearly half of all combinations, and if the power supply potential difference is set equal, the number of occupations of the power supply short circuit combination becomes larger than the majority of the total.

On the other hand, there is a multi-value logic circuit of the special table 2002-517937 which can be said to have a multi-value logic processing function. FIG. 39 shows the basic circuit (three-value one-input) of this Omoto which has been simplified for the sake of explanation. The circuit diagram of the patent publication is correct because it is an error (the normally-on display and the normally-off display of the gate-insulated FET are opposite to each other).
In the circuit of FIG. 39, two normally-on (depletion mode) P and N-channel gate-insulated FETs (Q2 and Q3) are used as output means for outputting an intermediate potential V1 between the highest potential V2 and the lowest potential V0. Bidirectional switching means in which are connected in series is used. In addition, the circuit of FIG. 39 can also detect whether the “input numerical value corresponding to the input potential” corresponds to “the numerical value corresponding to the intermediate potential” by “zero gate voltages of both transistors Q2 and Q3”. “On driving”, that is, “a characteristic that both transistors Q2 and Q3 are turned on when the potential difference (= voltage) between the input potential and the intermediate potential V1 is zero” is used.
The combined use of the output means and the detection means has an advantage that the number of parts is small for the logic function and the circuit configuration is simple. In the operation, if the input potential is V0, the output potential is V2, if the input potential is V1, the output potential is V1, and if the input potential is V2, the output potential is V0.

  Note that two P- and N-channel junction FETs cannot be used in place of these gate-insulated FETs. This is because when the transistor Q3 is a P-channel junction FET, when the input potential is V0 and the transistor Q1 is on, a power supply short-circuit current flows from the transistor Q1 to the input terminal In via the drain-gate PN junction of the transistor Q3. It is because it ends. On the other hand, when the transistor Q2 is an N-channel junction FET, the gate-drain PN junction of the transistor Q2 clamps the upper limit of the input potential to the power supply potential V1, and a power supply short-circuit current flows again. In addition, since the gates and sources of the transistors Q2 and Q3 are connected in parallel, when a junction FET is used, both PN junctions are connected in reverse parallel, and a sufficient gate reverse bias voltage is applied to each. Because it is not possible.

Problem 1

For this reason, the first problem is that “a gate-isolated normally-on FET must be used as a part of it”, that is, “it is desired to be configured without using a normally-on gate-isolated FET”. There are points.
If normally-off type switching means can be used for all switching means, it is convenient to increase the number of parts to be used. Similarly, if bipolar mode transistors can be used, it is convenient to increase the number of parts to be used.

Problem 2

Further, there is a second problem that “a multi-value logic circuit having four or more values causes a power supply short-circuit current to flow transiently when the power is turned on”.
This is because in the case of a multi-value logic circuit having four or more values, there are two or more intermediate power supply potentials described above, and each of the intermediate power supply potentials is “both two normally-on gate-insulated FETs connected in series as described above. Since the “directional switching means” are connected one by one, at least one or more “combinations in which two normally-on bidirectional switching means are connected between two power supply potentials (= between both power supply ends)” Because there is. As a result, for example, in the case of a quaternary logic circuit, each gate voltage is zero before the power is turned on, and the bidirectional switching means is in the on state, and after the power is turned on, each power supply voltage rises and at least one bidirectional switching is performed. This is because the power supply short-circuit current flows until a sufficient gate reverse bias voltage is applied to each gate of the means. The problem with this power supply short circuit is that if a digital circuit is configured using a large number of multi-valued logic circuits, a very large power supply short-circuit current will flow when the power is turned on, and the power supply voltage cannot be raised, making it unusable. Or the power line is burned out by repeated power-on, or the semiconductor near the power line is damaged by thermal damage or distortion.

Problem 3

Furthermore, the third is that there are multi-valued logic processing functions that cannot be realized and unknown multi-valued logic processing functions because bidirectional switching means for limiting the relationship between the input voltage and the output voltage is used. There is a problem.
First, “restriction of relationship between input voltage and output voltage” will be described. For the sake of explanation, consider a case where the transistors Q1 and Q4 are removed from the circuit of FIG. 39 and the power supply potential V0 (0 volts) is input to the input terminal In. Here, if the potential of the output terminal Out becomes V0 for some reason, the drain and the gate of the P-channel transistor Q3 are “the same potential”, that is, “substantially the same as being directly connected”. . For this reason, since the transistor Q3 becomes conductive, both source potentials of the transistors Q3 and Q2 eventually become the potential V0, that is, the gate-source voltages of the transistors Q3 and Q2 become zero. As a result, normally-on transistors Q3 and Q2 are completely turned on, so that both transistors Q3 and Q2 short-circuit between the power supply potentials V1 and V0.
In order to prevent this power supply short circuit, when the input potential is V0 (0 volt), the source potential of the transistor Q2 is set to plus 1.75 volts or more, and the gate-source voltage of the transistor Q2 is set to the on / off threshold value. The voltage must be minus 1.75 volts or less. At this time, since the transistor Q3 is turned on, the potential of the output terminal Out is also set to plus 1.75 volts or more. That is, when the input potential is V0, the output potential must be plus 1.75 volts or more. That is, the “circuit of FIG. 39 assuming that the transistors Q1 and Q4 are removed for explanation” can only be used in this way.
This is the same even when the input potential is V2 (5 volts), the positions of the transistors Q2 and Q3 are switched, and the output potential must be (V2-1.75 volts) = plus 3.25 volts or less. . In fact, in the original circuit of FIG. 39, the transistor Q1 pulls up the output potential to V2 when the input potential is V0, and the transistor Q4 pulls down the output potential to V0 when the input potential is V2. Accordingly, when the input potential is V0, the output potential V0 cannot be output or released, and when the input potential is V1, the output cannot be opened, and the input potential is V2. In this case, the output potential V2 cannot be output or the output cannot be opened. For this reason, the relationship between the input voltage and the output voltage is limited in the circuit of FIG. 39 and the “circuit in which the transistors Q1 and Q4 are removed from the circuit of FIG. 39”.

Next, the super-explosive size of the kind of multi-valued logic processing considered mathematically will be described. In the case of a binary two-input logic circuit, there are four combinations of input variables, that is, the square of 2 = 4 sets, and there are two ways of output in each of the four sets, “0” and “1”. The types of logic processing and logic functions are 2 4 = 16 types.
Reference: "Introduction to Transistor Circuit Lecture 5: Digital Circuit Concept" {Om Corp., issued May 20, 1981} p. 34 “Table 3. 8 Logical functions consisting of two input variables”.
Similarly, in the case of a ternary two-input multi-value logic circuit, there are 9 combinations of input variables: the square of 3 = 9 sets. In each of the 9 sets, the output method is “0”, “1”, “ 2 ”, there are 3 kinds of logic processing and logic functions, ie, the ninth power = 19,683.
Similarly, in the case of quaternary 2 input, there are 4 16 = 4,294,968,000 types, and in the case of quinary 2 input, 5 25 = 2.980233 × (10 to the 17th power) is there.
Thus, as the number of multi-values (for example, N for N values, 10 for 10 values, and so on) is increased, the types of multi-value logic processing increase super-explosively. This means that if a multi-value logic circuit having a multi-value logic processing function optimal for “required logic processing” is realized and selected, even a small number of circuits can cope with “various logic processing required”. This is similar to software programming in terms of problem-handling ability and suggests that new and tremendous possibilities may be buried in multi-valued logic and multi-valued logic. . Perhaps multi-digit computers, especially decimal computers, may outperform binary quantum computers. It should be noted that logical functions and logical processing seem to have “meaningful” and “nonsense”, so even if the number of “significant logical processing” is a fraction of the total, There is no change in the increase in super and explosive.

Therefore, even though the number of multi-valued logic circuits disclosed in the special table 2002-517937 is large, given the above-mentioned “ultra-explosive enormous number of types of multi-value logic processing”, It is insignificant. Then, it is very significant to provide a multi-value logic circuit capable of executing “multi-value logic processing not yet realized” and “unknown multi-value logic processing”.
For that reason, “there is a bi-directional switching means that limits the relationship between the input voltage and the output voltage, so there are multi-value logic processing functions that have not been realized and unknown multi-value logic processing functions” There is a third problem.

Problem 4

“Other multi-value logic circuits and output means (eg, output terminals, output electrodes, drain electrodes, etc.) cannot be connected to develop and enhance multi-value logic functions, nor can they change functions.” In other words, there is a fourth problem that “it is desirable to be able to perform a multi-valued logic output method of releasing the output”.
Since the multi-value logic circuit of JP-T-2002-517937 prioritizes “small number of parts” and fixes its function, the other multi-value logic circuit cannot be connected to the output means. If it is connected forcibly, a power supply short circuit will occur. For example, it is impossible to change the output voltage by connecting a pull-up resistor or a pull-down resistor.
Therefore, if there is an “opening output” method (for example, an output method called an open collector in a binary logic circuit) as a multi-value logic output method, a plurality of output values can be used as long as different output voltages are not output simultaneously. Connect output means of multi-valued logic circuits freely {and optionally connect input means (eg, input terminals, input electrodes, gate electrodes, etc.)} to supplement the lack of functions Accordingly, the multi-value logic function can be flexibly developed and enhanced in accordance with “required multi-value logic processing”. Also, the output voltage can be freely changed by connecting, for example, a pull-up resistor or a pull-down resistor.
The flexible function development / enhancement capability and function change capability are very advantageous for flexibly responding to the above-mentioned “ultra-explosive enormous amount of multi-valued logic processing”.
That's why "You cannot connect other multi-value logic circuits and output means to develop and enhance multi-value logic functions, and you cannot change the function", that is, "Multi-value logic that opens output" There is a fourth problem that it is desirable to be able to output.

Problem 5

There is a fifth problem that “it is desirable to know the multi-value logic processing function from the multi-value logic circuit name”.
As mentioned above, the number of types of multi-valued logic processing increases enormously and explosively, so it was not very memorable and couldn't cope with the fact that it was written in the truth table one by one. That is absolutely impossible. For example, the most convenient multi-decimal system for a person (person) is the decimal system, but in the case of a 10-value 3-input logic circuit, there are 1,000 combinations of only combinations of input variables.
Therefore, if it is possible to know the multi-value logic processing function immediately from the multi-value logic circuit name, it is kind to humans and is very convenient. It is indispensable for the practical use of decimal computers and the like.

  Each embodiment of the special table 2002-517937 is an application and development of the basic circuit of FIG. 39, and a plurality of P or N-channel gate insulation types depending on the number of input signals and multi-level logic processing function. Although FETs are complicatedly connected in series or connected in parallel, the basic operation of the normally-on bidirectional switching means is the same. In short, the method described in paragraph [0017] is used in a steady state after power-on. A plurality of bidirectional switching means are connected in series and in parallel to one intermediate potential, and at least one of them is used as described above. This usage is such that even in the case of a logic circuit having four or more values, “bidirectional switching means having different potentials” are not simultaneously turned on in a steady state after power-on. However, when the output signal is switched at the time of switching the input signal, it may be turned on simultaneously in a transient manner. In the circuit of FIG. 39, the transistors Q1 to Q3 are simultaneously turned on while the input potential is between (2.5-1.75) = 0.75 volts and (5-3.25) = 1.75 volts. Then, the transistors Q2 to Q4 are simultaneously turned on even when the input potential is between 3.25 volts and (2.5 + 1.75) = 4.25 volts. Accordingly, it is necessary to prevent the input potential from being long and staying between these potentials. However, it is inevitable that the switching power loss increases due to the power supply short-circuit due to simultaneous ON when the input signal is switched.

  JP2003-204259 (multi-valued logic circuit)   Special table 2002-517937 (multi-valued logic circuit)   Japanese Patent Application No. 2003-109619 (Prior application of the present inventor, same invention)   Patent No. 3423780 (inventor's bidirectional insulated switch)   "Introduction to Transistor Circuit Lecture 5: Digital Circuit Concept" published by OHM Co., Ltd. on May 20, 1986. p. 34 “Table 3. 8 Logical functions consisting of two input variables”.   Patent No. 2853041 (related application, multi-value storage means of the present inventor)   JP 2000-83369 (same as above)   Japanese Patent Application No. 2001-32972 (same as above)   WO 03/028214 A1 (same as above)   Japanese Patent Application No. 2001-402788 (same as above)   Japanese Patent Application No. 2003-203347 (same as above)

Disclosure of the first invention

Problems to be solved by the first invention

Therefore, there are three conventional problems as follows. (Task)
a) It is desirable to be able to configure without using a normally-on gate insulated FET.
b) In the case of a multi-value logic circuit having four or more values, a power supply short-circuit current flows transiently when the power is turned on.
c) It is desirable that a multi-valued logic output method of releasing the output is possible.

SUMMARY OF THE INVENTION Accordingly, an object of the first invention is to provide the following multi-value logic circuit.
(Object of the first invention)
a) It can be configured without using a normally-on gate insulated FET.
b) Only when a normally-off type is used for the bidirectional switching means of the output section, a transient power supply short-circuit current due to the normally-on type does not flow when the power is turned on even in the case of a multi-valued logic circuit having four or more values. .
c) A multi-valued logic output method in which the output is released can be performed.

Means to solve the problem

That is, the first invention is a multi-value logic circuit according to claim 1. Each of one or more bidirectional switching means of the output unit “bidirectional switching means in which the output terminal side switch terminal and the switch drive unit are bi-directionally turned off when driven off” It is characterized by using one by one.
One means may also serve as a plurality of means. The N indicates a multi-value (3 ≧) number, and the numerical value is 0 to (N−1). The first potential represents the numerical value 0, the second potential represents the numerical value 1,..., And the Nth potential represents the numerical value (N−1). If a certain signal potential is lower than “a positive threshold potential with respect to the first potential”, the signal potential represents the numerical value 0. If a signal potential is “between a negative threshold potential and a positive threshold potential with respect to the second potential”, the signal potential represents the numerical value 1, and a certain signal potential is similarly ( N-1) If the potential is between both threshold potentials up to the potential, the signal potential represents each numerical value up to the numerical value (N-2). If a certain signal potential is higher than “a negative threshold potential based on the Nth potential”, the signal potential represents a numerical value (N−1).

Effects of the first invention

This eliminates the need to use both the detecting means for detecting the input potential and the bidirectional switching means for output (although of course, they may be used together). It can also be configured using off-type switching means.
(Effect 1 of the first invention)
Also, only when the normally-off type is used as the bidirectional switching means for output, a transient power supply short-circuit current does not flow when the power is turned on, unlike the normally-on type.
(Effect 2 of the first invention)
Furthermore, since “bidirectional switching means that can be turned off in both directions” is used for each “bidirectional switching means that outputs an intermediate potential between the second potential and the (N−1) th potential”, each output The multi-valued logic output method of releasing the
(Effect 3 of the first invention)

Disclosure of the second invention

Problems to be solved by the second invention

Therefore, there are four conventional problems as follows. (Task)
a) It is desirable to be able to configure without using a normally-on gate insulated FET.
b) In the case of a multi-value logic circuit having four or more values, a power supply short-circuit current flows transiently when the power is turned on.
c) Since bidirectional switching means for limiting the relationship between the input voltage and the output voltage is used, there are a multi-value logic processing function that cannot be realized or a multi-value logic processing function that is not known.
d) It is desired that a multi-value logic output method of releasing the output can be performed.

Accordingly, the second invention aims to provide the following multi-value specific value logic circuit.
(Object of the second invention)
a) It can be configured without using a normally-on gate insulated FET.
b) Only when a normally-off type is used for the bidirectional switching means of the output section, a transient power supply short-circuit current due to the normally-on type does not flow when the power is turned on even in the case of a multi-valued logic circuit having four or more values. .
c) A circuit having a multi-valued logic processing function that cannot be realized by a conventional circuit or a multi-valued logic processing function that is not known can be realized “independently”.
d) A multi-value logic output method in which the output is released can be performed.

Means to solve the problem

  That is, the second invention is a multi-value specific value logic circuit according to claim 2. The N indicates a multivalued number (3 ≧), and the numerical value is 0 to (N−1). The first potential represents the numerical value 0, the second potential represents the numerical value 1,..., And the Nth potential represents the numerical value (N−1). If a certain signal potential is lower than “a positive threshold potential with respect to the first potential”, the signal potential represents the numerical value 0. If a signal potential is “between a negative threshold potential and a positive threshold potential with respect to the second potential”, the signal potential represents the numerical value 1, and a certain signal potential is similarly ( N-1) If the potential is between both threshold potentials up to the potential, the signal potential represents each numerical value up to the numerical value (N-2). If a signal potential is higher than “a negative threshold potential with reference to the Nth potential”, the signal potential represents a numerical value (N−1).

The output potential pulling means is connected between one of the first to Nth potential supply means, the potential supply means of one specific potential and the output means, and when on, the potential of the output means is set to the specific potential. The output means is opened when it is off.
Further, the numerical value relation detecting means is based on “a positive or negative threshold potential determined in advance with reference to the specific potential”, and among “0 to (N−1), the first to S-th input means. A magnitude relationship between “each numerical value corresponding to each potential” and “a numerical value corresponding to the specific potential (hereinafter referred to as“ specific value ”)” or a relationship between equality or not equal is detected.
Then, the logic processing means performs processing based on “the detection result of the numerical value relation detecting means” and “predetermined multi-value logic”. The on / off driving means is controlled by the logic processing means to drive the output potential pulling means on / off.
However, one means may also serve as a plurality of means.

Effects of the second invention

This eliminates the need to use both the detection means for detecting the input potential and the output switching means (although of course both may be used), and the normally-off type switching means is provided for each of the detection means and the output means. You can configure it even if you use it.
(Effect 1 of the second invention)
Also, only when the normally-off type switching means is used as the output potential pulling means, a transient power supply short-circuit current does not flow when the power is turned on, unlike the normally-on type.
(Effect 2 of the second invention)
Furthermore, since the output potential pulling means that does not limit the relationship between the input voltage and the output voltage is used as the output switching means, the “multi-value logic processing function” or “unknown multi-value logic processing function” that cannot be realized with the conventional circuit Can be realized “independently”.
(Effect 3 of the second invention)
Then, since the “switching means having the required off function” is used as the output potential pull means, a multi-valued logic output method of releasing the output can be performed.
(Effect 4 of the second invention)

Best Mode for Carrying Out Each Invention

  In order to explain each invention in more detail, these will be described with reference to the accompanying drawings.

FIG. 1 shows an embodiment common to the first and second inventions, which is a multi-value logic circuit named by the present inventor as a “multi-value specific value determination circuit”. In the embodiment shown in FIG. 1, each component corresponds to each component described in claims 1 and 2, and S = 1. Then, n in the figure corresponds to N described above, and m corresponds to a specific value (a numerical value corresponding to a specific potential). There are relationships of “n ≧ 3”, “n−1 ≧ m + 1”, and “m−1 ≧ 0”, and this relationship can be applied to other embodiments described later.
a) power supply line V0,..., power supply line V (m-1), power supply line Vm, power supply line V (m + 1), ..., power supply line V (n-1), respectively. For each of the first potential supply means to the Nth potential supply means.
b) The input terminal In is an input means according to claims 1 and 2, respectively.
c) The output terminal Out is the output means in each of claims 1 and 2.
d) The potential of the power supply line Vm is set to the specific potential in claim 2.
e) The power supply line Vm is “one potential supply means of one specific potential” in claim 2.
f) "Bidirectional switching means connected between power supply line Vm and output terminal Out and constituted by transistors 3-6 and diodes 9-12" and the bidirectional switching means according to claim 1 2. To output potential pulling means described in 2.
In the case of this bidirectional switching means, each switch terminal and its on / off drive part (gate, source part) are completely turned off in both directions at the time of off driving, and the off state is the potential of each switch terminal. Not affected at all. (Reference: Patent No. 3,423,780)
g) "Connecting body of power supply line V (m + 1), power supply line V (m-1) and transistors 1-2" is the logic processing means according to claim 1. Then, both the numerical relationship detecting means and the logic processing means in claim 2.
The negative threshold potential of the specific value m is determined by the potential of the power supply line V (m−1) and the on / off threshold voltage of the transistor 2, and the positive threshold potential of the specific value m. Is determined by the potential of the power supply line V (m + 1) and the magnitude of the on / off threshold voltage of the transistor 1. In general, the negative threshold potential of the specific value m is not limited to the embodiment of FIG. 1, but is “the potential of the power supply line Vm” and “the middle potential of both potentials of the power supply line Vm · V (m−1)”. Set between. The positive threshold potential of the specific value m is set between “the middle potential of both the power supply lines V (m + 1) and Vm” and “the potential of the power supply line Vm”.
h) A connection body of the transistors 1 and 2, the Zener diodes 13 and 14, and the resistors 15 and 16 is the on / off driving means according to each of claims 1 and 2.

The operation of the embodiment of FIG. 1 is as follows. If the potential of the input terminal In is between the “minus threshold potential with respect to the potential of the power supply line Vm and the plus threshold potential”, the transistors 1 and 2 are simultaneously turned on. ˜6 are driven on. As a result, since the output terminal Out is bidirectionally connected to the power supply line Vm, the potential of the output terminal Out is pulled up or down to the potential of the power supply line Vm, and the output terminal Out has the potential of the power supply line Vm. Output. On the other hand, if the potential of the input terminal In is not between both the threshold potentials, one or both of the transistors 1 and 2 are turned off, and the resistors 15 and 16 drive the transistors 3 to 6 off, so that the output terminal Out is It becomes open. This bidirectional switching means cannot turn on the transistors 3 to 6 only by turning on one of the transistors 1 and 2.
Regarding the logical operation, the embodiment of FIG. 1 outputs a specific value m when the input numerical value (the numerical value corresponding to the input potential) is equal to the specific value m (the numerical value corresponding to the specific potential), and the input numerical value is the specific value m. When it is not equal, the output is released.

  It should be noted that the output terminal Out may be pulled up or down to a “power supply line other than the power supply line Vm” or “a power supply line other than the power supply line V0 to V (n−1)” by a resistor or the like. It is done. In addition, a method of “preparing a plurality of the embodiments of FIG. 1 whose specific potentials are different from each other, connecting the input terminals, and connecting the output terminals” is also conceivable. Further, if the relationship of the potential of the power supply line V0 ≦ the potential of the output terminal Out ≦ the potential of the power supply line V (n−1), the diodes 7 and 8 may be omitted, and the Zener diodes 13 and 14 are also omitted. It doesn't matter. Then, instead of the resistors 15 and 16, “junction FET or normally-on type MOS • FET in which the gate and the source are directly connected” can be used one by one as the resistance means. Then, instead of the diodes 9 to 12, “a normally-off type MOS circuit in which its gate, back gate and source are directly connected”, such as “each MOS FET connected to the output terminal in the embodiment of FIG. 30 to be described later”. "FET" can be used one by one. These also apply to each of the embodiments shown in FIGS. In addition, it is possible to use one N-channel IGBT instead of each of the transistors 3 and 4 and one P-channel IGBT instead of each of the transistors 5 and 6. In this case, the diodes 9 to 12 are not required if each IGBT is a reverse blocking type.

In the embodiment common to the first and second inventions of FIG. 2 named by the inventor as "multi-value specific value determination circuit", the bidirectional switching means in claim 1 and the output potential pull in claim 2 are provided. As a means, "bidirectional switching means formed by transistors 6, 3 and diodes 12, 9" and "unidirectional switching means formed by transistors 4, 5 and diodes 10, 11" are connected in reverse parallel. Since this means is used, two transistors, such as transistors 1a and 1b and transistors 2a and 2b, are required.
The embodiment of FIG. 2 is the same as the embodiment of FIG. 1 with respect to its logical operation, and outputs a specific value m when the input numerical value is equal to the specific value m, and opens the output when the input numerical value is not equal to the specific value m. To do.

  In the embodiment common to the first and second inventions of FIG. 3 named by the inventor as "multi-value specific value determination circuit", the bidirectional switching means in claim 1 and the output potential pull in claim 2 are provided. As a means, bidirectional switching means using a diode bridge connection type rectifier circuit is used. The embodiment shown in FIG. 3 is the same as the embodiment shown in FIGS. 1 and 2 with respect to the logical operation. When the input numerical value is equal to the specific value m, the specific value m is output. When the input value is not equal, the output is released.

In the embodiment common to the first and second inventions of FIG. 4 named by the inventor as "multi-value specific value determination circuit", the transistors 4 and 6 are turned on only when both the transistors 1 and 2 are on. The transistor 17 detects on / off of the transistor 2, and the transistor 18 detects on / off of the transistor 1. When both the transistors 1 and 2 are on, the series circuit of the transistors 1 and 17 drives the transistor 4 on, and the series circuit of the transistors 18 and 2 drives the transistor 6 on.
. The embodiment of FIG. 4 is the same as the embodiment of FIGS. 1 to 3 with respect to its logical operation. When the input numerical value is equal to the specific value m, the specific value m is output, and when the input value is not equal, the output is released.

In the embodiment common to the first and second inventions of FIG. 5 named by the inventor as “multi-value specific value determination circuit”, the detection means applying the conventional binary DTL (diode transistor logic circuit) is “ It is detected whether or not “a numerical value corresponding to the input potential (input numerical value)” is equal to “a numerical value corresponding to the potential (specific potential) of the power supply line Vm (specific value)”. Transistors 21 and 24 and diodes 10 and 12 constitute bidirectional switching means. When the input numerical value is the same as the specific value, the diode 25 bypasses the current of the resistor 33, the current of the resistor 34, the diode 27, the current of the resistor 36, the diode 29, and the current of the resistor 37 bypass the diode 31. As a result, the transistors 19, 20, 22, and 23 are off, and the transistors 21 and 24 and the diodes 10 and 12 bidirectionally connect the output terminal Out to the power supply line Vm.
Instead of each of the diodes 25 and 26 and the diodes 27 and 28, one “NPN transistor having two PN junctions” may be used, or each of the diodes 29 and 30 and the diodes 31 and 32 may be replaced with “PN”. One PNP transistor having two junctions may be used one by one. Usually, each emitter comes to the input side due to the magnitude of the forward voltage.
The embodiment of FIG. 5 is the same as the embodiment of FIGS. 1 to 4 with respect to the logical operation, and outputs a specific value m when the input numerical value is equal to the specific value m, and releases the output when it is not equal.

The embodiment common to the first and second inventions of FIG. 6 named by the inventor as “multi-value specific value NOT circuit” is obtained by adding an output inversion function to the embodiment of FIG. The transistors 20, 21, 23, 24 and the diodes 10, 12 constitute bidirectional switching means.
. With respect to the logical operation, the embodiment of FIG. 6 releases the output when the input numerical value is equal to the specific value m, and outputs the specific value m when the input numerical value is not equal to the specific value m.

The embodiment common to the first and second inventions of FIG. 7 named by the present inventor as a “multi-value specific value NOT circuit” uses another input potential detection method. The illustration is omitted except for the power supply line Vm. Instead of each diode, “PNP or NPN transistor in which collector and base are directly connected” may be used one by one. Instead of each PNP transistor, a P-channel type BSIT (bipolar mode static induction transistor) or GTBT (bipolar FET with a grounded groove electrode) may be used one by one, or each NPN transistor. Instead of N-channel type BSIT and GTBT, one by one may be used. These replacements can be similarly applied to FIGS. 5 and 6 and FIGS. 9 to 12, FIGS. 31 to 33, and FIGS.
The embodiment of FIG. 7 is the same as the embodiment of FIG. 6 with respect to its logical operation, and its output is released when the input numerical value is equal to the specific value m, and the specific value m is output when the input numerical value is not equal to the specific value m. To do.

The embodiment common to the first and second inventions of FIG. 8 named by the present inventor as “multi-value specific value NOT circuit” is the implementation of the embodiment of FIG. 7 with MOS • FET, except for the power supply line Vm. The illustration is omitted. An embodiment in which the input terminal In is pulled up to the power supply line V (m + 1) with a first resistor and pulled down to the power supply line V (m−1) with a second resistor is also possible.
The embodiment of FIG. 8 is the same as the embodiment of FIGS. 6 to 7 with respect to its logical operation. When the input numerical value is the same as the specific value m, the output is released, and when the input numerical value is different from the specific value m, the specific value m. Is output.

  The embodiment common to the first and second inventions of FIG. 9 named by the inventor as “multi-value specific value AND circuit” is the same as the embodiment of FIG. 1 except that “three transistors of the same type” are used instead of the transistor 1. Instead of the transistor 2, “three transistors of the same type” are connected in series, and three input terminals In1, In2, and In3 are provided. If each potential of the input terminals In1, In2, and In3 is between the above-described “negative threshold potential with respect to the potential of the power supply line Vm and positive threshold potential”, the output terminal Out is the power supply line Vm. On the other hand, if any one of the input terminals In1, In2, and In3 is not between the threshold potentials, the output terminal Out is opened. Accordingly, with respect to its logical operation, the embodiment of FIG. 9 outputs a specific value m when all three input numerical values are equal to the specific value m, and when at least one of the three input numerical values is not equal to the specific value m Release the output.

  The embodiment common to the first and second inventions of FIG. 10 named by the inventor as "multi-value specific value AND circuit" is an application of the embodiment of FIG. A multi-emitter (3-emitter) NPN transistor is used instead of each of the diodes 41-44 and 45-48, and a multi-emitter (3-emitter) is used instead of each of the diodes 49-52 and 53-56. ) Even if one PNP transistor is used one by one, it does not lie down. Usually, each emitter comes to the input side due to the magnitude of the forward voltage. This is also true for the embodiment shown in FIG. Further, the embodiment of FIG. 9 is the same as the embodiment of FIG. 10 in terms of its logical operation, and outputs a specific value m when all three input numerical values are equal to the specific value m, and at least one of the three input numerical values is When it is not equal to the specific value m, the output is released.

  The embodiment common to the first and second inventions of FIG. 11 named by the inventor as "multi-value specific value NAND circuit" is an application of the embodiment of FIG. With respect to its logical operation, the embodiment of FIG. 11 releases its output when all three input values are equal to a specific value m, and outputs a specific value m when at least one of the three input values is not equal to the specific value m. To do.

  The embodiment common to the first and second inventions of FIG. 12 named by the present inventor as "multi-value specific value NAND circuit" uses a multi-emitter PNP transistor and an NPN transistor. The embodiment of FIG. Is applied. The base part of the NPN transistor with common emitter is a binary diode OR circuit. Instead of this combination, “a binary transistor with four emitters connected to each other and four emitters connected to each other”. Alternatively, the “grounded-emitter PNP transistor side” can be used instead of a “binary transistor OR circuit in which four PNP transistors are connected in parallel and the emitter is grounded”. Further, the embodiment of FIG. 12 is the same as the embodiment of FIG. 11 with respect to its logical operation. When all three input numerical values are equal to the specific value m, the output is released, and at least one of the three input numerical values is specified. When it is not equal to the value m, the specific value m is output.

  In the embodiment common to the first and second inventions of FIG. 13 named by the present inventor as the “multi-value specific value OR circuit”, even if the potentials of the input terminals In1, In2, In3 are one, The output terminal Out outputs the potential of the power supply line Vm, while the potentials of the input terminals In1, In2, and In3 are all within the range between the negative threshold potential and the positive threshold potential with respect to the potential. If it is outside between the two threshold potentials, the output terminal Out is opened. In addition, in each circuit, each conducting wire which attached | subjected code | symbol a, b, c is in a connection state. Further, regarding the logical operation, the embodiment of FIG. 13 outputs the specific value m when at least one of the three input numerical values is equal to the specific value m, and outputs the output when all three input numerical values are different from the specific value m. Open.

  In the embodiment common to the first and second inventions of FIG. 14 named by the inventor as “multi-value specific value NOR circuit”, the “binary inverter circuit in which the transistor 39 and the resistor 57 are connected in series” in the embodiment of FIG. ”Is used to invert the on / off drive signal to output the complementary output of the multi-value specific value OR circuit. Regarding the logical operation, the embodiment of FIG. 14 releases the output when at least one of the three input numerical values is equal to the specific value m, and outputs the specific value m when all three input numerical values are different from the specific value m. .

The embodiment common to the first and second inventions in FIG. 15 is the “multi-value specific value OVER (over) circuit” named by the present inventor or “multi-value specific value NUNDER (nander)” according to the height of the input threshold potential. ) Circuit {= complementary output circuit of multi-value specific value UNDER (under) circuit}.
When the potential (or voltage) of the input terminal In is higher than the potential (or voltage) determined by the potential (or voltage) of the power supply line V (m−1) and the on / off threshold voltage of the transistor 2, the output terminal Out is the power source. The potential (or voltage) of the line Vm, that is, “a numerical value corresponding to the potential (or voltage) of the power supply line Vm” is output, otherwise the output terminal Out is opened.
Therefore, if the input threshold potential is higher than the positive threshold potential of the specific value m and lower than the negative threshold potential of the numerical value (m + 1), the embodiment of FIG. Become a circuit. On the other hand, if the input threshold potential is higher than the positive threshold potential of the numerical value (m−1) and lower than the negative threshold potential of the specific value m, the embodiment of FIG. It becomes a specific value NUNDER circuit.
As a result, the multi-value specific value OVER circuit outputs the specific value m when the input numerical value is larger than the specific value m, that is, outputs the potential of the power line Vm, while the input numerical value is smaller than or equal to the specific value m. The output terminal Out is opened. The multi-value specific value NUNDER circuit outputs the specific value m when the input numerical value is greater than or equal to the specific value m, that is, outputs the potential of the power line Vm, while outputting when the input numerical value is smaller than the specific value m. Open the terminal Out.

The embodiment common to the first and second inventions of FIG. 16 is a “multi-value specific value UNDER circuit” or “multi-value specific value NOVER (Nouver) circuit” named by the present inventor depending on the height of the input threshold potential. = Complementary output circuit of multi-value specific value OVER circuit).
When the potential (or voltage) of the input terminal In is lower than the potential (or voltage) determined by the potential (or voltage) of the power line V (m + 1) and the on / off threshold voltage of the transistor 1, the output terminal Out is connected to the power line Vm. Potential (or voltage), that is, "a numerical value corresponding to the potential (or voltage) of the power supply line Vm" is output, otherwise the output terminal Out is opened.
Therefore, if the input threshold potential is lower than the negative threshold potential of the specific value m and higher than the positive threshold potential of the numerical value (m−1), the embodiment of FIG. It becomes a value UNDER circuit. On the other hand, if the input threshold potential is lower than the negative threshold potential of the numerical value (m + 1) and higher than the positive threshold potential of the specific value m, the embodiment of FIG. It becomes a NOVER circuit.
As a result, the multi-value specific value UNDER circuit outputs the specific value m when the input numerical value is smaller than the specific value m, that is, outputs the potential of the power line Vm, while the input numerical value is greater than or equal to the specific value m. The output terminal Out is opened. The multi-value specific value NOVER circuit outputs a specific value m when the input numerical value is less than or equal to the specific value m, that is, outputs the potential of the power line Vm, while outputting when the input numerical value is larger than the specific value m. Open the terminal Out.

The embodiment common to the first and second inventions of FIG. 17 is “multilevel specific value NOVER circuit” or “multilevel specific value UNDER circuit” named by the present inventor depending on the height of the input threshold potential. .
When the potential (or voltage) of the input terminal In is higher than the potential (or voltage) determined by the potential (or voltage) of the power supply line V (m−1) and the on / off threshold voltage of the transistor 2, the output terminal Out is opened. Otherwise, the output terminal Out outputs the potential (or voltage) of the power supply line Vm, that is, “a numerical value corresponding to the potential (or voltage) of the power supply line Vm, a specific value m”.
Therefore, if the input threshold potential is higher than the positive threshold potential of the specific value m and lower than the negative threshold potential of the numerical value (m + 1), the embodiment of FIG. Become a circuit. On the other hand, if the input threshold potential is higher than the positive threshold potential of the numerical value (m−1) and lower than the negative threshold potential of the specific value m, the embodiment of FIG. It becomes a specific value UNDER circuit.
As a result, the multi-value specific value NOVER circuit outputs the specific value m when the input numerical value is smaller than or equal to the specific value m, that is, outputs the potential of the power line Vm, while the input numerical value is larger than the specific value m. The output terminal Out is opened. The multi-value specific value UNDER circuit outputs a specific value m when the input numerical value is smaller than the specific value m, that is, outputs the potential of the power line Vm, while outputting when the input numerical value is greater than or equal to the specific value m. Open the terminal Out.

The embodiment common to the first and second inventions in FIG. 18 is the “multi-value specific value NUNDER circuit” or “multi-value specific value OVER circuit” named by the present inventor depending on the height of the input threshold potential.
When the potential (or voltage) of the input terminal In is lower than the potential (or voltage) determined by the potential (or voltage) of the power supply line V (m + 1) and the on / off threshold voltage of the transistor 1, the output terminal Out is opened. Otherwise, the output terminal Out outputs the potential (or voltage) of the power supply line Vm, that is, “a numerical value corresponding to the potential (or voltage) of the power supply line Vm”.
Therefore, if the input threshold potential is lower than the negative threshold potential of the specific value m and higher than the positive threshold potential of the numerical value (m−1), the embodiment of FIG. It becomes a value NUNDER circuit. On the other hand, if the input threshold potential is lower than the negative threshold potential of the numerical value (m + 1) and higher than the positive threshold potential of the specific value m, the embodiment of FIG. It becomes an OVER circuit.
As a result, the multi-value specific value NUNDER circuit outputs the specific value m when the input numerical value is greater than or equal to the specific value m, that is, outputs the potential of the power line Vm, while the input numerical value is smaller than the specific value m. The output terminal Out is opened. The multi-value specific value OVER circuit outputs the specific value m when the input numerical value is larger than the specific value m, that is, outputs the potential of the power supply line Vm, while outputting when the input numerical value is smaller than or equal to the specific value m. Open the terminal Out.

The embodiment common to the first and second inventions of FIG. 19 is an application of the embodiment of FIG. 15, and the “multi-value specific value AND / OVER circuit named by the present inventor according to the height of the input threshold potential”. = Multi-value specific value NOR / NOVER circuit "or" Multi-value specific value AND / NUNDER circuit = Multi-value specific value NOR / UNDER circuit ".
Therefore, if the input threshold potential is higher than the positive threshold potential of the specific value m and lower than the negative threshold potential of the numerical value (m + 1), the embodiment of FIG. OVER circuit = multi-value specific value NOR / NOVER circuit On the other hand, if the input threshold potential is higher than the positive threshold potential of the numerical value (m−1) and lower than the negative threshold potential of the specific value m, the embodiment of FIG. Specific value AND · NUNDER circuit = multi-value specific value NOR · UNDER circuit.
As a result, the multi-value specific value AND / OVER circuit = multi-value specific value NOR / NOVER circuit outputs the specific value m when all the input numerical values are larger than the specific value m, that is, outputs the potential of the power supply line Vm. When at least one of the input numerical values is less than or equal to the specific value m, the output terminal Out is opened. The multi-value specific value AND / NUNDER circuit = multi-value specific value NOR / UNDER circuit outputs the specific value m when all the input numerical values are greater than or equal to the specific value m, that is, outputs the potential of the power supply line Vm. On the other hand, when at least one of the input numerical values is smaller than the specific value m, the output terminal Out is opened.

The embodiment common to the first and second inventions of FIG. 20 applies the embodiment of FIGS. 17 and 19, and the “multi-value specific value NAND · OVER circuit = multi-value specific value OR / NOVER circuit ”or“ multi-value specific value NAND / NUNDER circuit = multi-value specific value OR / UNDER circuit ”.
Therefore, if the input threshold potential is higher than the positive threshold potential of the specific value m and lower than the negative threshold potential of the numerical value (m + 1), the embodiment of FIG. OVER circuit = multi-value specific value OR / NOVER circuit On the other hand, if the input threshold potential is higher than the positive threshold potential of the numerical value (m-1) and lower than the negative threshold potential of the specific value m, the embodiment of FIG. Specific value NAND · NUNDER circuit = multi-value specific value OR · UNDER circuit.
As a result, in the multi-value specific value NAND / OVER circuit = multi-value specific value OR / NOVER circuit, the output terminal Out is opened when all the input numerical values are larger than the specific value m, while at least one of the input numerical values is greater than the specific value m. When smaller or equal, the specific value m is output, that is, the potential of the power supply line Vm is output. Further, in the multi-value specific value NAND / NUNDER circuit = multi-value specific value OR / UNDER circuit, when all the input numerical values are greater than or equal to the specific value m, the output terminal Out is opened, while at least one of the input numerical values is the specific value m. When the value is smaller, the specific value m is output, that is, the potential of the power supply line Vm is output.

The embodiment common to the first and second inventions of FIG. 21 is an application of the embodiment of FIG. 16, and the “multi-value specific value AND UNDER circuit named by the present inventor according to the height of the input threshold potential”. = Multi-value specific value NOR / NUNDER circuit "or" Multi-value specific value AND / NOVER circuit = Multi-value specific value NOR / OVER circuit ".
Therefore, if the input threshold potential is lower than the negative threshold potential of the specific value m and higher than the positive threshold potential of the numerical value (m−1), the embodiment of FIG. Value AND · UNDER circuit = multi-value specific value NOR · NUNDER circuit. On the other hand, if the input threshold potential is lower than the negative threshold potential of the numerical value (m + 1) and higher than the positive threshold potential of the specific value m, the embodiment of FIG. AND / NOVER circuit = multi-value specific value NOR / OVER circuit.
As a result, the multi-value specific value AND / UNDER circuit = multi-value specific value NOR / NUNDER circuit outputs the specific value m when all the input numerical values are smaller than the specific value m, that is, outputs the potential of the power supply line Vm. When at least one of the input numerical values is greater than or equal to the specific value m, the output terminal Out is opened. The multi-value specific value AND / NOVER circuit = multi-value specific value NOR / OVER circuit outputs the specific value m when all the input numerical values are smaller than or equal to the specific value m, that is, outputs the potential of the power supply line Vm. On the other hand, when at least one of the input numerical values is larger than the specific value m, the output terminal Out is opened.

The embodiment common to the first and second inventions of FIG. 22 applies the embodiment of FIGS. 16 and 21, and the “multi-value specific value NAND · UNDER circuit = multi-value specific value OR / NUNDER circuit ”or“ multi-value specific value NAND / NOVER circuit = multi-value specific value OR / OVER circuit ”.
Therefore, if the input threshold potential is lower than the negative threshold potential of the specific value m and higher than the positive threshold potential of the numerical value (m−1), the embodiment of FIG. Value NAND · UNDER circuit = multi-value specific value OR · NUNDER circuit. On the other hand, if the input threshold potential is lower than the negative threshold potential of the numerical value (m + 1) and higher than the positive threshold potential of the specific value m, the embodiment of FIG. NAND / NOVER circuit = multi-value specific value OR / OVER circuit.
As a result, the multi-value specific value NAND · UNDER circuit = multi-value specific value OR · NUNDER circuit opens the output terminal Out when all the input numerical values are smaller than the specific value m, while at least one of the input numerical values is higher than the specific value m. When larger or equal, the specific value m is output, that is, the potential of the power supply line Vm is output. In the multi-value specific value NAND / NOVER circuit = multi-value specific value OR / OVER circuit, the output terminal Out is opened when all the input numerical values are smaller than or equal to the specific value m, while at least one of the input numerical values is the specific value m. When the value is larger, the specific value m is output, that is, the potential of the power supply line Vm is output.

The embodiment common to the first and second inventions of FIG. 23 is an application of the embodiment of FIG. 15, and the “multi-value specific value OR / OVER circuit named by the present inventor is named according to the height of the input threshold potential. = Multi-value specific value NAND / NOVER circuit "or" Multi-value specific value OR / NUNDER circuit = Multi-value specific value NAND / UNDER circuit ".
Therefore, if the input threshold potential is lower than the negative threshold potential of the numerical value (m + 1) and higher than the positive threshold potential of the specific value m, the embodiment of FIG. OVER circuit = multi-value specific value NAND / NOVER circuit On the other hand, if the input threshold potential is lower than the negative threshold potential of the specific value m and higher than the positive threshold potential of the numerical value (m−1), the embodiment of FIG. Specific value OR · NUNDER circuit = multi-value specific value NAND · UNDER circuit.
As a result, the multi-value specific value OR / OVER circuit = multi-value specific value NAND / NOVER circuit outputs the specific value m when at least one of the input numerical values is larger than the specific value m, that is, outputs the potential of the power supply line Vm. On the other hand, when all the input numerical values are smaller than or equal to the specific value m, the output terminal Out is opened. Further, the multi-value specific value OR · NUNDER circuit = multi-value specific value NAND · UNDER circuit outputs the specific value m when at least one of the input numerical values is greater than or equal to the specific value m, that is, the potential of the power line Vm On the other hand, when all the input numerical values are smaller than the specific value m, the output terminal Out is opened.

The embodiment common to the first and second inventions of FIG. 24 is an application of the embodiment of FIGS. 15 and 23. The multi-value specific value NOR. OVER circuit = multi-value specific value AND / NOVER circuit ”or“ multi-value specific value NOR / NUNDER circuit = multi-value specific value AND / UNDER circuit ”.
Therefore, if the input threshold potential is lower than the negative threshold potential of the numerical value (m + 1) and higher than the positive threshold potential of the specific value m, the embodiment of FIG. OVER circuit = multi-value specific value AND / NOVER circuit On the other hand, if the input threshold potential is lower than the negative threshold potential of the specific value m and higher than the positive threshold potential of the numerical value (m−1), the embodiment of FIG. Specific value NOR / NUNDER circuit = multi-value specific value AND / UNDER circuit.
As a result, the multi-value specific value NOR / OVER circuit = multi-value specific value AND / NOVER circuit opens the output terminal Out when at least one of the input numerical values is larger than the specific value m, while all the input numerical values are smaller than the specific value m. When they are equal, the specific value m is output, that is, the potential of the power supply line Vm is output. Further, in the multi-value specific value NOR / NUNDER circuit = multi-value specific value AND / UNDER circuit, the output terminal Out is opened when at least one of the input numerical values is greater than or equal to the specific value m, while all the input numerical values are the specific value m. When the value is smaller, the specific value m is output, that is, the potential of the power supply line Vm is output.

The embodiment common to the first and second inventions of FIG. 25 is an application of the embodiment of FIG. 16, and the “multi-value specific value OR · UNDER circuit” named by the present inventor according to the height of the input threshold potential. = Multi-value specific value NAND / NUNDER circuit "or" Multi-value specific value OR / NOVER circuit = Multi-value specific value NAND / OVER circuit ".
Therefore, if the input threshold potential is higher than the positive threshold potential of the numerical value (m−1) and lower than the negative threshold potential of the specific value m, the embodiment of FIG. Value OR · UNDER circuit = multi-value specific value NAND · NUNDER circuit. On the other hand, if the input threshold potential is higher than the positive threshold potential of the specific value m and lower than the negative threshold potential of the numerical value (m + 1), the embodiment of FIG. OR / NOVER circuit = multi-value specific value NAND / OVER circuit.
As a result, the multi-value specific value OR / UNDER circuit = multi-value specific value NAND / NUNDER circuit outputs the specific value m when at least one of the input numerical values is smaller than the specific value m, that is, outputs the potential of the power supply line Vm. On the other hand, when all the input numerical values are greater than or equal to the specific value m, the output terminal Out is opened. The multi-value specific value OR / NOVER circuit = multi-value specific value NAND / OVER circuit outputs the specific value m when at least one of the input numerical values is less than or equal to the specific value m, that is, the potential of the power supply line Vm. On the other hand, when all the input numerical values are larger than the specific value m, the output terminal Out is opened.

The embodiment common to the first and second inventions of FIG. 26 is an application of the embodiment of FIGS. 18 and 25, and the “multi-value specific value NOR” named by the present inventor according to the height of the input threshold potential. “Under circuit = multi-value specific value AND / NUNDER circuit” or “multi-value specific value NOR / NOVER circuit = multi-value specific value AND / OVER circuit”.
Therefore, if the input threshold potential is higher than the positive threshold potential of the numerical value (m−1) and lower than the negative threshold potential of the specific value m, the embodiment of FIG. Value NOR · UNDER circuit = multi-value specific value AND · NUNDER circuit. On the other hand, if the input threshold potential is higher than the positive threshold potential of the specific value m and lower than the negative threshold potential of the numerical value (m + 1), the embodiment of FIG. NOR / NOVER circuit = multi-value specific value AND / OVER circuit.
As a result, in the multi-value specific value NOR / UNDER circuit = multi-value specific value AND / NUNDER circuit, when at least one of the input numerical values is smaller than the specific value m, the output terminal Out is opened, while all the input numerical values are from the specific value m. When larger or equal, the specific value m is output, that is, the potential of the power supply line Vm is output. In the multi-value specific value NOR / NOVER circuit = multi-value specific value AND / OVER circuit, when at least one of the input numerical values is smaller than or equal to the specific value m, the output terminal Out is opened, while all the input numerical values are the specific value m. When the value is larger, the specific value m is output, that is, the potential of the power supply line Vm is output.

In the embodiment common to the first and second inventions of FIG. 27 named by the present inventor as “multi-value specific value NAND / OVER-OR-NAND / UNDER circuit”, all the potentials of the input terminals In1, In2, and In3 are expressed as “ The output terminal Out is opened when it is higher than “a positive threshold potential with reference to the potential of the power supply line Vm” or lower than “a negative threshold potential with reference to the potential of the power supply line Vm”. On the other hand, when the potentials of the input terminals In1, In2, and In3 are not, that is, all the input potentials are not higher than the positive threshold potential, and all the input potentials are lower than the negative threshold potential. When not low, the output terminal Out outputs the potential of the power supply line Vm. The method for determining the on / off threshold voltages of the transistors 1a to 1c and 2a to 2c is the same as in the embodiment of FIG.
Thus, with respect to its logic operation, the embodiment of FIG. 27 releases its output when all three input values are greater than or less than a specified value m, and outputs the specified value m otherwise.

The embodiment common to the first and second inventions of FIG. 28 named by the present inventor as "multi-value specific value AND / OVER-OR-AND / UNDER circuit" is an application of the embodiment of FIG. Each input positive side threshold potential is lower than “the negative side threshold potential of the power supply line V (m + 1) for judging the numerical value (m + 1)”, and “the positive side threshold potential of the power supply line Vm for judging the specific value m”. Higher than "potential". Each input minus-side threshold potential is higher than “the plus-side threshold potential of the power supply line V (m−1) for determining the numerical value (m−1)”, and “the power supply line Vm for determining the specific value m”. Lower than the negative threshold potential.
With respect to the logical operation, the embodiment of FIG. 28 outputs a specific value m when all three input numerical values are larger or smaller than the specific value m, and otherwise releases the output.

  The embodiment common to the first and second inventions of FIG. 29 named by the present inventor as "multi-value specific value NAND / OVER-OR-NAND / UNDER circuit" is a power supply of a binary inverter circuit in the embodiment of FIG. The complementary outputs of the embodiment of FIG. 28 are output one by one above and below the line Vm. Therefore, the conditions of each input threshold potential are the same as in the embodiment of FIG. 28, and the logic operation is the same as in the embodiment of FIG.

  The embodiment common to the first and second inventions of FIG. 30 named by the present inventor as "multi-value specific value NAND / OVER-OR-NAND / UNDER circuit" is completely C / MOS implementation of the embodiment of FIG. Thus, the P- and N-channel normally-on type MOS FETs are used as resistance means. Similarly, the embodiment of FIG. 28 can also be completely C.MOS.

  The embodiment 31 common to the first and second inventions of FIG. 31 named by the inventor as "multi-value specific value determination circuit" is composed of bipolar transistors, and the logical operation thereof is the same as that of the embodiment of FIG. .

  The embodiment 32 common to the first and second inventions of FIG. 32 named by the inventor as "multi-value specific value determination circuit" is composed of bipolar transistors, and the logical operation thereof is the same as that of the embodiment of FIG. .

  The embodiment 33 common to the first and second inventions of FIG. 33 named by the inventor as “multi-value specific value determination circuit” is composed of bipolar transistors, and the logical operation thereof is the same as that of the embodiment of FIG. .

  The common embodiment 34 of FIG. 34 named by the present inventor as a “multi-value specific value determination circuit” has a C / MOS configuration. Each series circuit of two diodes also serves as a level shift diode that adjusts the output potential (or voltage) to Vm, and the number is increased or decreased according to the adjustment.

  The common embodiment 35 of FIG. 35 named by the present inventor as a “multi-value specific value determination circuit” is the one in which the embodiment of FIG. 4 is composed of a bipolar transistor or the like.

  A simplified version of the embodiment of FIG. 36 named by the present inventor as a “multi-value specific value NOT circuit” is the embodiment of FIG.

  The embodiment of the second invention of FIG. 37 named by the present inventor as a “multi-value specific value determination circuit” is a multi-value specific value determination circuit for the highest potential power supply line V (n−1). If a binary inverter circuit is connected halfway as in the embodiment of FIG. 29, the embodiment of FIG. 37 becomes a multi-value specific value NAND circuit for the power supply line V (n-1) having the highest potential. Each diode indicated by a dotted line may or may not be present.

  The embodiment of the second invention of FIG. 38 named by the inventor as "multi-value specific value determination circuit" is a multi-value specific value determination circuit for the power supply line V0 having the lowest potential. If a binary inverter circuit is connected halfway as in the embodiment of FIG. 29, the embodiment of FIG. 38 becomes a multi-value specific value NAND circuit for the power supply line V0 having the lowest potential. Each diode indicated by a dotted line may or may not be present.

  A description will be given of an embodiment 39 that the inventor names "multi-value AND circuit". For example, “eight embodiments of FIG. 9 where n = 10 and m is 1 to 8”, “one embodiment of FIG. 37 where n = 10” and “first embodiment of FIG. 38 where n = 10”. 10 "and 10 input terminals In2, 10 input terminals In3, 10 input terminals In3 and 10 output terminals Out, respectively, and connect new input terminals In1 to In3 and output terminal Out. Is formed, a 10-value 3-input type multi-value AND circuit can be formed. In this case, if all the “numerical values corresponding to the potentials of the input terminals In1 to In3” are the same, the “potential (or voltage) corresponding to the numerical values” is output from the output terminal Out. That is, with respect to the logical operation, the embodiment 39 outputs the same numerical value when all three input numerical values are the same, and releases the output when even one is different.

  Thus, in the case of the first and second inventions, as long as “different potentials”, that is, “different values” are not output simultaneously, the output terminals and the input terminals of a plurality of multi-value logic circuits are connected to each other. Logical processing capability can be developed and strengthened. In addition, for example, inputs of “multi-value specific value NUNDER circuit of specific value (m + 1)”, “multi-value specific value determination circuit of specific value m” and “multi-value specific value NOVER circuit of specific value (m−1)” are input. If the terminals and the output terminals are connected, "output of numerical value (m + 1) if input numerical value ≥ numerical value (m + 1)", "output of numerical value m if input numerical value = numerical value m" and "input numerical value ≤ numerical value (m-1). ) Can be configured as a circuit having a logical function of “output of numerical value (m−1)”.

Finally, the following will be supplemented.
a) In each embodiment, each diode indicated by a dotted line may be present or absent.
b) In each embodiment, instead of each diode, “bipolar transistor with its collector and base directly connected”, “junction FET with its drain and source directly connected”, “bipolar mode SIT with its drain and gate directly connected” Or GTBT ”,“ normally off-type MOS FET with its gate, back gate and source connected ”or“ the back gate potential between the drain and back gate and between the source and back gate so as not to conduct. Can be used one by one, normally-off type MOS FET having its drain and gate connected.
c) In each embodiment, the level of each power supply potential is reversed, and each controllable switching means is defined as “controllable switching means in a complementary relationship (eg, P-channel MOS • FET with respect to N-channel MOS • FET). It is also possible to replace one by one and reverse the direction of each directional component (eg, diode) “an embodiment that is symmetrical with respect to voltage direction or voltage polarity relative to the original embodiment”. is there. However, in that case, the function may be the same as the original or may be different.
d) In the embodiment of FIG. 3, “bidirectional switching means connected between the power supply line Vm and the output terminal Out” is replaced with “bidirectional switching using a diode-bridge connection type rectifier circuit” in the embodiment of FIG. It has been replaced by “means”. In the embodiments of FIGS. 9 and 13 to 27, the same replacement can be made. The replacement is the same for the bidirectional switching means in the embodiment of FIG.
e) If the input threshold potential is made different for each input terminal in each of the embodiments of FIGS. 9 to 14 and 19 to 30, the multi-value logic processing function may be further developed.
f) The “multi-value specific value judging circuit” may be called “multi-value specific value EQUAL circuit” or “multi-value specific value SAME circuit”.
g) In the case of the second invention, there is no need to change the circuit configuration regardless of the number of multi-values (N of N values), and the same circuit configuration can be used for 5 values, 10 values, or 100 values. Good, flexible, flexible and responsive. You just need to change the connection of the power line to connect.
h) In the first and second inventions, a multi-valued logic output method is available in which the output is opened. Therefore, the output means (eg, output terminal etc.) is connected to the “potential supply means (eg: power line). The output voltage can be freely changed by pulling up or down to "potential supply means other than Vm" or "potential supply means other than potential supply means V0 to V (n-1)".

i) In the above-described mathematical explanation regarding the number of types of multi-valued logic processing and the explosive size of the multi-valued logic processing, it has been described conservatively in the case of 1 digit (digit) 2 input. Increased number of inputs makes it “super, super,… super, explosive”. For example, even in the case of 10 values, 1 digit, and 3 inputs, there are 10 kinds of multi-value logic processing and multi-value logic functions, which are astronomical numbers.
j) Semiconductor (substrate) multi-layer technology (= 3D IC technology) and low-voltage technology are "multi-adic logic circuit, multi-adic arithmetic circuit, multi-adic memory circuit, multi-adic computer, etc." Assists in practical use. If semiconductor multi-layer technology, low-voltage drive and withstand voltage maintenance technology, energy-saving technology, cooling technology, etc. continue to advance, 64, 100, and 128 logic circuits, arithmetic circuits, and memory circuits Or a computer or the like will be possible, and a super-super computer of 64, 100, 128, etc .... may appear.
k) By the way, the decimal computer “DC” (Decimal Computer) eliminates, prevents, or alleviates the “syndrome called“ computer over-adaptation ”caused by the current binary computer” Or it is expected to be cured. “Computer over-adaptation” makes it impossible to communicate with “others who leave ambiguous room” by identifying them with the binary thinking of computers that have only “0” or “1”. Gets worse.
Reference: p. Of the morning edition dated March 11, 2002 of the Nihon Keizai Shimbun (Tokyo edition). 34 “Musoba techno stress”.
This means that “multiple, especially decimal, is better for building human-friendly, human-friendly computers, neurocomputers or artificial intelligence”, and “multi-adic, especially 10 for fuzzy control. It suggests that the decimal system is better.
However, these things may apply to Asians, such as Japan, which has “an ambiguous expression culture”, and may not apply to Western countries, which have “a clear culture of YES, NO”. If so, “Isn't the multi-adic computer, etc. suitable for Asians such as Japan, and is a specialty? ].
l) If the number of input terminals of the embodiment 39 (refer to paragraph number 0074) named “multi-value AND circuit” by the inventor is one and the input terminal and the output terminal are connected, a 10-value memory, 10 Value storage means can be configured. Similarly, multi-value storage means having different multi-value numbers can be configured by changing the multi-value number (N of N values).
m) For example, a plurality of 10-value or more multi-value storage means are used in decimal decimal numbers, and 11-values and 12-values other than 10 values are used for plus / minus sign or parity check, etc. It is also possible to do. For this reason, a multi-value number and a multi-adic system number (N in N-adic system) do not always coincide with each other. Therefore, rather than calling a multi-value logic circuit, a multi-value computer, etc. The present inventor thinks that it is correct to call it a legal computer or the like. Actually, a binary circuit using a quaternary memory has been put into practical use.
n) Multi-adic logic circuits, multi-adic computers, etc. have higher performance and advantages than those of the binary system, even if they consume more power or have more parts. It is worth putting into practical use. The above-mentioned “human-friendly” is one of the advantages, but the amount of information that can be sent with the same number of data lines, there is no binary / decimal conversion error in decimal, and the number of carry The advantage is that there are few. There are others.
o) In terms of power loss, the power supply voltage is intuitively considered that the decimal circuit has a power loss as large as the square of the binary circuit voltage 10 times the square = 100 times. In the case of a decimal circuit, the number of power supplies required for 10 power supply potentials is 9, and the total voltage is 9 times. In addition, since each signal does not always fully swing between the lowest potential and the highest potential, statistical processing is required to calculate the power loss. In addition, do each of the power lines have their own electrostatic shielding effect and shielding effect? What happens to the effect of floating capacitance such as signal lines related to charge / discharge energy?
p) Supplementary description will be made regarding effect 3 (paragraph number 0032) of the second invention.
"A circuit in which the transistors Q1 and Q4 are removed from the conventional circuit of FIG. 39", that is, "a circuit of bidirectional switching means connected to an intermediate potential between the lowest potential and the highest potential" is shown in FIGS. Although it corresponds to each embodiment of FIG. 35, as described above (paragraph number 0017), there is a limit to how to use it and it cannot be used alone. On the other hand, each of the embodiments of FIGS. 1 to 5 and FIGS. 31 to 35 of the second invention has no such restrictions on use, and can be used freely. That is, these embodiments have a “multi-valued logic processing function that cannot be realized by a conventional circuit”.
Further, output functions of complementary outputs such as “multi-value specific value NOT circuit”, “multi-value specific value NAND circuit”, and “multi-value specific value NOR circuit” are also “multi-value logic processing functions that cannot be realized by conventional circuits”. Or, “unknown multi-value logic processing function”.
Furthermore, the same multi-value logic processing function as the “multi-value specific value OVER circuit”, “multi-value specific value UNDER circuit”, “multi-value specific value NOVER circuit”, “multi-value specific value NUNDER circuit”, etc. of the second invention is provided. There is no conventional circuit. This is especially true for circuits that output a specific potential bidirectionally.
q) In the conventional circuit of FIG. 39, the transistors Q2 and Q3 can be removed, and one of the embodiments of FIGS. 1 to 5 and 31 to 35 can be combined instead. On the other hand, in the embodiment 39 (paragraph number 0074), a circuit in which n = 3 instead of n = 10 is possible, and a multi-value specific value NAND circuit is used instead of each multi-value specific value AND circuit that is not used. An embodiment using one by one is also possible. As described above, the present invention has a high degree of freedom and response capability, and can be freely developed, strengthened or changed. This is a very useful means for dealing with “a super-explosive large multi-valued logic process and number of types of multi-valued logic functions that the inventor points out”.
r) There is a possibility that the clock frequency and the like can be lowered by the multi-value processing. This is because there is a large amount of information that can be sent and handled. Lowering the frequency reduces the number of charge / discharge cycles such as the capacitance between the gate and source of the C / MOS / FET, thereby reducing the power consumption.

各図は、本発明の各実施例を１つずつ示す回路図である。先行発明の多値論理回路の大本（おおもと）の基本回路を示す回路図である。

Each figure is a circuit diagram showing each embodiment of the present invention one by one. It is a circuit diagram which shows the basic circuit of Omoto (Omoto) of the multi-value logic circuit of prior invention.

Claims (31)

When a predetermined plural number of 3 or 3 is represented by N and a predetermined natural number is represented by S,
N potentials increasing in numerical order from the first potential to the Nth potential are supplied one by one, and each potential corresponds to each numerical value of 0 to (N-1) in a one-to-one correspondence. Each of potential supply means to Nth potential supply means;
From each of the first input means to the S-th input means for inputting signals one by one,
Output means for outputting a signal therefrom,
At least one bidirectional switching means connected between at least one of the second potential supply means to the (N-1) th potential supply means and the output means;
Logic processing means for processing based on “each numerical value corresponding to each potential of the first to S-th input means among 0 to (N−1)” and “predetermined multi-value logic”;
ON / OFF drive means controlled by the logic processing means to drive ON / OFF of each of the “at least one bidirectional switching means”;
In a multi-value logic circuit having
Each of the “at least one bidirectional switching means” has one “bidirectional switching means that is turned off bidirectionally between the switch terminal on the output means side and the switch drive section when driven off”. A multi-valued logic circuit characterized by using each one. When a predetermined plural number of 3 or 3 is represented by N and a predetermined natural number is represented by S,
N potentials increasing in numerical order from the first potential to the Nth potential are supplied one by one, and each potential corresponds to each numerical value of 0 to (N−1) in a one-to-one correspondence. Each of potential supply means to Nth potential supply means;
From each of the first input means to the S-th input means for inputting signals one by one,
Output means for outputting a signal therefrom;
One of the first to Nth potential supply means is connected between the potential supply means having a specific potential and the output means, and when on, the potential of the output means is pulled up or down to the specific potential. Output potential pulling means for opening the output means when off;
“Each numerical value corresponding to each potential of the first to S-th input means among 0 to (N−1)” based on “a positive or negative threshold potential determined in advance with respect to the specific potential” And a numerical value relationship detecting means for detecting a magnitude relationship between “a numerical value corresponding to the specific potential” or a relationship between equality and inequality;
Logic processing means for processing based on the “detection result of the numerical relationship detection means” and “predetermined multi-value logic”;
An on / off drive means controlled by the logic processing means to drive the output potential pull means on and off;
A multi-value specific value logic circuit comprising: 3. The multi-value specific value logic circuit according to claim 2, wherein said S is 1 and said numerical relation detecting means detects said "relation between equality and unequal", and said ON / OFF driving means outputs said output when they are equal. A multi-value specific value determination circuit, wherein the potential pull means is turned on and is turned off when they are not equal. 4. A multi-value specific value NOT circuit according to claim 3, wherein the on / off drive of the on / off drive means is opposite. 3. The multi-value specific value logic circuit according to claim 2, wherein said S is plural, and said numerical relation detecting means detects said "relation between equality or not equal", and when all are equal, said on / off driving means A multi-value specific value AND circuit characterized in that the output potential pulling means is driven on, and otherwise off. 6. The multi-value specific value AND circuit according to claim 5, wherein the on / off drive of the on / off drive means is opposite. There are N multi-value specific value AND circuits according to claim 5, wherein each of the specific potentials is one potential from the first potential to the Nth potential.
Connect all the output means as new output means,
A multi-value AND circuit characterized in that, when S new input means are formed, one input means of each multi-value specific value AND circuit is connected to each new input means. 3. The multi-value specific value logic circuit according to claim 2, wherein said S is plural and said numerical relationship detecting means detects said "relation between equality or not equal", and said on / off drive means when at least one is equal The multi-value specific value OR circuit is characterized in that the output potential pull means is turned on, and is otherwise driven off. 9. A multi-value specific value NOR circuit according to claim 8, wherein the on / off drive of the on / off drive means is opposite. 3. The multi-value specific value logic circuit according to claim 2, wherein said S is 1, said numerical relationship detecting means detects said magnitude relationship, and said on / off is detected when said input potential value is greater than said specific potential value. A multi-value specific value OVER circuit, characterized in that the driving means drives the output potential pulling means on, and otherwise turns it off. 11. The multi-value specific value OVER circuit according to claim 10, wherein the on / off drive of the on / off drive means is opposite. 3. The multi-value specific value logic circuit according to claim 2, wherein when the S is plural and the numerical value relation detecting means detects the magnitude relation, and all of the numerical values of the input potential are larger than the numerical value of the specific potential, A multi-value specific value AND / OVER circuit characterized in that an off driving means drives the output potential pulling means on and off otherwise. 13. A multi-value specific value NAND / OVER circuit according to claim 12, wherein the on / off drive of the on / off drive means is opposite to the other. 3. The multi-value specific value logic circuit according to claim 2, wherein said S is plural, said numerical relationship detecting means detects said magnitude relationship, and at least one of the input potential values is greater than said specific potential value. The multi-value specific value OR / OVER circuit characterized in that the on / off driving means drives the output potential pulling means on, and otherwise turns it off. 15. The multi-value specific value NOR / OVER circuit according to claim 14, wherein the on / off drive of the on / off drive means is opposite. 3. The multi-value specific value logic circuit according to claim 2, wherein said S is 1, said numerical relationship detecting means detects said magnitude relationship, and said on / off is detected when said input potential value is smaller than said specific potential value. A multi-value specific value UNDER circuit characterized in that the drive means drives the output potential pull means on, and otherwise turns it off. 17. The multi-value specific value UNDER circuit according to claim 16, wherein the on / off drive of the on / off drive means is opposite to that of the multi-value specific value UNDER circuit. 3. The multi-value specific value logic circuit according to claim 2, wherein when the S is plural and the numerical value relation detecting means detects the magnitude relation, and all of the numerical values of the input potential are smaller than the numerical value of the specific potential, A multi-value specific value AND / UNDER circuit characterized in that an off driving means drives the output potential pulling means on, and otherwise turns off. 19. The multi-value specific value AND • UNDER circuit according to claim 18, wherein the on / off drive of the on / off drive means is opposite. 3. The multi-value specific value logic circuit according to claim 2, wherein there are a plurality of S, the numerical value relation detecting means detects the magnitude relation, and at least one of the numerical values of the input potential is smaller than the numerical value of the specific potential. The multi-value specific value OR / UNDER circuit is characterized in that the on / off driving means drives the output potential pulling means on, and otherwise turns off the output potential pulling means. 21. The multi-value specific value NOR / UNDER circuit according to claim 20, wherein the on / off drive of the on / off drive means is opposite. 3. The multi-value specific value logic circuit according to claim 2, wherein said S is plural, and said numerical value relationship detecting means detects said magnitude relationship, and when all of the numerical values of the input potential are greater than or equal to the numerical value of said specific potential. A multi-value specific value AND NUNDER circuit characterized in that the on / off driving means drives the output potential pulling means on, and otherwise turns it off. 23. The multi-value specific value NAND / NUNDER circuit according to claim 22, wherein the on / off drive of the on / off drive means is opposite to that of the multi-value specific value NAND / NUNDER circuit. 3. The multi-value specific value logic circuit according to claim 2, wherein said S is plural, said numerical value relation detecting means detects said magnitude relation, and at least one of the numerical values of the input potential is greater than the numerical value of said specific potential. The multi-value specific value OR · NUNDER circuit is characterized in that the on / off driving means drives the output potential pulling means on when they are equal and off when not. 25. The multi-value specific value NOR / NUNDER circuit according to claim 24, wherein the on / off drive of the on / off drive means is opposite to that of the multi-value specific value NOR / NUNDER circuit. 3. The multi-value specific value logic circuit according to claim 2, wherein there are a plurality of S, and the numerical value relationship detecting means detects the magnitude relationship, and when all of the numerical values of the input potential are smaller than or equal to the numerical value of the specific potential, A multi-value specific value AND / NOVER circuit characterized in that the on / off driving means drives the output potential pulling means on, and otherwise turns it off. 27. The multi-value specific value NAND / NOVER circuit according to claim 26, wherein the on / off drive of the on / off drive means is opposite. 3. The multi-value specific value logic circuit according to claim 2, wherein said S is plural, said numerical value relation detecting means detects said magnitude relation, and at least one of the numerical values of said input potential is smaller than said specific potential value. The multi-value specific value OR / NOVER circuit is characterized in that the ON / OFF driving means drives the output potential pulling means ON when they are equal, and OFF when not. 29. The multi-value specific value NOR / NOVER circuit according to claim 28, wherein the on / off drive of the on / off drive means is opposite. 3. The multi-value specific value logic circuit according to claim 2, wherein the S is plural, and the numerical value relation detecting means detects the magnitude relation, and “when all of the numerical values of the input potential are larger than the numerical value of the specific potential” or “When all the values of the input potential are smaller than the value of the specific potential” The multi-value specific value AND characterized in that the on / off drive means drives the output potential pull means on, and otherwise turns off. • OVER-OR-AND and UNDER circuit. 31. The multi-value specific value NAND.OVER-OR-OR circuit according to claim 30, wherein the on-off drive of the on / off drive means is opposite. -NAND / UNDER circuit.

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