JP2004088763A

JP2004088763A - Multistable circuit

Info

Publication number: JP2004088763A
Application number: JP2003203347A
Authority: JP
Inventors: Toshiyasu Suzuki; 鈴木　利康
Original assignee: Individual
Current assignee: Individual
Priority date: 2002-06-24
Filing date: 2003-06-24
Publication date: 2004-03-18

Abstract

<P>PROBLEM TO BE SOLVED: To provide a multistable circuit which is constituted with a small number of parts and from normally-off switching means, and which a power source short circuit current is little when powered up. <P>SOLUTION: As shown in the figure, for example, an on-state is held by itself between a power source lines v0 and v1, and between the power source lines v1 and v2, respectively. A pull down means of a self-retention type switch capable of off-driving and pulling down a potential of an input/output terminal Tio is established one by one. The on-state is held by itself between the power source lines v2 and v3, and between power source lines v3 and v4, respectively. A pull up means of a self-retention type switch capable of off-driving and pulling up the potential of the input/output terminal Tio is established one by one. Each of the above-mentioned pull down means between the power source lines v1 and v2, and the above-mentioned pull up means between the power source lines v3 and v4, is a multistable circuit of 4 values without capability for clamping the potential of input/output terminal Tio in the reverse direction. The above-mentioned target can be attained by the circuit just mentioned. Diodes 3a and 3d may be eliminated. <P>COPYRIGHT: (C)2004,JPO

Description

【０００１】
【技　術　分　野】
本発明は、その安定状態の数が３又は３以上で、その安定状態に応じた電圧もしくは電位を保持または出力できる多安定回路に関する。この多安定回路は多値のメモリー・セル、多値メモリー又は多値記憶手段として利用でき、さらに多値（又は多進法）論理回路、多値（又は多進法）演算回路、多値コンピュータ（特に４、８、『１０』、１６、３２、６４、１００、１２８進法コンピュータ）又は多値（又は多進法）制御手段の構成要素として利用できる。
【０００２】
【背　景　技　術】
特許第２８５３０４１号公報に開示された多安定回路には『部品点数が多い』という問題点が有る。また、特開２０００−８３３６９号公報の図２７〜図３６と特願２００１−３２９７２号公報の図１０〜図１４に開示された多安定回路には『ノーマリィ・オン型スイッチング手段しか使うことができず、しかも、電源投入時に電源電圧が立ち上がってそれらノーマリィ・オン型スイッチング手段に充分なゲート逆バイアス電圧を印加できるまで電源短絡電流が流れてしまう』という問題点が有る。ノーマリィ・オフ型で多安定回路を構成できれば、構成手段の選択肢が増えて便利である。また、この電源短絡電流の問題は例えば『その多安定回路を多値のメモリー・セルとして多数使って多値メモリー手段を構成する場合、電源投入時に極めて大きな電源短絡電流が流れ、電源電圧を立ち上げることができず、使い物にならない』という問題点に結び付く。
【０００３】
そこで、本発明は『部品点数が少なく、ノーマリィ・オフ型スイッチング手段を使うことができて、電源投入時の電源短絡電流を少なくできる』多安定回路を提供することを目的としている。　　　　　　　　（　発　明　の　目　的　）
【０００４】
【発　明　の　開　示】
即ち、本発明は請求項１に記載した通りの多安定回路である。但し、その所定の前記電位供給線手段は第２電位供給線手段から第Ｎ電位供給線手段までのいずれか１つに該当するため、前記プル・アップ手段が１つしかない場合も有るし、あるいは、前記プル・ダウン手段が１つしかない場合も有るので、前記の「それぞれのプル・アップ手段」には１つの場合も含まれ、前記の「それぞれのプル・ダウン手段」には１つの場合も含まれる。ノーマリィ・オフ型スイッチング手段で構成した自己保持型スイッチング手段をプル・アップ手段やプル・ダウン手段として用いているので、本発明の多安定回路には『部品点数が少なく、ノーマリィ・オフ型スイッチング手段を使うことができて、電源投入時の電源短絡電流を少なくできる』という効果が有る。　　　　　　　（　発　明　の　効　果　）
【０００５】
【発明を実施するための最良の形態】
本発明をより詳細に説明する為に以下添付図面に従ってこれを説明する。図１に示す実施例は４安定または４値の多安定回路で、この実施例では前述したＮは４で、次の通り各構成要素が前述した請求項１記載中の各構成手段に相当する。
ａ）電源線Ｖ０〜Ｖ４が前述した第１電位供給線手段〜第（Ｎ＋１）電位供給線
手段に。
ｂ）入出力端子Ｔｉｏが前述した入出力端子に。
ｃ）電源線Ｖ２が前述した所定の前記電位供給線手段に。
ｄ）「電源線Ｖ２、Ｖ３間に接続されたトランジスタ１ｃ、２ｃ、ダイオード３ｃ及び抵抗４ｃ〜６ｃの接続体」と「電源線Ｖ３、Ｖ４間に接続されたトランジスタ１ｄ、２ｄ（、ダイオード３ｄ）及び抵抗４ｄ〜６ｄの接続体」それぞ
れが前述したプル・アップ手段に。
ｅ）「電源線Ｖ０、Ｖ１間に接続されたトランジスタ１ａ、２ａ（、ダイオード３ａ）及び抵抗４ａ〜６ａの接続体」と「電源線Ｖ１、Ｖ２間に接続されたトランジスタ１ｂ、２ｂ、ダイオード３ｂ及び抵抗４ｂ〜６ｂの接続体」それぞ
れが前述したプル・ダウン手段に。
【０００６】
「トランジスタ１ａ、２ａ（、ダイオード３ａ）及び抵抗４ａ〜６ａが構成する自己保持型スイッチング手段」は自分でオン状態を保持する機能を持ち、トランジスタ１ａ、２ａは互いに相手をオン駆動できるが、入出力端子Ｔｉｏの電位が「電源線Ｖ１の電位からトランジスタ１ａのオン・オフしきい値電圧を引いた電位」より高くなると、その自己保持型スイッチング手段はターン・オフする。同様に「トランジスタ１ｂ、２ｂ、ダイオード３ｂ及び抵抗４ｂ〜６ｂが構成する自己保持型スイッチング手段」も自分でオン状態を保持する機能を持ち、トランジスタ１ｂ、２ｂは互いに相手をオン駆動できるが、入出力端子Ｔｉｏの電位が「電源線Ｖ２の電位からトランジスタ１ｂのオン・オフしきい値電圧を引いた電位」より高くなると、その自己保持型スイッチング手段はターン・オフする。
【０００７】
「トランジスタ１ｄ、２ｄ（、ダイオード３ｄ）及び抵抗４ｄ〜６ｄが構成する自己保持型スイッチング手段」は自分でオン状態を保持する機能を持ち、トランジスタ１ｄ、２ｄは互いに相手をオン駆動できるが、入出力端子Ｔｉｏの電位が「電源線Ｖ３の電位にトランジスタ２ｄのオン・オフしきい値電圧を加算した電位」より低くなると、その自己保持型スイッチング手段はターン・オフする。同様に「トランジスタ１ｃ、２ｃ、ダイオード３ｃ及び抵抗４ｃ〜６ｃが構成する自己保持型スイッチング手段」も自分でオン状態を保持する機能を持ち、トランジスタ１ｃ、２ｃは互いに相手をオン駆動できるが、入出力端子Ｔｉｏの電位が「電源線Ｖ２の電位にトランジスタ２ｃのオン・オフしきい値電圧を加算した電位」より低くなると、その自己保持型スイッチング手段はターン・オフする。
【０００８】
尚、入出力端子Ｔｉｏの電位が常に電源線Ｖ０の電位と電源線Ｖ４の電位の間にあれば、ダイオード３ａ、３ｄは有っても無くても構わない。また、図１の実施例ではトランジスタ２ａ、２ｂ、１ｃ、１ｄのいずれか１つがオンである安定状態にあるので、トランジスタ１ｂのエミッタ接合（エミッタ・ベース間ＰＮ接合）と抵抗６ｂの直列回路は弱いながらも一応プル・アップ能力を持つが、入出力端子Ｔｉｏの電位を電源線Ｖ２の電位にクランプすることはできない。つまり、「トランジスタ１ｂ、２ｂ、ダイオード３ｂ及び抵抗４ｂ〜６ｂが構成する自己保持型スイッチング手段」は逆方向に関して入出力端子Ｔｉｏの電位をクランプする能力を持っていない。加えて抵抗６ｂの一端をダイオード３ｂのアノードからカソードに接続し直せば、この自己保持型スイッチング手段は逆阻止型になるので、その不要な弱いプル・アップ能力を完全に取り除くことができる。同様に、抵抗６ｃとトランジスタ２ｃのエミッタ接合の直列回路は弱いながらも一応プル・ダウン能力を持つが、入出力端子Ｔｉｏの電位を電源線Ｖ２の電位にクランプすることはできない。つまり、「トランジスタ１ｃ、２ｃ、ダイオード３ｃ及び抵抗４ｃ〜６ｃが構成する自己保持型スイッチング手段」は逆方向に関し入出力端子Ｔｉｏの電位をクランプする能力を持っていない。加えて抵抗６ｃの一端をダイオード３ｃのカソードからアノードに接続し直せば、その自己保持型スイッチング手段は逆阻止型になるので、その不要な弱いプル・ダウン能力を完全に取り除くことができる。
【０００９】
それから、その安定状態を切り換えるには、すなわち、その記憶内容を書き換えるには「入出力端子Ｔｉｏを電源線Ｖ３又はＶ４の電位にプル・アップ又は電源線Ｖ０又はＶ１の電位にプル・ダウンするか」、「トランジスタ２ａ、２ｂ、１ｃ、１ｄのいずれか１つにパルス・オン駆動信号を与えるか、あるいは、その４トランジスタのいずれか３つにパルス・オフ駆動信号を与えるか」又は「トランジスタ１ａ、１ｂ、２ｃ、２ｄのいずれか１つにパルス・オン駆動信号を与えるか、あるいは、その４トランジスタのいずれか３つにパルス・オフ駆動信号を与えるか」すれば良い。その記憶内容を読み出す時は例えば入出力端子Ｔｉｏを「その記憶内容に影響を与えない大きさのプル抵抗を電源線ｖ２との間に接続したデータ線」に接続すれば良い。そして、トランジスタ１ａ〜１ｄ、２ａ〜２ｄそれぞれの代わりに「その駆動信号入力用に対を成す制御端子と主端子の間の逆バイアス電圧極性がそれと同じノーマリィ・オフ型スイッチング手段」ならば何でも使用できる。例えばバイポーラ・モードのＳＩＴ、ＭＯＳ・ＦＥＴ、ＩＧＢＴ、ＧＴＢＴ（接地した溝形電極を持つバイポーラ型ＦＥＴ）、ノーマリィ・オフ型ＳＩサイリスタ、ＧＴＯサイリスタ等が有る。各ダイオードの代わりに「そのコレクタとベースを接続したバイポーラ・トランジスタ」を使っても良い。電源線ｖ２、ｖ１間の各構成手段と直流電源を取り外し、電源線ｖ２、ｖ１を直結すれば図１の実施例は３安定もしくは３値の多安定回路になる。電源線ｖ３、ｖ２間についても同様にすれば図１の実施例は３値の多安定回路になる。電源線ｖ３、ｖ１間の各構成手段と各直流電源を取り外し、電源線ｖ３、ｖ１を直結すれば図１の実施例は双安定回路になる。ところで、図１の実施例においてトランジスタ２ｃのエミッタを電源線Ｖ２から電源線Ｖ１へ接続し直し、トランジスタ１ｂのエミッタを電源線Ｖ２から電源線Ｖ３へ接続し直した回路も可能である。
【００１０】
図２の実施例は６安定または６値の多安定回路で、電源線ｖ３が前述した所定の電位供給線手段である。図３の実施例は１０値の多安定回路で、電源線ｖ５が前述した所定の電位供給線手段で、接続端子ｃｔ１、ｃｔ２に関して同じ符号同士が接続状態にある。なお、図３の実施例において電源線Ｖ５に接続したＰ・ＭＯＳとＮ・ＭＯＳを取り外し、電源線Ｖ６に接続したＰ・ＭＯＳ（図左側）のドレインと電源線Ｖ４に接続したＮ・ＭＯＳ（図左側）のドレインを接続した実施例も可能である。図４、図５の各実施例は７値の多安定回路である。図４の実施例では電源線ｖ４が前述した所定の電位供給線手段で、図５の実施例では電源線ｖ３が前述した所定の電位供給線手段である。図６の実施例は１２値の多安定回路で、電源線ｖ６が前述した所定の電位供給線手段で、接続端子ｃｔ３、ｃｔ４に関して同じ符号同士が接続状態にある。これら実施例についても上述の様にして各電源線を直結すれば、その多値数が異なる多安定回路をいくつも構成したり、双安定回路を構成したりできる。図２、図３、図６の各実施例において「そのドレインがダイオードを介して入出力端子Ｔｉｏに接続されるＭＯＳ・ＦＥＴ」それぞれを逆阻止型ＩＧＢＴで１つずつ置き換えた実施例では逆阻止用の各ダイオードは不要である。逆阻止型の可制御スイッチング手段を使えば同様に逆阻止用の各ダイオードは不要である。各実施例において各ダイオードの代わりに「そのコレクタとベースを直結したバイポーラ・トランジスタ」、「そのコレクタとエミッタを直結したバイポーラ・トランジスタ」、「そのドレインとソースを直結した接合型ＦＥＴ」、「そのドレインとゲートを直結したバイポーラ・モードのＳＩＴ又はＧＴＢＴ」、「そのゲート、ソース及びバックゲートを接続したＭＯＳ・ＦＥＴ」、「そのドレインとソースを接続し、そのゲートとバックゲートを接続したＭＯＳ・ＦＥＴ」又は「そのドレイン・バックゲート間、そのソース・バックゲート間それぞれが導通しない様にそのバックゲート電位を保ち、そのドレインとゲートを接続したＭＯＳ・ＦＥＴ」を１つずつ使用できる。
【００１１】
各実施例において各電源線の高低を正反対にして、各可制御スイッチング手段を「それと相補関係に有る可制御スイッチング手段（例：Ｎチャネル型ＭＯＳ・ＦＥＴに対するＰチャネル型ＭＯＳ・ＦＥＴ）で１つずつ置換え、方向性の有る各構成要素（例：ダイオード）の向きを逆にした「元の実施例に対して電圧方向または電圧極性に関して対称的な関係に有る実施例」もまた可能である。但し、その場合、その機能が元と同じ場合も有るし、違う場合も有る。それから、図４、図５の両実施例は、各前段のベース抵抗の接続位置の違いを除けば、互いに前記の様な対称的な関係に有る。例えば１０値以上の多安定回路の複数個を１０進法の多数桁で使用し、１０値以外をプラス、マイナスの符号あるいはパリティ・チェック等に使用することも可能である。点線で示したダイオードの意味は「有っても無くても良い」という意味である。便宜上、入出力端子と呼んだが、実際には端子として存在せず、単なる導線や電極である場合が多い。
【００１２】
半導体の（基板）多層化技術（３次元化ＩＣ技術）や低電圧化技術は「本発明を利用する多進法コンピュータなど」の実用化を強力にアシストする。もし、半導体の（基板）多層化技術（３次元化ＩＣ技術）、低電圧化技術、耐（電）圧化技術、省エネルギー技術、冷却技術などがどんどん進歩すれば、６４進法、１００進法、１２８進法の論理回路、演算回路もしくはコンピュータ等も可能になり、６４進法、１００進法、１２８進法の超ウルトラ・スーパー・コンピュータが出現するかもしれない。又、１０進法コンピュータ『ＤＣ』（Ｄｅｃｉｍａｌ　Ｃｏｍｐｕｔｅｒ）が「現在の２進法コンピュータが引き起こす『コンピュータ過剰適応症』と呼ばれる症候群」を無くしたり、予防したり、緩和（かんわ）したり、あるいは治（なお）したり、することが期待される。『コンピュータ過剰適応症』では「０」か「１」しかないコンピュータの２進法的な思考に同一化して、「曖昧な余地を残す他者」とのコミュニケーションができなくなり、人間関係が悪化する。（参考：日本経済新聞の２００２年３月１１日付け朝刊Ｐ．３４『心蝕むテクノストレス』）
【図面の簡単な説明】
【図１〜図６】各図は、本発明の実施例を１つずつ示す回路図である。[0001]
【Technical field】
The present invention relates to a multistable circuit having three or more stable states and capable of holding or outputting a voltage or potential corresponding to the stable state. The multi-stable circuit can be used as a multi-valued memory cell, a multi-valued memory or a multi-valued storage means, and furthermore, a multi-valued (or multi-valued) logic circuit, a multi-valued (or multi-valued) arithmetic circuit, a multi-valued computer (Especially 4, 8, "10", 16, 32, 64, 100, 128-ary computer) or as a component of multi-level (or multi-level) control means.
[0002]
[Background technology]
The multistable circuit disclosed in Japanese Patent No. 2853041 has a problem that "the number of components is large". The multistable circuits disclosed in FIGS. 27 to 36 of Japanese Patent Application Laid-Open No. 2000-83369 and FIGS. 10 to 14 of Japanese Patent Application No. 2001-32972 can only use "normally-on type switching means." In addition, the power supply voltage rises when the power is turned on, and the power supply short-circuit current flows until a sufficient gate reverse bias voltage can be applied to the normally-on type switching means. " If a normally-off type multi-stable circuit can be formed, it is convenient to increase the choices of constituent means. The problem of the power supply short-circuit current is described in, for example, "When a multi-valued memory means is configured by using a large number of such multi-stable circuits as multi-valued memory cells, an extremely large power supply short-circuit current flows when the power is turned on, and the power supply voltage rises. It can't be lifted and can't be used. "
[0003]
SUMMARY OF THE INVENTION It is an object of the present invention to provide a multi-stable circuit which "reduces the number of components, can use normally-off type switching means, and can reduce the power supply short-circuit current when the power is turned on". (The purpose of the invention)
[0004]
[Disclosure of the invention]
That is, the present invention is a multistable circuit as described in claim 1. However, since the predetermined potential supply line means corresponds to any one of the second potential supply line means to the Nth potential supply line means, there may be only one pull-up means, Alternatively, since there may be only one pull-down means, the "each pull-up means" includes one case, and the "each pull-down means" includes one case. The case is also included. Since the self-holding type switching means constituted by the normally-off type switching means is used as the pull-up means or the pull-down means, the multi-stable circuit of the present invention has "the number of parts is small, the normally-off type switching means is small. Can be used to reduce the power supply short-circuit current at power-on. " ( The invention's effect )
[0005]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings. The embodiment shown in FIG. 1 is a four-stable or quaternary multi-stable circuit. In this embodiment, the above-mentioned N is 4, and the respective constituent elements correspond to the respective constituent means in claim 1 as follows. .
a) The power supply lines V0 to V4 correspond to the above-described first to (N + 1) th potential supply line means.
b) The input / output terminal Tio is the input / output terminal described above.
c) The power supply line V2 serves as the predetermined potential supply line means described above.
d) “Connected body of transistors 1c and 2c, diode 3c and resistors 4c to 6c connected between power supply lines V2 and V3” and “transistors 1d and 2d (diode 3d) connected between power supply lines V3 and V4” And the connection body of the resistances 4d to 6d ”is used as the pull-up means described above.
e) "Connected body of transistors 1a and 2a (and diode 3a) and resistors 4a to 6a connected between power supply lines V0 and V1" and "transistors 1b and 2b and diode 3b connected between power supply lines V1 and V2" And the connection body of the resistances 4b to 6b "is used as the pull-down means described above.
[0006]
The “self-holding type switching means constituted by the transistors 1a and 2a (and the diode 3a) and the resistors 4a to 6a” has a function of holding the ON state by itself, and the transistors 1a and 2a can drive each other on. When the potential of the output terminal Tio becomes higher than "the potential obtained by subtracting the ON / OFF threshold voltage of the transistor 1a from the potential of the power supply line V1," the self-holding switching means is turned off. Similarly, the “self-holding switching means constituted by the transistors 1b and 2b, the diode 3b, and the resistors 4b to 6b” also has a function of maintaining the ON state by itself, and the transistors 1b and 2b can drive each other on. When the potential of the output terminal Tio becomes higher than "the potential obtained by subtracting the ON / OFF threshold voltage of the transistor 1b from the potential of the power supply line V2", the self-holding type switching means is turned off.
[0007]
The “self-holding type switching means constituted by the transistors 1d and 2d (and the diode 3d) and the resistors 4d to 6d” has a function of holding the ON state by itself, and the transistors 1d and 2d can drive each other on. When the potential of the output terminal Tio becomes lower than "the potential obtained by adding the on / off threshold voltage of the transistor 2d to the potential of the power supply line V3", the self-holding type switching means is turned off. Similarly, the "self-holding switching means constituted by the transistors 1c and 2c, the diode 3c, and the resistors 4c to 6c" also has a function of holding the ON state by itself, and the transistors 1c and 2c can drive each other ON. When the potential of the output terminal Tio becomes lower than "the potential obtained by adding the ON / OFF threshold voltage of the transistor 2c to the potential of the power supply line V2", the self-holding type switching means is turned off.
[0008]
Note that if the potential of the input / output terminal Tio is always between the potential of the power supply line V0 and the potential of the power supply line V4, the diodes 3a and 3d may or may not be provided. In the embodiment shown in FIG. 1, since any one of the transistors 2a, 2b, 1c, and 1d is in a stable state, the series circuit of the emitter junction (emitter-base PN junction) of the transistor 1b and the resistor 6b is formed. Although it has a weak pull-up capability, it cannot clamp the potential of the input / output terminal Tio to the potential of the power supply line V2. That is, the "self-holding switching means constituted by the transistors 1b and 2b, the diode 3b, and the resistors 4b to 6b" does not have the ability to clamp the potential of the input / output terminal Tio in the reverse direction. In addition, if one end of the resistor 6b is reconnected from the anode to the cathode of the diode 3b, the self-holding switching means becomes a reverse blocking type, so that the unnecessary weak pull-up ability can be completely eliminated. Similarly, the series circuit of the resistor 6c and the emitter junction of the transistor 2c has a weak pull-down capability, but cannot clamp the potential of the input / output terminal Tio to the potential of the power supply line V2. That is, the "self-holding switching means constituted by the transistors 1c and 2c, the diode 3c, and the resistors 4c to 6c" does not have the ability to clamp the potential of the input / output terminal Tio in the reverse direction. In addition, if one end of the resistor 6c is connected again from the cathode to the anode of the diode 3c, the self-holding switching means becomes a reverse blocking type, so that the unnecessary weak pull-down ability can be completely eliminated.
[0009]
Then, in order to switch the stable state, that is, to rewrite the stored contents, it is necessary to determine whether the input / output terminal Tio is pulled up to the potential of the power supply line V3 or V4 or pulled down to the potential of the power supply line V0 or V1. "Whether to apply a pulse-on drive signal to any one of the transistors 2a, 2b, 1c, or 1d, or to apply a pulse-off drive signal to any three of the four transistors" or "Transistor 1a , 1b, 2c, or 2d, or a pulse-off drive signal to any three of the four transistors. " When reading the stored content, for example, the input / output terminal Tio may be connected to a "data line in which a pull resistor having a size that does not affect the stored content is connected between the power supply line v2". Instead of the transistors 1a to 1d and 2a to 2d, any type of "normally-off type switching means having the same reverse bias voltage polarity between the control terminal and the main terminal as a pair for inputting the drive signal" is used. it can. For example, there are a bipolar mode SIT, a MOS FET, an IGBT, a GTBT (a bipolar FET having a grounded groove electrode), a normally-off SI thyristor, a GTO thyristor, and the like. Instead of each diode, a "bipolar transistor having its collector and base connected" may be used. If the components between the power supply lines v2 and v1 and the DC power supply are removed and the power supply lines v2 and v1 are directly connected, the embodiment of FIG. 1 becomes a three-stable or ternary multi-stable circuit. If the same applies between the power supply lines v3 and v2, the embodiment of FIG. 1 becomes a ternary multistable circuit. If the components and the DC power supply between the power supply lines v3 and v1 are removed and the power supply lines v3 and v1 are directly connected, the embodiment of FIG. 1 becomes a bistable circuit. By the way, a circuit in which the emitter of the transistor 2c is reconnected from the power supply line V2 to the power supply line V1 and the emitter of the transistor 1b is reconnected from the power supply line V2 to the power supply line V3 in the embodiment of FIG.
[0010]
The embodiment of FIG. 2 is a six-stable or six-valued multistable circuit, and the power supply line v3 is the predetermined potential supply line means described above. The embodiment of FIG. 3 is a ten-valued multistable circuit, in which the power supply line v5 is the predetermined potential supply line means described above, and the same reference numerals are connected to the connection terminals ct1 and ct2. In the embodiment of FIG. 3, the P-MOS and the N-MOS connected to the power supply line V5 are removed, and the drain of the P-MOS (left side in FIG. 3) connected to the power supply line V6 and the N-MOS ( An embodiment in which the drain (on the left side in the figure) is connected is also possible. Each of the embodiments shown in FIGS. 4 and 5 is a seven-valued multistable circuit. In the embodiment of FIG. 4, the power supply line v4 is the above-mentioned predetermined potential supply line means, and in the embodiment of FIG. 5, the power supply line v3 is the above-mentioned predetermined potential supply line means. The embodiment of FIG. 6 is a twelve-valued multistable circuit, in which the power supply line v6 is the predetermined potential supply line means described above, and the same reference numerals are connected to the connection terminals ct3 and ct4. Also in these embodiments, if the power supply lines are directly connected as described above, it is possible to configure a number of multi-stable circuits having different multi-value numbers or a bistable circuit. In each of the embodiments shown in FIGS. 2, 3 and 6, the MOS / FET whose drain is connected to the input / output terminal Tio via a diode is replaced with a reverse blocking IGBT one by one. Each diode is unnecessary. Similarly, if reverse controllable controllable switching means is used, each diode for reverse blocking is unnecessary. In each embodiment, instead of each diode, "a bipolar transistor whose collector and base are directly connected", "a bipolar transistor whose collector and emitter are directly connected", "a junction type FET whose drain and source are directly connected", " Bipolar-mode SIT or GTBT with drain and gate directly connected, "MOS / FET with its gate, source and back gate connected", "MOS / FET with its drain and source connected and its gate and back gate connected" FETs or MOS-FETs whose drain and gate are connected and whose back gate potential is maintained so that the drain and back gate and the source and back gate do not conduct each other can be used.
[0011]
In each embodiment, the height of each power supply line is reversed, and each of the controllable switching means is composed of one controllable switching means (e.g., a P-channel type MOS.FET for an N-channel type MOS.FET) having a complementary relationship with it. An "embodiment having a symmetrical relationship with respect to the voltage direction or voltage polarity with respect to the original embodiment" in which the direction of each directional component (eg, diode) is replaced by each other is also possible. However, in that case, the function may be the same as the original, or may be different. 4 and 5 have a symmetrical relationship with each other as described above, except for the difference in the connection position of the base resistor in each preceding stage. For example, it is possible to use a plurality of multi-stable circuits having 10 or more values in a large number of decimals, and to use other than 10 values for plus / minus sign or parity check. The meaning of the diode shown by the dotted line means "it may or may not be present". Although referred to as input / output terminals for convenience, they are not actually present as terminals, but are often simply conductors or electrodes.
[0012]
Semiconductor (substrate) multilayering technology (three-dimensional IC technology) and low voltage technology strongly assist in the practical application of "multi-point computer using the present invention". If semiconductor (substrate) multi-layer technology (three-dimensional IC technology), low voltage technology, anti-voltage (electric) resistance technology, energy saving technology, cooling technology, etc. progress steadily, hexadecimal system and 100 system system , 128-ary logic circuit, arithmetic circuit or computer, etc., and a super-ultra-super computer of a hexadecimal system, a 100-system system, or a 128-system system may appear. Also, the decimal computer “DC” (Decimal Computer) eliminates, prevents, alleviates, or eliminates “a syndrome called“ computer over-adaptation ”caused by the current binary computer”, or It is expected to be healed. "Computer over-adaptation" equates to a binary thinking of a computer that has only "0" or "1", making it impossible to communicate with "others who leave vague room" and deteriorating human relationships . (Reference: Nikkei, Morning Paper, March 11, 2002, P.34, “Heart-Eating Technostress”)
[Brief description of the drawings]
1 to 6 are circuit diagrams each showing one embodiment of the present invention.

Claims

When N is 3 or a predetermined plurality that is 3 or more,
"First potential supply line means to supply (N + 1) potentials, each of which increases in numerical order from the first potential to the (N + 1) th potential, to (N + 1) th potential supply line means"; There is an input / output terminal that performs output,
Between the potential supply line means and the (N + 1) th potential supply line means, between each of the two potential supply line means which are adjacent to each other at the height of the potential, "connected to the input / output terminal and turned on. A pull-up means for pulling up the potential of the input / output terminal on the high potential side of the two potential supply line means.
Between the two potential supply line means that are adjacent to each other at the height of the potential from the first potential supply line means to the predetermined potential supply line means, "being connected to the input / output terminal, One pull-down means for pulling down the potential of the input / output terminal on the lower potential side of the two potential supply line means,
Each of the pull-up means is a `` self-holding switching means that can hold the ON state by itself and turn off when the potential of the input / output terminal falls to its own potential '',
Each of the pull-down means is a `` self-holding switching means that can hold the ON state by itself and turn off when the potential of the input / output terminal rises to its own potential '',
Each of the (N-2) self-holding type switching means provided from the second potential supply line means to the N potential supply line means is a reverse blocking type, or the input / output terminal in the reverse direction. A multi-stable circuit characterized in that it does not have the ability to clamp the potential of the circuit.