JP2006252742A - Multi-level storage means, multi-level buffer means, and bi-directional switching means - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a senary storage means having such effects that less numbers of parts, simple constitution, use of a normally-off type FET, less short circuit current of a power source at the time of applying the power source, less numbers of power source lines, prevention of increment of power source voltage, elimination of trouble at the time of read-out, reduction of power loss, reduction of erroneous discrimination of read-out contents, improving of noise proofing property are attained. <P>SOLUTION: In the senary storage means, a binary CMOS type inverter is provided between power source lines V0 to V5 in which a potential is raised successively, a source of a NMOS is grounded to the power source line V0, a source of a PMOS is grounded to the power source line V5, a series circuit (bi-directional switch) of the NMOS and the PMOS is connected to each of the power source lines V1 to V4, on/off driving of each PMOS and each NMOS is performed by the inverter shown as the figure, "an open end of the NMOS of the power source line VO, an open end of the PMOS of the power source line V5, all open ends of the series circuit, and all input terminals of the inverters" are connected and they are made an input/output terminal Tio. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The first invention relates to a multi-value storage means that can store or input / output a voltage or a potential corresponding to the numerical value or the like in three or three or more possible numerical values (or meanings or contents). This multi-value storage means can be used as a multi-value (or multi-adic) memory cell, multi-value (or multi-adic) memory, (external) multi-value (or multi-adic) information storage means or a multistable circuit. . Also, a multi-value (or multi-adic) logic circuit, a multi-value (or multi-adic) arithmetic circuit, a multi-value computer (or a multi-adic computer, in particular, 4, 8, “10”, 16, 32, 64, “100 ”, 128-base computer, etc.), various kinds of multi-value modulation communication means such as in-vehicle, wireless or wired, multi-value recording means, or multi-value (or multi-adic) control means. The second invention relates to a multi-value storage means having the same functions and effects as the first invention, having a smaller number of parts than the first invention, and having a simple configuration. The third invention relates to a multi-value buffer means to which the second invention is applied and which has a small number of parts and a simple configuration. The fourth invention relates to bidirectional switching means used in each invention.

  The multi-value storage means disclosed in Japanese Patent No. 2853041 has a problem that “the number of parts is large even though the bidirectional pull means described later is not configured”. Even if such a bidirectional pulling means can be constructed, the number of parts naturally increases. The multi-value storage means disclosed in FIGS. 27 to 36 of Japanese Patent Laid-Open No. 2000-83369, FIGS. 21 to 28 of Japanese Patent Laid-Open No. 2001-257570, and “WO 03/028214 A1” include “normally on type switching means”. (Example: Depletion type MOS FET) can only be used, and for that reason, the power supply voltage rises when the power is turned on, and a short circuit current flows until a sufficient gate reverse bias voltage can be applied to these normally-on switching means Furthermore, there is a problem that it is necessary to increase the magnitude of each power supply voltage.

  If the multi-value storage means can be configured with normally-off type switching means (for example, enhancement type MOS-FET), it is convenient to increase the number of constituent means, and the power supply short-circuit current at power-on can be reduced. The problem of the power supply short-circuit current is, for example, “When the multi-value memory means is used as a multi-value memory cell and a multi-value memory means is configured, an extremely large power-supply short-circuit current flows when the power is turned on. The power line cannot be used because it cannot be started up, or the power line burns out due to repeated power-on, or damage to the semiconductor near the power line due to thermal damage or expansion distortion It leads to the problem of “Yes”. For each power supply voltage, in order to drive off each transistor pair forming the negative resistance means, the off drive voltage must be supplied simultaneously between the gates and the sources of the paired transistors connected in series. Therefore, each power supply voltage becomes about “4 times absolute value of on / off threshold voltage”, and eventually becomes larger than that of other multi-value storage means, and switching loss at the time of rewriting stored contents Will also grow. This is because, when each transistor pair is, for example, a combination of a P-type and an N-type MOS FET, it is common to set both on / off threshold voltage absolute values equal. This is because each power supply voltage must have an absolute value of the on / off threshold voltage at least four times so that the "turned-off transistor pair" is not turned on as simultaneously as possible. The power supply voltage of a normal binary CMOS memory is approximately “the sum of absolute values of both on-off threshold voltages of P-type MOS and N-type MOS”.

  Further, in the multi-value storage means disclosed in Japanese Patent Application Laid-Open No. 2003-188696, normally-off type switching means and normally-on type switching means are used in series, so that the power supply short circuit current and the constituent means are improved. However, there is a problem that “the number of potential supply means (for example, power supply lines) increases and the total sum of the power supply voltages remains large and the switching loss at the time of rewriting the stored contents remains large”. .

  Then, the multi-value storage means disclosed in Japanese Patent Application Laid-Open No. 2004-087763 can be constituted by normally-off type switching means. “Each potential supply means and input / output means excluding the highest and lowest potential supply means (eg, input / output terminals) Etc.)), there is a problem that the bidirectional pulling means for output (means for pulling up or pulling down) is not configured. This problem causes the following problems. When the potential of the “connected external data line” is higher than the potential of the pull-up means, the external data line cannot be pulled down because there is no pull-down function, and moreover than the potential of the pull-down means. When the potential of the “connected external data line” is lower, the external data line cannot be pulled up because there is no pull-up function, or conversely, the “connected external data line” is The charge of the input / output means of the multi-value storage means is pulled up or pulled up higher than the potential of the pull-up means, or pulled down below the potential of the pull-down means. This causes problems such as changes in stored contents during reading, reading of incorrect stored contents, or delays in reading time ”and“ unstable operation ”. These problems are not only for "potential and charging charge of connected external data line" but also for "leakage current from internal conductors connected to the input / output means" and "selection for connecting the external data line and the input / output means" It is also caused by a drive current of a switch transistor or the like (eg, charge / discharge current of capacitance between gate and source of an insulated gate FET). The same applies to each of the multivalue storage means disclosed in the above-mentioned Japanese Patent No. 2853041 and Japanese Patent Laid-Open No. 2000-83369.

In order to clarify the existence of the effect of the first invention just in case, each of the multi-value storage means (Japanese Patent Application 2004) shown in FIGS. 2 and 9B considered by the inventor prior to the first invention. -303564, unpublished.) Each of the pull means (= each pull-up means and each pull-down means) is “forward voltage (or forward direction) in the multivalue storage means of n (≧ 3) in FIG. 2 and ternary value in FIG. 9B. As a result of incorporating a diode means such as a diode with a voltage), there are the following two problems, and the first invention can solve this problem. The following two problems also exist in each of the multi-value storage means described above.
(A) Since the ON voltage of each pull means increases by the forward voltage, the difference and difference between the output potentials and output voltages become smaller. As a result, “the noise margin becomes smaller and the next stage circuit (eg, read out) Circuits, etc.) are easily affected by noise, and the input numerical values corresponding to the input potential and the input voltage are easily determined.
(B) Since each pull means cannot be securely pulled smaller than the forward voltage due to the presence of the forward voltage, it becomes open in the vicinity of the original power supply potential (or power supply voltage) to be output. Since the impedance increases, it becomes easier for noise to be applied to the output signal, and the next-stage circuit amplifies the noise and has other adverse effects.

  Here, the multi-value storage means of FIG. 2 capable of temporarily storing n values will be described. All MOS FETs are normally-off type, and the potential of the power supply line V0 to power supply line V (n-1), that is, the potential v0 to potential v (n-1) increases in order. One binary CMOS memory is connected between each of the power supply lines V0 to V (n-1) and the two power supply lines, and there are (n-1) in total. The "PMOS-FET and diode series circuit" and the "diode and NMOS-FET series circuit" connected to each of the power lines V1 to V (n-2) are both unidirectional controllable switching means. And can be kept off with respect to the reverse voltage even during on-drive. The diodes DU1 to DU (n−2) and DL2 to DL (n−) are arranged so that a power supply short circuit does not occur when the (n−1) binary C · MOS memories cooperate to perform an n value storing operation. 1) is connected. Normally, the potential v0 corresponds to the numerical value “0”, the potential v1 corresponds to the numerical value “1”, the potential v2 corresponds to the numerical value “2”, and similarly, each potential corresponds to the potential v (n−1) in order. The potential v (n−1) is made to correspond to the numerical value “n−1”. Of course, other uses are possible.

  Specifically, when the input / output terminal Tio holds the potential v0, the transistors QL1 to QL (n-1) are on, but the diodes DL2 to DL (n-1) are turned on to the transistors QL2 to QL ( n-1) and the power supply short circuit between the transistor QL1 are prevented. Further, when the input / output terminal Tio holds the potential v (n-1), the transistors QU1 to QU (n-1) are on, but the diodes DU1 to DU (n-2) are turned on to the transistor QU (n-1). And the power supply short circuit of the transistors QU1 to QU (n-2) is prevented. Further, when the input / output terminal Tio holds the potential v1, the transistors QU1 and QL2 to QL (n-1) are on, but the diodes DL3 to DL (n-1) are connected to the transistors QL3 to QL (n-1). The power supply short circuit of the transistor QL2 is prevented. Moreover, at this time, the parallel circuit of “the series circuit of the transistor QU1 and the diode DU1” and “the series circuit of the diode DL2 and the transistor QL2” is substantially bi-directional pull means, that is, “pull up or pull down”. Means ". Similarly, when the input / output terminal Tio holds the potentials v2 to v (n−2), a similar parallel circuit substantially constitutes a bidirectional pulling unit.

  From here, the problem of the multi-value storage means of FIG. 2 etc. of the previous (paragraph number 0006) is explained in full detail. In the multi-value storage means of FIG. 2, for example, when the transistors QU1 and QL2 are on, the upper limit of the potential of the input / output terminal Tio is excessively higher than the forward voltage of the diode DL2, whereas when the transistors QU2 and QL3 are on Since the lower limit of the potential of the output terminal Tio is excessively reduced by the forward voltage of the diode DU2, the difference or difference between the potential v2 output and the potential v1 output is reduced. The same applies to other potential outputs. As a result, “the noise margin is reduced, the next-stage circuit (eg, readout circuit, etc.) is easily affected by noise, and the input numerical value corresponding to the input potential and the input voltage is easily determined. ].

  In general, the forward voltage of the signal diode is about 0.6 volts, and as can be seen from the voltage-current characteristics of the diode, the forward current is very small so that the forward voltage is close to zero volts. There must be. For this reason, when each “pull means with built-in diode means” pulls up or down something, it can pull firmly even if it tries to pull at a forward voltage of almost zero volts. Just pull it very very weakly. In other words, the pull means cannot pull firmly within a voltage range smaller than the forward voltage, so that the pull means becomes open near the original power supply potential (or power supply voltage) to be output. End up. That is, the output impedance becomes large. As a result, “the output signal becomes more susceptible to noise, and the next-stage circuit amplifies the noise and adversely affects the other”. These two problems also exist in each of the multi-value storage means described above.

Related technology

  Patent No. 2853041 (multi-value storage means, application of the present inventor)   JP 2000-83369 (same as above)   JP 2001-257570 (same as above)   WO 03/028214 A1 (same as above)   JP 2003-188696 (same as above)   JP 2004-88763 (same as above)   Japanese Patent Application No. 2004-303564

Disclosure of the first invention

Problems to be solved by the first invention

The conventional problems are as follows. (Task)
a) The number of parts is large. (Multi-value storage means of Patent Document 1)
b) It is desirable to increase the number of constituent means. (Each multi-value storage means of patent documents 2-4)
c) There are many power supply short-circuit currents at the time of power-on, and there are adverse effects due to the power supply short-circuit currents.
(Each multi-value storage means of patent documents 2-4)
d) The magnitude of each power supply voltage must be increased, increasing power loss.
(Each multi-value storage means of patent documents 2-5)
e) The number of potential supply means (eg, power supply lines) is large. (Multi-value storage means of Patent Document 5)
f) Since there is no bidirectional pull means for output between each potential supply means except the highest and lowest potential supply means and the input / output means (eg, input / output terminals), Impossible, changes in stored contents at the time of reading, reading of wrong stored contents, or delays in reading time ”and“ unstable operation ”occur. (Multivalue storage means in Patent Documents 1, 2, and 6)
g) Since each pull means incorporates “diode means with forward voltage”, the noise margin is reduced, the next stage circuit is easily affected by noise, and the input numerical value etc. is easily discriminated, Noise is easily applied to the output signal, and the next-stage circuit amplifies the noise to have other adverse effects. (Each multivalue storage means of patent documents 1-7)

Therefore, the first invention aims to provide a multi-value storage means having the following characteristics.
(Object of the first invention)
a) The number of parts is small.
b) Since all can be constituted by normally-off type switching means, the combination of the conventional multi-value storage means increases the choices of the construction means, which is convenient.
c) It is possible to reduce the power supply short-circuit current when the power is turned on, and to eliminate or reduce the adverse effects caused by the power supply short-circuit current.
d) It is not necessary to increase the magnitude of each power supply voltage, and an increase in power loss can be avoided.
e) The number of potential supply means is not increased.
f) Bidirectional pull means for output can be configured substantially between each potential supply means excluding the highest and lowest potential supply means and input / output means (eg, input / output terminals). There is no “impossibility, change in stored contents at the time of reading, reading of wrong stored contents, delay in reading time”, and the operation becomes stable.
g) Since each pull means does not incorporate a “diode means with forward voltage”, the noise margin increases, the next stage circuit is less susceptible to noise, and it is difficult to discriminate the input numerical value, etc. In addition, it is difficult for noise to be applied to the output signal, and the subsequent stage circuit is less likely to amplify the noise, thereby making it difficult to affect the others.

Means to solve the problem

  That is, the first invention is the multi-value storage means described in claim 1. In the first potential supply means to the Nth potential supply means, one binary storage means is provided between each of two potential supply means adjacent to each other by number, and a total of (N−1) 2 There is a value storage means. 2. As described in claim 1, each of the binary storage means that are in an up-and-down relationship with each other does not short-circuit the power supply means between the potential supply means. The first controllable switching means are connected in series one by one to form an output pull-up series circuit. Similarly, each second output controllable switching means is connected in series to each specific output pull-down switching means. Connected to form a series circuit for output pull-down. In addition, a parallel circuit of “the output pull-up series circuit and the output pull-down series circuit” is connected to each of the second to (N−1) th potential supply means one by one. Each parallel circuit substantially functions as a bidirectional pulling means.

  Thus, (N−1) pieces of the binary storage means cooperate to function as a multi-value storage means. Further, the binary storage means other than the uppermost binary storage means output the output so that there is no problem even if the input / output means (eg, input / output terminals) of all the binary storage means are connected. When the pull-up switching means is on and a reverse voltage is applied to the “series circuit of output pull-up switching means and first controllable switching means”, the first controllable switching means is driven off. The output pull-up switching means is on, and when the forward voltage is applied to the series circuit, the first controllable switching means is also driven on, The series circuit performs an output pull-up operation. Furthermore, the output pull down switching means is turned on in each binary storage means except the lowest binary storage means so that there is no problem. When a reverse voltage is applied to the `` series circuit of control switching means '', the second controllable switching means is driven off to prevent the reverse voltage, while its output pull-down switching means is on, When a forward voltage is applied to the series circuit, the second controllable switching means is also turned on, and the series circuit performs an output pull-down operation.

  When the multi-value storage means holds the first potential, the output pull-down switching means at the first potential is on, the output pull-up switching means at the Nth potential, The parallel circuit of the series circuit for output and the series circuit for output pull-down is off. When the multi-value storage means holds the Nth potential, the output pull-up / switching means for the Nth potential is on, and the output pull-down / switching means for the first potential and each of the above parallel circuits. Is off. Further, when the multi-value storage means holds a certain potential from the second potential to the (N-1) th potential, the output pull-down above the potential and the potential is set at the potential. “All switching means” and “all the output pull-up switching means below that potential and below that potential” are turned on. However, even if they are turned on, as described above, each of the first controllable switching means and each of the second controllable switching means acts on the reverse voltage with respect to each of the output pull-up series circuits and Since the “output pull-down series circuit” is turned off, only the parallel circuit of the potential is turned on bidirectionally and functions as bidirectional pulling means, so that a power supply short circuit does not occur.

Effects of the first invention

As a result, the multi-value storage means of the first invention has the following effects.
a) The number of parts can be reduced as compared with the multi-value storage means of Japanese Patent No. 2853041.
b) Since all can be constituted by normally-off type switching means, the combination of the conventional multi-value storage means increases the choices of the construction means, which is convenient.
c) Since all can be configured by normally-off type switching means, the power supply short-circuit current when the power is turned on can be reduced, and the adverse effects of the power supply short-circuit current can be eliminated or reduced.
d) Since a conventional normally-off type binary storage means (which may be new) can be used, it is not necessary to increase the magnitude of each power supply voltage, and an increase in power loss can be avoided.
e) The number of potential supply means is not increased.
f) Bidirectional pull means for output can be formed between each potential supply means except the highest and lowest potential supply means and the input / output means (eg, input / output terminal).
g) Since each pull means does not include “diode means with forward voltage”, the noise margin increases, the next-stage circuit is hardly affected by noise, and the input numerical value and the like are difficult to discriminate. In addition, since each pulling means can be pulled firmly, it is difficult for noise to be applied to the output signal, and the subsequent stage circuit is less likely to amplify the noise, making it difficult to affect the others.

  In the multi-value storage means of the first invention, there is substantially bidirectionality between each of the second potential supply means to the (N-1) th potential supply means and its input / output means (eg, input / output terminal). Since the pull means is configured, when the external data line is connected to the input / output means and the stored data is read, the potential of the external data line is higher than the potential of the “content stored at the time of reading”. Even if it is low or low, the external data line is pulled up or down depending on the stored contents. In addition, there is no “reading of stored contents”, and the reading time is shortened and the operation is stabilized. In addition, each of the substantially bidirectional pull means includes not only “potential and charge charge of external data line to be connected” but also “leakage current from a conductive line inside the multi-value storage means connected to the input / output means” and “ Similar problems caused by the drive current (eg, charge / discharge current of the gate-source capacitance of an insulated gate FET) that connects the external data line and its input / output means It is also effective against

Disclosure of the second invention

Problems to be solved by the second invention

In any field, “the same function and the same effect are desired, but a small number of parts, a simple structure, and a low production cost are desired”. The same applies to the first invention. (Task)
Therefore, the second invention provides "a multi-value storage means that can be realized with the same function and the same effect as the multi-value storage means of the first invention, but with a small number of parts, a simple configuration, and a low manufacturing cost". It is an object. (Object of the second invention)

Means to solve the problem

  That is, the second invention is the multivalue storage means described in claim 2. In the multi-value storage means of the first invention described above, the potential supply means of the second potential to the (N-1) th potential is “the output pull-up series circuit connected to the potential supply means and the output pull-up. Since both of the series circuits for down function as bidirectional switching means, that is, bidirectional pull means, the second invention is “the two series circuits connected to the respective potential supply means”. Among them, it is a multi-value storage means in which either one is removed.

Effects of the second invention

  As a result, the “multi-value storage means” of the first invention is simply removed from the multi-value storage means of the first invention, so that the second invention has the functions and effects of the multi-value storage means of the first invention as it is. , Small number of parts, simple configuration and low manufacturing cost.

Disclosure of the third invention

Problems to be solved by the third invention

A multi-value buffer means capable of realizing a small number of parts, a simple configuration, and a low production cost is desired. Conventionally, there was no such multi-value buffer means. (Task)
Therefore, the third invention is intended to provide the “multi-value buffer means with a small number of parts, a simple configuration, and a low manufacturing cost” by applying the first or second invention. (Object of the third invention)

Means to solve the problem

  That is, the third invention is the multi-value buffer means described in claim 3. Since the multi-value storage means of the first or second invention is just “a configuration in which the output signal is positively fed back to the input side in the multi-value buffer means of the third invention”, the third invention is the opposite of “the first or second invention. The multi-value buffer means is configured to block the positive feedback of the output signal in the multi-value storage means.

Effects of the third invention

  As a result, the third aspect of the invention is simply “blocking the positive feedback of the output signal” in the multi-value storage means of the first or second aspect of the invention. Multi-value buffer means having the characteristic of “low cost and low manufacturing cost” can be realized.

Disclosure of the fourth invention

Problems to be solved by the fourth invention

Of course, it can be used as a general bidirectional switching means, but in order to be able to construct a complementary circuit such as a C • MOS • FET or a PNP / NPN complementary type as a whole, “C • MOS • It is also possible to use on / off drive means using complementary three-terminal switching means such as FETs. In particular, in a multi-valued or multi-valued logic circuit, it is important to realize a C / MOS / FET circuit configuration from the viewpoint of power saving. (Task)
Accordingly, the fourth invention aims to provide a “bidirectional switching means that can also use an on / off drive means using a complementary three-terminal switching means such as a C / MOS / FET”. (Object of the fourth invention)

Means to solve the problem

  That is, the fourth invention is the bidirectional switching means described in claim 4. Both “switching directions that can control switching” are opposite to each other, and both are connected in series, and the other on / off drive is performed via one, thereby providing both on / off drive means at one main electrode. Provided.

Effects of the fourth invention

  As a result, the on / off driving means using the three-terminal switching means can be used to impair the bidirectional switching function. As a result, “on / off using the complementary three-terminal switching means such as C / MOS / FET”・ Off drive means can also be used. In particular, since a C / MOS / FET circuit configuration can be realized in a multi-value logic circuit or the like, power consumption can be reduced.

  In order to explain the present invention in more detail, this will be described with reference to the accompanying drawings. Note that the potential of the power supply line V0 is represented by the potential v0, the potential of the power supply line V1 is represented by the potential v1, and thereafter, similarly, each potential from the power supply line V2 to the power supply line V (n−1) is represented by the potential v2 to the potential v ( n-1). Further, the potential increases in order from the potential v0 to the potential v (n-1).

The embodiment 1 shown in FIG. 1 is a 10-value multi-value storage means, and the above-mentioned N is 10, and the conductors having the same reference numerals with respect to the signs s1 to s5 are in a conductive state. All the MOS FETs are normally-off type, ie, enhancement mode FETs, and one binary CMOS memory is connected between each power supply line, and there are nine in total. 1 correspond to the constituent means in claim 1 as follows.
a) The potential v0 to the potential v9 are sequentially changed to the first potential to the Nth potential in the same paragraph.
b) The power supply line V0 to the power supply line V9 are sequentially supplied to the first potential supply means to the Nth potential supply means in the same paragraph.
c) The input / output terminal Tio is the input / output means described in the same paragraph.
d) Nine binary CMOS memories connected one by one between each power source line V0 to power source line V9 to the binary storage means described in the same paragraph.
e) Each of the transistors 1c to 9c is connected to the output pull-up switching means described in the same paragraph.
f) Each of the transistors 1d-9d is connected to the output pull-down switching means described in the same paragraph.
g) Each of the transistors 1e to 8e is respectively connected to the first controllable switching means described in the same paragraph.
h) Each of the transistors 2f to 9f is respectively connected to the second controllable switching means described in the same paragraph.
i) Each series circuit of the transistors “1c, 1e”, “2c, 2e”..., “8c, 8e” is replaced with each series circuit for output pull-up described in the same paragraph.
j) Each series circuit of the transistors “2f, 2d”, “3f, 3d”..., “9f, 9d” is replaced with each output pull-down series circuit described in the same paragraph.

  In order to prevent a power supply short circuit even if the input / output terminals of all the binary CMOS memories are connected and combined into one input / output terminal Tio, the reverse voltage is applied to each of the transistors 1c to 8c during the ON period. The reverse blocking transistors 1e to 8e, which are sometimes off at times, block, while the reverse voltages during the ON periods of the transistors 2d to 9d are "reverse blocking transistors 2f to 9f that are off when the reverse voltage is applied." Each "stops. For example, when the input / output terminal Tio holds the potential v1, the transistors “2a-9a, 2d-9d, 1c, 1b” are on and the transistors “2c-9c, 2b-9b, 1a, 1d” are off, Transistors “1e-8e, 2f” are on, and transistors “3f-9f” are off. As a result, these transistors do not short-circuit the power supply lines. In other words, a power supply short circuit does not occur. When this potential v1 is maintained, the transistors "2f, 2d, 1c, 1e" that are on conduct bidirectionally between the power supply line V1 and the input / output terminal Tio, and these transistors are bidirectional pulling means (pull-up Or a pull-down means), and substantially constitutes a bidirectional pull means. Such bidirectional pull means is configured in the same manner not only when holding the potential v1 but also when holding each potential of the potentials v2 to v8.

  Each binary storage means of the present invention has a common input / output type, that is, a type in which a portion for inputting a write signal or outputting a read signal (= input / output means, eg, input / output terminal) is common. Is used. The first embodiment uses, for example, the potential v0 corresponding to the numerical value “0”, the potential v1 corresponding to the numerical value “1”, the potential v2 corresponding to the numerical value “2”,..., And the potential v9 corresponding to the numerical value “9”. Of course, it is possible to use each power supply potential in correspondence with an arbitrary code, meaning, or content. For example, numerical values “−2” to “7” or characters “a” to “j” may be used instead of the numerical values “0” to “9”. The usage of other embodiments is the same. Further, the external data line is connected to the input / output terminal Tio by a selection switch / transistor or the like at the time of writing and reading, but the word selection method can be used when the multi-value storage means of the present invention is used as a memory cell. . Further, the writing of the multi-value storage means of the present invention is performed by pulling up / down the input / output terminal Tio and holding it at “potential or voltage corresponding to the written numerical value”, and reading out the input / output terminal. The potential or voltage of Tio is discriminated and its numerical value is read. Then, if the on-drive voltage polarity is the same as each FET, “normally-off control electrode insulation type switching means in which the roles of both main electrodes can be interchanged depending on the direction of the applied voltage” instead of each FET is 1 Can be used one by one.

  The back gates of the transistors 1a to 9a are connected to the source and “power supply line having a higher potential than the source”, and the back gates of the transistors 1b to 9b are connected to the source and “power supply line having a lower potential than the source”. Etc. ". On the other hand, the back gates of the transistors 2f to 9f are connected to their sources, but the power supply line V9 (or the power supply line V9) so that the back gate-source PN junction and the back gate-drain PN junction are not conductive. Similarly, the back gate of each of the transistors 1e to 8e is connected to the source thereof, but the back gate-source PN junction and the back gate / drain thereof are also connected. It may be connected to a power supply line V0 (or a power supply line having a potential lower than that of the power supply line V0) so that the inter-PN junction does not conduct. By the way, each of the reverse blocking transistors “1e to 8e, 2f to 9f” The roles of the drain and source are interchanged depending on the applied voltage direction between the drain and source. May be actively used as a built-in diode between PN junction. This is also true in the embodiments using the MOS · FET to be described later.

  In the embodiment of FIG. 1, the "power supply (not shown) and binary memory" between the power supply line V2 and the power supply line V1 is removed, and the power supply line V2 and the power supply line V1 are directly connected to share both power supply lines. An embodiment of nine-value multivalue storage means is possible in which the gate of 1e is connected to both drains of the transistors 3a and 3b, and the gate of the transistor 3f is connected to both drains of the transistors 1a and 1b. Remove the “power supply (not shown) and binary memory” between the power supply lines V2, connect the power supply lines V1 to V3 directly to share the three power supply lines, and connect the gate of the transistor 1e to both drains of the transistors 4a and 4b. An embodiment of an eight-value multi-value storage means is possible in which the gates of the transistor 4f are connected to both drains of the transistors 1a and 1b. After that, in the same way, “sequential removal of power supply and binary memory, commonization of power supply lines, and reconnection of gates” is performed in order, and 7-value to 3-value multivalue storage means becomes possible. . The same applies to other embodiments described later, and different embodiments having different multi-value numbers (for example, N of N values, 10 for 10 values, and so on) can be configured. (Derived Example)

  In the third embodiment shown in FIG. 3, the ten-value storage is changed from the ten-value storage to the four-value storage in the first embodiment shown in FIG. 1, and the connection of each gate of the transistors 1a and 2a is connected from the input / output terminal Tio to each drain of the transistors 1c and 2c. This is a quaternary multi-value storage means in which the connections of the gates of the transistors 2b and 3b are changed from the input / output terminal Tio to the drains of the transistors 2d and 3d.

  In the fourth embodiment shown in FIG. 4, the upper and lower connections of the transistors “1e and 1c, 2e and 2c..., 8e and 8c” and the transistors “2d and 2f, 3d and 3f. .., 9d and 9f "are 10-value multi-value storage means in which the upper and lower connections are interchanged. In this case, the back gate of each of the transistors 1c to 8c is connected to the source thereof, or the power line V9 (or the power line) so that the back gate-source PN junction and the back gate-drain PN junction are not conductive. Similarly, the back gate of each of the transistors 2d to 9d is also connected to the source thereof, or the back gate-source PN junction or the back gate-drain PN junction. Is connected to the power supply line V0 (or a power supply line having a lower potential than the power supply line V0, etc.) On the other hand, the back gates of the transistors 1e to 8e are connected to their sources. May be reconnected to a lower power line, etc. And the back of each of the transistors 2f-9f Although the gate is connected to its source, it may be reconnected to “a power supply line higher than its source potential, etc.” Note that the conductors having the same reference numerals t1 to t5 in FIG. It is in a state.

  In the fifth embodiment shown in FIG. 5, the ten-value storage is changed from the ten-value storage in the first embodiment shown in FIG. 1, and a PNP transistor with a base current limiting means is used in place of each P-type MOS • FET, and each N-type MOS is used. -An NPN transistor with a base current limiting means is used instead of an FET, and the roles of the collector and emitter of the transistors 11e to 13e and transistors 12f to 14f are interchanged depending on the direction of the applied voltage between the collector and the emitter. This is a five-value multi-value storage means using what can be used. When reading the stored content, the input resistance of the potential (or voltage) discrimination means of the reading means is large, so that each on-driving transistor is overdriven and is in a supersaturated state, and the on-voltage becomes the forward voltage of the diode. Smaller than that. The same applies to Examples 6 to 7 described later.

  The sixth embodiment shown in FIG. 6 uses a PNP transistor with base current limiting means instead of each P-type MOS.FET in the third embodiment of FIG. 3, and has base current limiting means instead of each N-type MOS.FET. Using an NPN transistor, each of the transistors 11e to 12e and transistors 12f to 13f has a quaternary value using the collector and emitter whose roles can be interchanged depending on the direction of the applied voltage between the collector and the emitter. Multi-value storage means.

  In the seventh embodiment shown in FIG. 7, the ten-value memory is changed from the ten-value memory to the five-value memory in the fourth embodiment shown in FIG. 4, and a PNP transistor with a base current limiting means is used instead of each P-type MOS FET. -An NPN transistor with a base current limiting means is used instead of an FET, and the roles of the collector and emitter of the transistors 11e to 13e and transistors 12f to 14f are interchanged depending on the direction of the applied voltage between the collector and the emitter. This is a five-value multi-value storage means using what can be used.

  In the eighth embodiment shown in FIG. 8A, all “power supplies (not shown) and circuit components” between the power supply line V8 and the power supply line V1 except the input / output terminal Tio in the embodiment of FIG. The power supply line V8 and the power supply line V1 are directly connected to share both power supply lines, the gate of the transistor 1e is connected to both drains of the transistors 9a and 9b, and the gate of the transistor 9f is connected to both drains of the transistors 1a and 1b. The ternary multi-value storage means. That is, it is a ternary storage means such as a binary memory between the power supply line V9 and the power supply line V8, a binary memory between the power supply line V1 and the power supply line V0, and an input / output terminal Tio. Similarly, in each of the other embodiments, the ternary storage means is configured by directly connecting the two binary memories up and down, leaving only the highest binary memory, the lowest binary memory, and the input / output terminal Tio. Can do. (Derived Example)

  In the ninth embodiment shown in FIG. 8B, all “power supplies (not shown) and circuit components” between the power supply line V8 and the power supply line V1 except the input / output terminal Tio in the embodiment of FIG. The power supply line V8 and the power supply line V1 are directly connected to share both power supply lines, the gate of the transistor 1e is connected to both drains of the transistors 9a and 9b, and the gate of the transistor 9f is connected to both drains of the transistors 1a and 1b. The ternary multi-value storage means.

  The embodiment 10 shown in FIG. 9A removes the “power supply (not shown) and all circuit components” between the power supply line V2 and the power supply line V1, leaving the input / output terminal Tio in the embodiment of FIG. The power supply line V2 and the power supply line V1 are directly connected to share both power supply lines, the gate of the transistor 1e is connected to both drains of the transistors 3a and 3b, and the gate of the transistor 3f is connected to both drains of the transistors 1a and 1b. This is a ternary multi-value storage means.

  Example 11 (second invention) shown in FIG. 10 is a six-value multivalue storage means in which the transistors “1c to 8c, 1e to 8e” in the embodiment of FIG. It is. In the embodiment of FIG. 1, both the series circuit of the transistors 1c and 1e and the series circuit of the transistors 2f and 2d function as bidirectional pulling means, and have only one function. Therefore, one of them can be removed. Similarly, “a series circuit of transistors 2c and 2e and a series circuit of transistors 3f and 3d”, “a series circuit of transistors 3c and 3e and a series circuit of transistors 4f and 4d”, and so on, “a series circuit of transistors 8c and 8e” The same can be said for each of the "series circuit of transistors 9f and 9d", and one of the series circuits can be removed one by one. Similarly, in each of the first to tenth embodiments of the first invention, either one of the same two series circuits can be removed one by one, and this embodiment can be removed from the multivalue storage means of the second invention. This is an example (derived example).

  In the twelfth embodiment (second invention), the transistors 2f, 2d, 3f, and 3d in the third embodiment shown in FIG. 3 are removed, and both gates of the transistors 2b and 3b that are opened by detachment are connected to the input / output terminal Tio. This is a four-value multivalue storage means. Alternatively, it is a quaternary multi-value storage means in which the transistors 1c, 1e, 2c, and 2e in Example 3 are removed, and both gates of the transistors 1a and 2a that are opened by the removal are connected to the input / output terminal Tio.

  The embodiment 13 (third invention) shown in FIG. 11 cuts off the positive feedback of the output signal to each input portion of the binary CMOS inverter on the left side of FIG. 10 in the embodiment 11 (second invention) of FIG. In order to do this, all the gates of the MOS FETs on the left side of FIG. 10 and the input / output terminal Tio are disconnected once, all the gates are connected to the input terminal In, and the input / output terminal Tio is changed to the output terminal Out. Multi-value buffer means. In other words, if the input terminal In and the output terminal Out of the twelfth embodiment (third invention) of FIG. Similarly, in each of Examples 1 to 10, 12 (first or second invention) and its derivative examples (first or second invention) and Examples 11 to 12 (second invention). If, for example, the positive feedback of the output signal to the input section is cut off, it becomes the multi-value buffer means of the third invention (each derivative embodiment). Contrast: A multi-value AND circuit (paragraph number 0032) disclosed in Japanese Patent Application Laid-Open No. 2004-32702 with one input terminal.

  Example 14 (fourth invention) shown in FIG. 12C is a bidirectional switching means that can be used in the first to third inventions. FIG. 12A is a “circuit diagram for explaining that the bidirectional switching means of FIG. 12C can be kept off in both directions when it is driven off in both directions”. In the circuit of FIG. 12A, “NMOS with shorted gate and source” can be kept off with respect to voltage application from the right terminal to the left terminal. On the other hand, if the PMOS tries to conduct even a little when the voltage is applied from the terminal on the left side of the figure to the terminal on the right side of the figure, the leakage current causes a voltage drop in the NMOS. Becomes a gate reverse bias voltage for the PMOS, so that the PMOS is driven off. Eventually, the circuit of FIG. 12A can be kept off in both directions. Therefore, it can be seen that in Example 14 (fourth invention) of FIG. 12C, the PMOS and NMOS can be simultaneously turned on or off simultaneously. Of course, it may be turned on one by one depending on how it is used, as in the first to third inventions. It is clear that two sets of “three-terminal switch and two resistor connections” can be replaced with CMOS FETs or “connectors such as PNP and NPN with a base current limiting resistor”. Each of 1 to 13 has the configuration of Example 14 (fourth invention) of FIG.

  The fifteenth embodiment (fourth invention) shown in FIG. 12D is also a bidirectional switching means used in the first to third inventions, but the fifteenth embodiment is merely P in the fourteenth embodiment shown in FIG. The connection positions of both the type and N type MOS • FETs are simply interchanged. FIG. 12B is also a “circuit diagram for explaining that the bidirectional switching means of FIG. 12D can be kept off in both directions when it is driven off in both directions”, but FIG. The effects and usage of the circuit are the same as described above. Each of Examples 1 to 10 and 12 has the configuration of Example 15 in FIG. In the embodiment 15 of FIG. 12D, a series circuit of a gate reverse bias DC power source and a resistor is used in place of both the PMOS and NMOS off-drive resistors (two resistors connected between the three-terminal switches). Can be used. In this case, the PMOS gate forward bias DC power source can also be used as the NMOS gate reverse bias DC power source, and the NMOS gate forward bias DC power source can also be used as the PMOS gate reverse bias DC power source. Also, each back gate is connected to each source, but of course, each connection is once disconnected, and each back gate potential is maintained so that the back gate / source PN junction and the back gate / drain PN junction do not conduct. It doesn't matter. This power sharing and back gate connection change are the same in the embodiment 14 of FIG.

  A supplementary explanation will be given at the end. For convenience of explanation, it is referred to as an input / output terminal (corresponding to the input / output means in claim 1), but it does not actually exist as a terminal, but is simply a lead wire or an electrode in many cases. This is the same as what is called a base terminal, a base electrode, and a base lead wire of a transistor, for example. In addition, the storage contents can be written or read out from the binary inverter side on the left side of each figure without using the input / output terminals, or from both sides. Furthermore, for example, a PMOS and NMOS series circuit is more advantageous in terms of on-voltage than a series circuit of MOS.FET and diode. This is because, for a diode, the voltage drop for the forward voltage must be taken into consideration, but in the series circuit, the sum of both on-resistances is sufficient, so each on-resistance can be reduced, and the source current and sink for read determination can be reduced. This is because the current is small and advantageous.

  In particular, “the second to third inventions with a small number of parts, simple configuration and low manufacturing cost” and “fourth invention with a new basic configuration” have high industrial applicability.

（ａ）と（ｂ）に第１発明の実施例を２つ示す回路図である。 （ａ）に第１発明の１実施例を示し、（ｂ）に同じく本発明者の先の発明回路を示す回路図である。 第２発明の１実施例を示す回路図である。 第３発明の１実施例を示す回路図である。 第４発明の実施例２つとその説明回路２つを示す回路図である。 It is a circuit diagram showing one embodiment of the first invention. It is a circuit diagram which shows this invention circuit of this inventor used by description of an invention effect.

(A) And (b) is a circuit diagram which shows two Examples of 1st invention. (A) shows one embodiment of the first invention, and (b) is a circuit diagram showing the inventor's previous invention circuit. It is a circuit diagram which shows one Example of 2nd invention. It is a circuit diagram which shows one Example of 3rd invention. It is a circuit diagram which shows two Example of 4th invention, and its explanatory circuit.

Claims (4)

When three or three or more predetermined plurals are represented by N,
Having a first potential supply means to an Nth potential supply means for supplying N potentials whose potentials increase in numerical order from the first potential to the Nth potential;
"Binary having input / output means for inputting a write signal or outputting a read signal therefrom, normally-off output pull-up switching means, and normally-off output pull-down switching means One storage means "is provided between each of the two potential supply means adjacent to each other by a number,
In each of the binary storage means other than the highest-level binary storage means, instead of the output pull-up switching means, “the output pull-up switching means” and “normally off, the on drive voltage polarity is A series circuit of “first controllable switching means” in which the roles of the two main electrodes can be switched with each other depending on the direction of the applied voltage, and the complementary output of the upper binary storage means is used as a drive signal. Use
In each of the binary storage means except the lowest binary storage means, the output pull-down switching means and the output pull-down switching means are normally off and the ON drive voltage polarity is A series circuit of “second controllable switching means” in which the roles of the two main electrodes can be switched with each other depending on the direction of the applied voltage, and the complementary output of the binary storage means one level lower is used as a drive signal. Use
A multi-value storage means characterized in that all the input / output means are connected and combined into one input / output means. One of the two series circuits connected to each of the second potential supply means to the (N-1) th potential supply means is removed one by one, and a control electrode or a control terminal opened by the removal is provided. 2. The multi-value storage means according to claim 1, wherein if present, the control electrode or the control terminal is connected to the input / output means. 3. The multi-value storage means according to claim 1 or 2, wherein the "input means for inputting a signal therefrom" of each binary inverter means for outputting the complementary outputs one by one in the constituent means of each binary storage means. Multi-value buffer means characterized in that it is separated from each of the series circuits, all of the input means are connected and combined into one input means, and the input / output means is used as output means. There are “two controllable switching means in which the roles of both main electrodes can be interchanged with each other depending on the direction of the applied voltage, both of which are complementary to each other”
Of the two controllable switching means, one main electrode and the other main electrode are connected,
One on / off driving means is provided between one open main electrode and one control electrode,
The other on / off drive means is provided between one open main electrode and the other control electrode,
A bidirectional switching means characterized in that a series circuit of both controllable switching means is used as a bidirectional switch.

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