JPH04111298A - Memory circuit - Google Patents

Abstract

PURPOSE:To make the holding current of a data zero by complementarily turning on/off two circuit elements having a negative resistance characteristic. CONSTITUTION:The respective sources of mutually reversely conductive transistors M11 and M12 are connected in common, and the gate of one transistor is connected to the drain of the other transistor each other so as to form a negative resistance element. Similarly, the respective sources of transistors M14 and M15 are connected in common, and the drain of a path transistor M13 is connected to the drain connecting part mutually between the transistors M11 and M15. In this case, the two circuit elements are complementarily turned on/off, and data at 'H' and 'L' levels can be held almost without letting any current flow. On the other hand, since the circuit element connected to a power supply terminal is turned to a low impedance efficiently when being turned on, holding force immune to capacity load can be obtained as well. Thus, the data holding current can be unnecessitated, and the data can be held without fail.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a low power consumption memory circuit used in battery-powered computers, memory cards, and the like.

Conventional technology Static random access memory (StaticR)
andom Access Memory SR
A.M. ) is a dynamic random access memory (Dynamic Random Access M
It does not require complicated refresh control like memory (hereinafter referred to as DRAM), and does not require multiplexing of addresses, making it easy to use and providing high-speed performance. Furthermore, since it is possible to reduce power consumption, it is widely used in battery-powered computers, memory cards, and the like.

The basic circuit of SRAM is a flip-flop circuit, but the basic circuit element can also be realized using a negative resistance element.

An example of an SRAM using a conventional negative resistance element will be explained using the memory circuit diagram shown in FIG.

In FIG. 5, 1 indicates a power supply terminal, and the drain of an N-channel depletion field effect transistor M1 is connected to the power supply terminal 1 through a resistor R, and the source of the transistor M1 is a P-channel depletion field effect transistor. Connected to the source of transistor M2. The gates of the transistors M1 and M2 are connected to the drains of the other, and the drain of the transistor M2 is connected to the connection terminal 2. Furthermore, the source of the pass transistor M3 is the transistor M1
Its drain is connected to the bit terminal 3 of the SRAM, and its gate is connected to the word terminal 4 of the SRAM.

FIG. 6 is a characteristic diagram showing the operating load curve of this SRAM. Next, the operation will be explained using this characteristic diagram. The solid lines shown in FIG. 6 are transistor M1 and transistor M2.
This is the current-voltage characteristic of a circuit element that is directly connected to the circuit element, and has negative resistance characteristics.

Also, the broken line in the figure shows the load characteristics when the resistor R is coupled to the load, and among the voltages at the intersection of the solid line and the broken line, the high voltage VH1 and the low voltage VL at both ends become the bistable point of this SRAM, and the middle voltage potential V. becomes a critical point. “H” level voltage vH is approximately close to the power supply voltage applied to power supply terminal 1 (
, the "L" level voltage vL has a value close to the ground potential.

Therefore, when a voltage is applied to the word line terminal 4 and an "H" level voltage VH is applied to the bit line terminal 3 so that the pass transistor M3 is turned on, the circuit element consisting of the transistor M1 and the transistor M2 is turned off. , voltage V1□ is held, and the "write "H"operation" is completed. Immediately after that, when transistor M3 is turned off, "H level data" is held.Similarly, when pass transistor M3 is turned on and a predetermined "L" level voltage is applied to bit line terminal 3, transistors M1 and M2 The circuit elements consisting of are turned on, the voltage vL is held, and the "L" level writing operation is completed. Immediately after that, when transistor M3 is turned off, the data at the "I7" level is held. Each data "read" operation is completed by turning on pass transistor M3 and detecting the drain voltage of transistor M1.

At this time, if the detected potential is less than the critical potential V shown in FIG. 6, the level is "L" and the critical potential V is reached. In the above case, “H”
``Recognize the level.

Problem to be Solved by the Invention However, when maintaining the data ("H" level, "L" level) retention state with the above configuration, the "H" level voltage vH as shown in FIG. Although no current flows through the resistor R, a current flows when the voltage V is at the "L" level.

Therefore, if this SRAM is used in a battery-powered device, the battery will be consumed to maintain the data retention state.
It was difficult to retain data for a long time.

In addition, during a "read" operation, the ability to hold the "H" level was weak (and it sometimes became the "L" level. This is because when the bit line terminal 3 has a large capacitive load, the capacitive load This is because a voltage drop occurs in the resistor R due to the current charging the resistor R, and when this voltage drop exceeds a certain threshold value, "L" level writing occurs.

In this way, conventional SRAM requires current to flow in order to retain data at the "L" level, and has a problem in that it has a weak ability to retain data at the "H" level, resulting in malfunctions when reading data. Ta.

In view of this problem, the present invention provides an SRAM that does not require current for data retention and that can securely retain data.

Means for Solving the Problems In order to solve the above problems, the present invention provides a method in which both sources of field effect transistors having channel regions having opposite conductivity are connected in common, and the gate of one is connected to the drain of the other. The present invention provides a memory circuit in which circuit elements configured as shown in FIG. Further, a memory circuit is also provided that uses a nonvolatile transistor having a tunneling electrode as one of two circuit elements constituting the memory circuit.

Operation According to the present invention, with such a configuration, two circuit elements are turned on and off in a complementary manner, and data retention at "H" and "L" levels can be realized with almost no current flowing. Further, since the circuit elements connected to the power supply terminal have sufficiently low impedance when turned on, a strong holding force can be obtained even against a capacitive load.

Embodiment Hereinafter, an SRAM circuit according to an embodiment of the present invention will be described with reference to the circuit diagram of FIG.

In FIG. 1, Mll and M14 are N-channel depletion type field effect transistors, M12゜M2S is a P-channel depletion type field effect transistor, M2S is a pass transistor, 11 is a power supply terminal, 12 is a ground terminal,
13 indicates a bit line terminal, and 14 indicates a word line terminal. First, the sources of the transistor Mll and the transistor M12, which have opposite conductivity to each other, are connected in common, and the gate of one transistor is connected to the drain of the other transistor to form a negative resistance element. Similarly transistor M14
and the sources of the transistor M15 are connected in common, and the gate of one transistor is connected to the drain of the other transistor to form a negative resistance element. The transistors Mll and M12. connected in this way. In addition, two negative resistance elements, transistors M14 and M2S, are connected in series at the drains of transistors M11 and M15, and the power terminal 11 is connected to the train of transistor M1.4, and the ground terminal 12 is connected to the drain of transistor M12. Connect to. Further, the drain of the pass transistor M13 is connected to the drain connection portion of the transistor Mll and the transistor M15.

FIG. 2 describes the operation of the SRAM configured in this manner using the operating load curve shown in FIG. The solid line is
Transistor M11. A negative resistance element made of M12,
The broken lines indicate the current-voltage characteristics of the negative resistance element consisting of the transistor M14°M2S, and have a stable point I at voltage V and voltage vH. Voltage VL is almost at ground potential, and at this time, transistor Mll and transistor M12 are on, while transistor M14 and transistor M15 are off. The voltage v1□ is almost at the power supply potential, and at this time, the transistors M14 and M2S are both on, while the transistors M11°1 and M12 are both off. In such a circuit, the two sets of negative resistance elements are turned on and off in a complementary manner, so the data retention current is almost zero.

Furthermore, in the SRAM circuit of this embodiment, -
Since the negative resistance elements of the set are on, the output impedance is small. Therefore, even if the bit line terminal 13 has a large capacitance, it can be quickly charged and discharged.
No errors occur during read operations.

As described above, according to this embodiment, two negative resistance elements are used.
By connecting them in series, they can be turned on and off in a complementary manner to reduce the data retention current to almost zero, and prevent malfunctions during reading.

Further, another embodiment of the present invention will be described with reference to FIG. FIG. 3 is a circuit diagram of an SRAM using a floating gate type nonvolatile field effect transistor.

In Figure 3, M31 is an N-channel depletion type field effect transistor, MB2゜M2S is a P-channel depletion type field effect transistor, M33 is a pass transistor, 31 is a power supply terminal, 32 is a ground terminal, 33 is a bit line terminal, and 34 is a word line terminal. Shows wire terminals. M34 is an N-channel floating gate field effect transistor having a tunneling terminal 35. Transistor M31
The sources of and MB2 are commonly connected, and the gate of one and the drain of the other are connected to each other to form a negative resistance element. Similarly, the transistor M34°M2S is also connected with the same connection as the negative resistance element. and transistor M31. A negative resistance element M32 and a transistor M34. The circuit element M35 is connected in series by connecting the drains of the transistor M31 and the transistor M35, and the power terminal 31 is connected to the drain of the transistor M34, and the ground terminal 32 is connected to the drain of the transistor M32. The drain of the pass transistor M33 is connected to the connecting portion of the drains of the transistor M31 and the transistor M35.

The operation of the SRAM configured in this manner will be explained using FIG. 4. This SRAM performs normal "read/write" operations when the power is turned on, "store" operations that make data non-volatile just before the power is turned off, and "recall" operations that restore data immediately after the power is turned on.
It has three operating modes.

First, the "read/write" operations of this embodiment will be described.

When electrons are sufficiently extracted from the floating gate of transistor M34, transistor M34 is of a depletion type. At this time, the circuit element consisting of transistor M34 and transistor M35 exhibits negative resistance characteristics. Therefore, in this embodiment, two negative resistance elements are connected in series and a pass transistor M33 is provided.
As shown in Figure a, it functions similarly to the SRAM shown in Figure 1 according to the same operating load curve as the previous embodiment.

Next, the "store" operation will be described. In this example, S
When the RAM is on, a potential of 5V is applied to the power supply terminal 31. In this state, immediately before turning off the power supply terminal 31, first turn off the word line terminal 34 as shown in FIG.
V, and then apply a -10V pulse to the tunneling terminal 35 for about 10m5. When the held data is an "H" level voltage ■□, a voltage of approximately 15V is applied between the gate of the transistor M34 and the tunneling terminal 357.

Electrons are injected into the floating gate and transistor M34 becomes enhancement type and non-conductive. Conversely, the retained data is an “L” level voltage■.

At this time, only a voltage of about 10 V is applied between the gate of the transistor M34 and the tunneling terminal 35, so electron tunneling does not occur and the transistor M34 remains in the depletion type.

As mentioned above, the retained data “H” immediately before powering off
Depending on the state of the “L” level, the transistor M3
By changing 4 into an enhancement type and a depletion type, the state immediately before the power is turned off can be stored in the circuit element.

Next, in the "recall" operation, as shown in FIG.
to the “H” level voltage vH, and the word line terminal 34
An "H" level signal is added to the "H" level signal to perform "H" level writing. If the transistor M34 is a depletion type, the "H" level signal at the word line terminal 34 turns on the circuit elements having negative resistance characteristics, such as the transistors M34 and M2S, and holds "H" level data.

On the other hand, if transistor M34 is an enhancement type,
At this time, the transistor M34 remains off, and the negative resistance element formed by the transistors M31 and MB2 is turned on, and in this state, writing from the bit line terminal 33 is not possible.
L” level data is held.

Next, in order to make the transistor M34 a depletion type, a 15V pulse is applied to the tunneling terminal 35 for about 10I.
Apply for IIs. When the transistor M34 is of the enhancement type, its gate is at the L'' level, so the potential difference between the gate and the tunneling terminal 35 is 15V, and the electrons from the floating gate are extracted.As a result, the transistor M34 becomes the depletion type. It remains at “L” level. Also, the transistor M
34 is depression type, the circuit state is “H”.
” level, so connect the gate and tunneling terminal 3.
The potential difference between M34 and M34 is only about 10 V, so tunneling does not occur and the threshold of transistor M34 does not drop too much.

As described above, the "recall" operation reproduces the inverted level of the retained data immediately before the power was turned off. In order to restore such inverted data to its original state, a "store" operation and a "recall" operation are performed again.

Thus, according to another embodiment of the present invention, a non-volatile SRA
In this case, it is possible to realize a highly integrated nonvolatile SRAM that can be configured with five elements.

Effects of the Invention In the memory circuit of the present invention, two
By turning two circuit elements on and off in a complementary manner,
The data holding current can be reduced to zero, and the output impedance is small, so there is no malfunction when reading data.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of one embodiment of the present invention, FIG. 2 is an explanatory diagram of the operation of the same embodiment, FIG. 3 is a circuit diagram of another embodiment, and FIG. 4 is an explanatory diagram of the operation of the same embodiment. Figure 5 is a conventional memory circuit diagram.
FIG. 6 is an explanatory diagram of the conventional operation. Mll...N-channel depletion type field effect transistor, M12...P channel depletion type field effect transistor, M2S...
...Pass transistor, M14...N-channel depletion type field effect transistor, M2S...
...P-channel depletion type field effect transistor, 11...Power terminal, 12...
Ground terminal, 13...Bit line terminal, 14...
...Word line terminal. Name of agent: Patent attorney Akira Okaji et al.

Claims (2)

[Claims] (1) Two circuit elements are connected in series, with the sources of both field-effect transistors having channel regions of opposite conductivity connected in common, and the gate of one connected to the drain of the other, and the connected portion A memory circuit that connects pass transistors. (2) The memory circuit according to claim 1, wherein a nonvolatile transistor having a tunneling electrode is used as the field effect transistor.