JPS5472640A - Semiconductor memory device - Google Patents

Semiconductor memory device

Info

Publication number
JPS5472640A
JPS5472640A JP14020577A JP14020577A JPS5472640A JP S5472640 A JPS5472640 A JP S5472640A JP 14020577 A JP14020577 A JP 14020577A JP 14020577 A JP14020577 A JP 14020577A JP S5472640 A JPS5472640 A JP S5472640A
Authority
JP
Japan
Prior art keywords
point
stable
memory
curves
power consumption
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP14020577A
Other languages
Japanese (ja)
Other versions
JPS5716437B2 (en
Inventor
Tetsuya Iizuka
Fujio Masuoka
Yukimasa Uchida
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP14020577A priority Critical patent/JPS5472640A/en
Publication of JPS5472640A publication Critical patent/JPS5472640A/en
Publication of JPS5716437B2 publication Critical patent/JPS5716437B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/36—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using diodes, e.g. as threshold elements, i.e. diodes assuming a stable ON-stage when driven above their threshold (S- or N-characteristic)
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Static Random-Access Memory (AREA)
  • Semiconductor Memories (AREA)

Abstract

PURPOSE:To intent high density integration and low power consumption by using a pair of CMOS transistors. CONSTITUTION:The voltage dependence of current flowing CMOS transistors Tr1 and Tr2 is shwon at A2 point respectively as curves I11 and I12; in the intersecting points of both curves, a2 and b2 are stable points and C2 is unstable poihnt. Memory information is stored in both a2 and b2 and ''1'' or ''0'' is decided according to stable point a2 or b2. The power consumption of this memory cell is almost 0 at both stable ponts of a2 in the Vss side and b2 in the VDD side. Namely, in the memory holding status of Tr 1 and Tr 2, either one of transistors is fully kept to be OFF. In the memory holding atatus, MOSTr for transfer gate T4 is usually shut but, in case of writing, word line WL makes Tr T4 turn ON and bit line BL makes the status of A2 point transit between a2 and b2 by applying or drawing current compulsorily. In case of reading, Tr T4 is turned ON and voltage of A2 point is detected through BL.
JP14020577A 1977-11-22 1977-11-22 Semiconductor memory device Granted JPS5472640A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14020577A JPS5472640A (en) 1977-11-22 1977-11-22 Semiconductor memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14020577A JPS5472640A (en) 1977-11-22 1977-11-22 Semiconductor memory device

Publications (2)

Publication Number Publication Date
JPS5472640A true JPS5472640A (en) 1979-06-11
JPS5716437B2 JPS5716437B2 (en) 1982-04-05

Family

ID=15263353

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14020577A Granted JPS5472640A (en) 1977-11-22 1977-11-22 Semiconductor memory device

Country Status (1)

Country Link
JP (1) JPS5472640A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4547790A (en) * 1980-05-20 1985-10-15 Tokyo Shibaura Denki Kabushiki Kaisha Semiconductor device having contacting but electrically isolated regions of opposite conductivity types
JPH04111298A (en) * 1990-08-30 1992-04-13 Matsushita Electron Corp Memory circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4547790A (en) * 1980-05-20 1985-10-15 Tokyo Shibaura Denki Kabushiki Kaisha Semiconductor device having contacting but electrically isolated regions of opposite conductivity types
JPH04111298A (en) * 1990-08-30 1992-04-13 Matsushita Electron Corp Memory circuit

Also Published As

Publication number Publication date
JPS5716437B2 (en) 1982-04-05

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