WO2022059378A1 - Non-volatile memory - Google Patents

Abstract

The present invention comprises: first and second transistors of which the gates are connected in common; a resistor having a first end and a second end, the first end being connected to a source of the first transistor; a lead voltage supply circuit configured so as to supply a lead voltage for turning on either the first or the second transistor between the gate of the first transistor and the second end of the resistor and between the gate and source of the second transistor; and a signal output circuit configured so as to output a signal associated with a first value or a second value on the basis of drain currents of the first and second transistors during a lead operation in which the lead voltage is supplied by the voltage supply circuit.

Description

Non-volatile memory

This disclosure relates to non-volatile memory.

There is a non-volatile memory that uses hot carrier injection into a transistor. This type of non-volatile memory includes first and second transistors (corresponding to m1 and m2 in FIG. 22) having the same characteristics in the initial state as memory elements, and hot carriers are provided only for one of the transistors. It is injected to deteriorate the characteristics. In the subsequent read operation, "0" data is stored or "1" data is stored based on the magnitude relationship of the drain current when a common gate voltage is supplied to the first and second transistors. Read if it is. For example, a state in which the drain current of the first transistor is smaller (a state in which the first transistor is deteriorated) corresponds to a state in which "0" data is stored, and the drain current of the second transistor is smaller. The state (the state in which the second transistor is deteriorated) corresponds to the state in which the data of "1" is stored.

However, in the above non-volatile memory, the stored data in the initial state is undefined. A non-volatile memory configured so that a larger drain current flows in either of the first and second transistors in the initial state so that the stored data in the initial state does not become undefined has also been proposed.

Japanese Unexamined Patent Publication No. 2011-103158

In order to reduce the size of the entire circuit, it is often required to reduce the size of the memory elements (first and second transistors), and as the size of the memory elements decreases, the characteristic mismatch between the memory elements increases. The characteristics of a plurality of transistors formed with the aim of aligning the characteristics may actually deviate significantly, and this deviation corresponds to a mismatch. Such a mismatch causes inconveniences such as hindering the storage and reading of correct data (this will be described in detail later). The development of non-volatile memory that is not easily affected by mismatches is expected.

The present disclosure aims to provide a non-volatile memory that is less susceptible to mismatches.

The non-volatile memory according to the present disclosure has a first transistor, a second transistor having a gate commonly connected to the gate of the first transistor, and first and second ends, and is a source of the first transistor. With respect to the resistor to which the first end is connected, between the gate of the first transistor and the second end of the resistor, and between the gate and the source of the second transistor, the first and the above. In a lead voltage supply circuit configured to supply a lead voltage for turning on at least one of the second transistors, and in a read operation in which the lead voltage is supplied by the lead voltage supply circuit. , A signal output circuit configured to output a signal associated with the first value or a signal associated with the second value based on the drain currents of the first and second transistors. ..

The other non-volatile memory according to the present disclosure has a first transistor, a second transistor having a gate commonly connected to the gate of the first transistor, and first and second ends, and the first transistor. A lead voltage supply circuit configured to be able to supply a resistor to which the first end is connected to the source of the above and a read voltage for turning on at least one of the first and second transistors. In the read operation in which the lead voltage is supplied by the lead voltage supply circuit, the signal associated with the first value or the second value is supported based on the drain currents of the first and second transistors. It includes a signal output circuit configured to be able to output the attached signal.

According to the present disclosure, it is possible to provide a non-volatile memory that is not easily affected by a mismatch.

FIG. 1 is a block diagram of a storage circuit according to a standard embodiment of the present disclosure. FIG. 2 is a diagram showing a state in which a transistor (MOSFET) shown as one element in FIG. 1 is composed of a parallel circuit of a plurality of unit MOSFETs. FIG. 3 is a diagram showing the characteristics of each transistor of FIG. FIG. 4 is a block diagram of a storage circuit according to the first embodiment of the present disclosure. FIG. 5 is a diagram showing the characteristics of each transistor of FIG. FIG. 6 is a diagram showing a configuration of a storage circuit according to Example EX1_1 belonging to the first embodiment of the present disclosure. FIG. 7 is a diagram showing a configuration of a storage circuit according to Example EX1_1 belonging to the first embodiment of the present disclosure. FIG. 8 is a timing chart of the read operation before the program operation according to the embodiment EX1_1 belonging to the first embodiment of the present disclosure. FIG. 9 is a diagram showing a state (switch state) of the precharge period in the read operation according to the embodiment EX1_1 belonging to the first embodiment of the present disclosure. FIG. 10 is a diagram showing a state (switch state) of a lead period in a read operation according to Example EX1_1 belonging to the first embodiment of the present disclosure. FIG. 11 is a diagram showing a relationship between a plurality of signals according to the embodiment EX1_1 belonging to the first embodiment of the present disclosure. FIG. 12 is a timing chart of the read operation after the program operation according to the embodiment EX1_1 belonging to the first embodiment of the present disclosure. FIG. 13 is a diagram showing a state (switch state) of the program period according to the embodiment EX1_1 belonging to the first embodiment of the present disclosure. FIG. 14A is a diagram showing a configuration of a constant voltage source according to the second embodiment of the present disclosure. FIG. 14B is a diagram showing a configuration of a constant voltage source according to the second embodiment of the present disclosure. FIG. 15A is a diagram showing correspondence when the output voltage of a constant voltage source is required at a plurality of locations according to the second embodiment of the present disclosure. FIG. 15B is a diagram showing correspondence when the output voltage of a constant voltage source is required at a plurality of locations according to the second embodiment of the present disclosure. FIG. 16 is a diagram showing a circuit configuration of a constant voltage source according to Example EX2_1 belonging to the second embodiment of the present disclosure. FIG. 17 is a diagram showing the characteristics of the two transistors constituting the differential pair according to the embodiment EX2_1 belonging to the second embodiment of the present disclosure. FIG. 18 is a diagram showing a modified circuit configuration of a constant voltage source according to Example EX2_1 belonging to the second embodiment of the present disclosure. FIG. 19 is a diagram showing a circuit configuration of a constant current source according to Example EX2_2 belonging to the second embodiment of the present disclosure. FIG. 20 is a diagram showing a modification technique for the circuit configuration of FIG. 19 according to Example EX2_2 belonging to the second embodiment of the present disclosure. FIG. 21 is a diagram showing a circuit configuration of a comparator according to Example EX2_3 belonging to the second embodiment of the present disclosure. FIG. 22 is a diagram showing a main part of the non-volatile memory according to the reference configuration.

Hereinafter, an example of the embodiment of the present disclosure will be specifically described with reference to the drawings. In each of the referenced figures, the same parts are designated by the same reference numerals, and duplicate explanations regarding the same parts will be omitted in principle. In this specification, for the sake of simplification of description, by describing a symbol or a code that refers to an information, a signal, a physical quantity, an element or a part, etc., the information, a signal, a physical quantity, an element or a part corresponding to the symbol or the code is described. Etc. may be omitted or abbreviated. For example, the lead voltage supply circuit referred to by “20” described later (see FIG. 4) may be referred to as a lead voltage supply circuit 20 or may be abbreviated as circuit 20. They all refer to the same thing.

First, some terms used in the description of the embodiments of the present disclosure will be explained. The ground refers to a reference conductive portion having a reference potential of 0 V (zero volt) or refers to the potential of 0 V itself. The reference conductive portion is formed of a conductor such as metal. The potential of 0V may be referred to as a ground potential. In the embodiments of the present disclosure, the voltage shown without any particular reference represents the potential seen from ground. Level refers to the level of potential, where a high level has a higher potential than a low level for any signal or voltage of interest. For any signal or voltage of interest, a signal or voltage at a high level means that the signal or voltage level is at a high level, and a signal or voltage at a low level means that the signal or voltage level is at a low level. It means being at a low level. A level for a signal is sometimes referred to as a signal level, and a level for a voltage is sometimes referred to as a voltage level.

For any transistor configured as a FET (Field Effect Transistor) including MOSFETs, the on state refers to the state in which the drain and source of the transistor are conducting, and the off state means the drain and source of the transistor. Refers to a state in which the interval is non-conducting (blocked state). The same applies to transistors that are not classified as FETs. Unless otherwise specified, MOSFETs are understood to be enhancement-type MOSFETs. MOSFET is an abbreviation for "metal-oxide-semiconductor field-effect transistor".

The electrical characteristics of the MOSFET include the gate threshold voltage. For any transistor that is an N-channel type and enhancement type MOSFET, the gate potential of the transistor is higher than the source potential of the transistor, and the gate-source voltage of the transistor (gate potential seen from the source potential). When the magnitude is equal to or greater than the gate threshold voltage of the transistor, the transistor is turned on, and when not, the transistor is turned off. For any transistor that is a P-channel type and enhancement type MOSFET, the gate potential of the transistor is lower than the source potential of the transistor, and the gate-source voltage of the transistor (gate potential seen from the source potential). When the magnitude is equal to or greater than the gate threshold voltage of the transistor, the transistor is turned on, and when not, the transistor is turned off.

Any switch can be configured with one or more FETs (Field Effect Transistors), and when a switch is on, both ends of the switch conduct, while when a switch is off, the switch There is no conduction between both ends. Hereinafter, for any transistor or switch, the on state and the off state may be simply expressed as on and off.

For any signal that takes a high level or low level signal level, the period when the level of the signal becomes high level is called the high level period, and the period when the level of the signal becomes low level is called the low level period. The same is true for any voltage that has a high or low level voltage level.

<< Basic Embodiment >>
The basic embodiment of the present disclosure will be described. FIG. 1 is a configuration diagram showing a main part of a storage circuit 901 according to a basic embodiment. The storage circuit 901 is a non-volatile memory that stores 1-bit data, and includes a memory unit 910, a read voltage supply circuit 920, a signal output circuit 930, and a program circuit 940. The storage circuit 901 may be configured by a semiconductor integrated circuit.

The memory unit 910 is composed of memory elements 911 and 912, and stores "0" data or "1" data in the memory unit 910. Each of the memory elements 911 and 912 is a transistor. Therefore, the memory elements 911 and 912 are also referred to as transistors 911 and 912. Each of the transistors 911 and 912 is configured as an N-channel MOSFET. However, while the transistor 911 is formed by a single unit MOSFET, the transistor 912 is formed by a parallel circuit of n unit MOSFETs as shown in FIG. n is any integer greater than or equal to 2. The unit MOSFETs constituting the transistor 911 and the unit MOSFETs constituting the transistor 912 have the same structure, and have the same electrical characteristics (including the gate threshold voltage) before the program operation by the program circuit 940 is executed. ..

The gates of the transistors 911 and 912 are commonly connected to each other. Each source of transistors 911 and 912 is connected to ground. Each drain of the transistors 911 and 912 is connected to the signal output circuit 930.

In the storage circuit 901, a read operation for reading the data stored in the memory unit 910 and a program operation (write operation) for rewriting the data stored in the memory unit 910 from "0" to "1" can be executed.

The lead voltage supply circuit 920 is a circuit that functions effectively in the read operation, and in the read operation, the lead voltage for turning on at least one of the transistors 911 and 912 is applied to each gate of the transistors 911 and 912. Supply. The read voltage is at least higher than the gate threshold voltage of the transistor 911. The signal output circuit 930 outputs a signal corresponding to the value of the data stored in the memory unit 910 based on the magnitude relationship of the drain currents of the transistors 911 and 912 in the read operation.

The program operation is realized by the program circuit 940. In the program operation, the program circuit 940 deteriorates the electrical characteristics of the transistor 912 by injecting hot carriers into the transistor 912, and the deterioration causes the gate threshold voltage of the transistor 912 to increase (rise).

See FIG. In FIG. 3, the solid line waveform 962 _INI represents the gate-source voltage dependence of the drain current of the transistor 912 before the execution of the program operation (that is, in the initial state of the storage circuit 901), and the solid line waveform 962 _PRG is It represents the gate-source voltage dependence of the drain current of the transistor 912 after the execution of the program operation. The dashed line waveform 961 represents the gate-source voltage dependence of the drain current of the transistor 911. Since hot carriers are not injected into the transistor 911 during the program operation, the electrical characteristics of the transistor 911 do not change before and after the execution of the program operation.

Before executing the program operation, each unit MOSFET constituting the transistors 911 and 912 has the same electrical characteristics. Therefore, when a common voltage exceeding their gate threshold voltage is supplied to the gates of the transistors 911 and 912, the transistors The drain current of the 912 is larger than the drain current of the transistor 911. The state in which the drain current of the transistor 912 is larger than the drain current of the transistor 911 corresponds to the state in which the data of "0" is stored in the memory unit 910. Therefore, in the read operation, when the drain current of the transistor 912 is larger than the drain current of the transistor 911, the signal output circuit 930 outputs a signal corresponding to the data of “0” (for example, a low level signal). ..

By executing the program operation, hot carriers are injected into each unit MOSFET of the transistor 912, so that the gate threshold voltage of each unit MOSFET of the transistor 912 increases. This corresponds to an increase in the gate threshold voltage of the transistor 912. After executing the program operation, the program operation is executed so that the gate threshold voltage of the transistor 912 becomes sufficiently higher than the gate threshold voltage of the transistor 911. The gate threshold voltage of the transistor 912 after the execution of the program operation may be higher than the read voltage, and when the read operation is performed after the execution of the program operation, the drain current of the transistor 911 is larger than the drain current of the transistor 912. Become. The state in which the drain current of the transistor 911 is larger than the drain current of the transistor 912 corresponds to the state in which the data of "1" is stored in the memory unit 910. Therefore, in the read operation, when the drain current of the transistor 911 is larger than the drain current of the transistor 912, the signal output circuit 930 outputs a signal corresponding to the data of “1” (for example, a high level signal). ..

It is also possible to configure a non-volatile memory in which the stored data in the initial state is indefinite. However, when such a non-volatile memory is used, it is necessary to perform processing for dealing with the indefinite storage data in another peripheral circuit, which is inconvenient from the viewpoint of circuit scale. There is also. According to the storage circuit 901 of FIG. 1, the stored data can be fixed to "0" in the initial state, and the stored data can be set to "1" only when the program operation is executed.

However, in order to reduce the size of the entire circuit, it is often required to reduce the size of the memory elements (911, 912), and as the size of the memory element becomes smaller, the characteristic mismatch between the memory elements becomes larger. That is, each unit MOSFET is formed on the semiconductor substrate with the aim of making the electrical characteristics of the unit MOSFETs of the transistors 911 and 912 the same, but in reality, the electrical characteristics of each unit MOSFET vary. Occurs. This variation corresponds to a mismatch. Such a mismatch hinders the storage and reading of correct data. Alternatively, it is necessary to take measures such as considerably increasing the value of the above "n" in order to realize correct data storage and reading in consideration of the mismatch. In the following first embodiment, a storage circuit that is not easily affected by the mismatch will be described.

<< First Embodiment >>
The first embodiment of the present disclosure will be described. FIG. 4 is a configuration diagram showing a main part of the storage circuit 1 according to the first embodiment. The storage circuit 1 is a non-volatile memory that stores 1-bit data, and includes a memory unit 10, a read voltage supply circuit 20, a signal output circuit 30, and a program circuit 40, as well as a resistor R1. The storage circuit 1 may be configured by a semiconductor integrated circuit.

The memory unit 10 includes memory elements M1 and M2, and stores "0" data or "1" data in the memory unit 10. Each of the memory elements M1 and M2 is a transistor. Therefore, the memory elements M1 and M2 are also referred to as transistors M1 and M2 (first and second transistors). Each of the transistors M1 and M2 is configured as an N-channel MOSFET. The transistors M1 and M2 have the same structure as each other, and have the same electrical characteristics as each other before the program operation by the program circuit 40 is executed. Therefore, before the program operation by the program circuit 40 is executed, the transistors M1 and M2 have the same gate threshold voltage. Here, for a transistor, the structure is a concept including the size of the transistor, and therefore, for any plurality of transistors, the same structure means that the sizes of the plurality of transistors are also the same. means. However, with respect to the structure and electrical characteristics (gate threshold voltage, etc.) of any plurality of transistors, the same structure or electrical characteristics means that they are the same in design, and an error is actually obtained. (Ie, the same is understood to be a concept involving errors).

The gates of the transistors M1 and M2 are commonly connected to each other. The source of the transistor M1 is connected to ground via the resistor R1. That is, the source of the transistor M1 is connected to one end of the resistor R1 and the other end of the resistor R1 is connected to the ground. On the other hand, the source of the transistor M2 is directly connected to the ground. Each drain of the transistors M1 and M2 is connected to the signal output circuit 30. The drain current of the transistor M1 is referred to by the symbol “ _ID1 ”, and the drain current of the transistor M2 is referred to by the symbol “ _ID2 ”.

In the storage circuit 1, a read operation for reading the data stored in the memory unit 10 and a program operation (write operation) for rewriting the data stored in the memory unit 10 from "0" to "1" can be executed.

The lead voltage supply circuit 20 is a circuit that functions effectively in the read operation, and in the read operation, the lead voltage for turning on at least one of the transistors M1 and M2 is applied to each gate of the transistors M1 and M2. Supply. However, since the source of the transistor M1 is connected via the resistor R1, in the read operation, a voltage obtained by subtracting the voltage drop of the resistor R1 from the read voltage is applied between the gate and the source of the transistor M1 (that is,). A read voltage is applied between both ends of the resistor R1 and one end connected to the ground and the gate of the transistor M1). On the other hand, in the read operation, the read voltage is directly applied between the gate and the source of the transistor M2. The read voltage is at least higher than the gate threshold voltage of the transistor M1. Therefore, in the read operation, at least the transistor M1 is turned on, and the drain current _ID1 can flow. The signal output circuit 30 outputs a signal D _OUT corresponding to the value of the data stored in the memory unit 10 based on the magnitude relationship of the drain currents of the transistors M1 and M2 in the read operation.

The program operation is realized by the program circuit 40. In the program operation, the program circuit 40 deteriorates the electrical characteristics of the transistor M2 by injecting hot carriers into the transistor M2, and the deterioration causes the gate threshold voltage of the transistor M2 to increase (rise).

See FIG. In FIG. 5, the solid line waveform 800M2 _INI represents the gate-source voltage dependence of the drain current of the transistor M2 before the execution of the program operation (that is, in the initial state of the storage circuit 1), and the solid line waveform 800M2 _PRG is It represents the gate-source voltage dependence of the drain current of the transistor M2 after the execution of the program operation. The dashed line waveform 800M1 represents the gate-source voltage dependence of the drain current of the transistor M1. Since hot carriers are not injected into the transistor M1 during the program operation, the electrical characteristics of the transistor M1 do not change before and after the execution of the program operation. Ideally, the waveforms 800M1 and 800M2 _INI will overlap each other. In FIG. 5, for convenience of illustration, the waveforms 800M1 and 800M2 _INI are shown with a slight shift.

Since the transistors M1 and M2 have the same electrical characteristics before the execution of the program operation, when a common voltage exceeding their gate threshold voltage is supplied to each gate of the transistors M1 and M2, the drain current I of the transistor M2 _D2 is larger than the drain current I _D1 of the transistor M1. The state in which the drain current I _D2 is larger than the drain current I _D1 corresponds to the state in which the data of "0" is stored in the memory unit 10. Therefore, in the read operation, when the drain current I _D2 is larger than the drain current I _D1 , the signal output circuit 30 outputs a signal D _OUT (for example, a low level signal D _OUT ) corresponding to the data of “0”. do. In the read operation before the execution of the program operation, the drain current I _D2 is larger than the drain current I _D1 .

By injecting hot carriers into the transistor M2 by executing the program operation, the gate threshold voltage of the transistor M2 increases. After executing the program operation, the program operation is executed so that the gate threshold voltage of the transistor M2 becomes sufficiently higher than the gate threshold voltage of the transistor M1. The gate threshold voltage of the transistor M2 after executing the program operation may be higher than the read voltage. When the read operation is performed after the execution of the program operation, the drain current _ID1 becomes larger than the drain current _ID2 . The state in which the drain current I _D1 is larger than the drain current I _D2 corresponds to the state in which the data of "1" is stored in the memory unit 10. Therefore, in the read operation, when the drain current I _D1 is larger than the drain current I _D2 , the signal output circuit 30 outputs a signal D _OUT (for example, a high level signal D _OUT ) corresponding to the data of “1”. do.

By adopting the circuit configuration of FIG. 4, it is possible to configure a storage circuit that is not easily affected by the above mismatch.

The connection relationship of FIG. 4 and the connection relationship described above for the circuit of FIG. 4 represent the connection relationship when the read operation is executed, and the source and drain of the transistor M2 may be exchanged when the program operation is executed. (However, this is not mandatory). That is, of the first and second electrodes of the transistor M2, the electrode on the high potential side functions as a drain and the electrode on the low potential side functions as a source, but the first electrode and the second electrode of the transistor M2 have. Of the electrodes, each circuit is connected using a switch or the like (not shown in FIG. 4) so that the electrode connected to the ground in the lead operation (the electrode that functions as the source) functions as the drain when the program operation is executed. The relationship may be changed (detailed circuit examples to achieve this will be described later).

The first embodiment includes the following examples EX1_1 to EX1_4. The above-mentioned matters in the first embodiment are applied to the following Examples EX1_1 to EX1_4 unless otherwise specified and without contradiction, and in each embodiment, the matters inconsistent with the above-mentioned matters in the first embodiment are described. The description in each embodiment may be prioritized. Further, as long as there is no contradiction, the matters described in any of the examples EX1_1 to EX1_4 can be applied to any other embodiment (that is, any two or more implementations in the plurality of examples). It is also possible to combine examples).

[Example EX1_1]
Example EX1_1 will be described. FIG. 6 shows the configuration of the storage circuit 1A according to the embodiment EX1_1. The storage circuit 1A is an example of the storage circuit 1 of FIG. The storage circuit 1A includes transistors M1 to M4, M11 to M14, M21 and M22, switches SW1 to SW12, resistors R1, R3 and R4, capacitors C1 and C2, inverters INV1 to INV5, and a constant current circuit CC _IG . And CC _OTPG , and a control circuit 60. The storage circuit 1A may be configured by a semiconductor integrated circuit.

Transistors M1 to M4 and M11 to M14 are N-channel MOSFETs, and transistors M21 and M22 are P-channel MOSFETs. The signals XRST and PRG are output from the control circuit 60. Signals XRST and PRG are binarized signals that take low or high level signal levels. The on / off of the switches SW1 to SW12 is controlled based on the signals XRST and PRG, and FIG. 6 shows the situation when it is assumed that all the switches are in the off state (the same applies to FIG. 7 described later).

The connection relationship of each component of the storage circuit 1A will be described. A positive power supply voltage VDD is applied to the power supply line LN _VDD . The power supply voltage VDD has a predetermined positive DC voltage value. The ground line LN _GND has a ground potential of 0 V.

Each source of the transistors M21 and M22 and one end of each of the switches SW3 and SW4 are connected to the power supply line LN _VDD . The other end of the switch SW3 is connected to the gate of the transistor M21, and the other end of the switch SW4 is connected to the gate of the transistor M22. The wiring connected to the gate of the transistor M21 is referred to as a line LN2, and the voltage applied to the line LN2 is referred to as a voltage V2. The wiring connected to the gate of the transistor M22 is referred to as a line LN1, and the voltage applied to the line LN1 is referred to as a voltage V1. The drain of the transistor M21 is connected to the line LN1, and the drain of the transistor M22 is connected to the line LN2.

The input terminal of the inverter INV1 is connected to the line LN1. The output terminal of the inverter INV1 is connected to the input terminal of the inverter INV2. The output terminal of the inverter INV2 is connected to the input terminal of the inverter INV3 and is also connected to the line LN1 via the capacitor C1. The input terminal of the inverter INV4 is connected to the line LN2. The output terminal of the inverter INV4 is connected to the input terminal of the inverter INV5. The output terminal of the inverter INV5 is connected to the line LN2 via the capacitor C2.

One end of the switch SW5 is connected to the line LN1, and the other end of the switch SW5 is connected to one end of the switch SW1. The other end of the switch SW1 is connected to the ground line LN _GND . One end of the switch SW6 is connected to the line LN2, and the other end of the switch SW6 is connected to one end of the switch SW2. The other end of the switch SW2 is connected to the ground line LN _GND .

Each gate of the transistors M11 to M14 is commonly connected to the gate line LN _IG . The voltage applied to the gate line LN _IG is called the gate voltage V _IG . Each gate of the transistors M1 to M3 is commonly connected to the gate line LN _OTPG . The voltage applied to the gate line LN _OTPG is referred to as the gate voltage V _OTPG .

The drain of the transistor M11 is connected to the line LN1, and the source of the transistor M11 is connected to the drain of the transistor M1. The source of the transistor M1 is connected to the ground line LN _GND via the resistor R1. That is, the source of the transistor M1 is connected to one end of the resistor R1 and the other end of the resistor R1 is connected to the ground line LN _GND .

The drain of the transistor M12 is connected to the line LN2, and the source of the transistor M12 is connected to the electrode E1 of the transistor M2. A switch SW9 is inserted in series between the electrode E1 of the transistor M2 and the ground line LN _GND . A switch SW10 is inserted in series between the electrode E2 of the transistor M2 and the ground line LN _GND . Further, the switch SW11 is inserted in series between the electrode E2 of the transistor M2 and the power supply line LN _VDD . In the transistor M2, among the electrodes E1 and E2, the electrode on the high potential side functions as a drain and the electrode on the low potential side functions as a source. As will be clarified from the explanation described later, in the read operation, the switches SW9, SW10, and SW11 are turned off, on, and off, respectively, so that the electrode E1 functions as a drain, and in the program operation, the switch SW9, When SW10 and SW11 are turned on, off, and on, respectively, the electrode E2 functions as a drain.

The switch SW12 is inserted in series between the power line LN _VDD and the gate line LN _OTPG , and the switch SW7 is inserted in series between the gate line LN _OTPG and the ground line LN _GND . The drain of the transistor M13 is connected to the gate line LN _OTPG , and the source of the transistor M13 is connected to the drain of the transistor M3. The source of the transistor M3 is connected to the ground line LN _GND via the resistor R3.

A switch SW8 is inserted in series between the gate line LN _IG and the ground line LN _GND . The drain of the transistor M14 is connected to the gate line LN _IG , and the source of the transistor M14 is connected to the drain of the transistor M4. The gate and drain of the transistor M4 are connected to each other. The source of the transistor M4 is connected to the ground line LN _GND via the resistor R4.

The constant current circuit CC _IG is connected to the gate line LN _IG . The constant current circuit CC _IG generates a constant current IG based on the power supply voltage VDD and supplies the constant current IG to the gate line LN _IG during a necessary period including a period in which the read operation is performed. The constant current circuit CC _OTPG is connected to the gate line LN _OTPG . The constant current circuit CC _OTPG generates a constant current OTPG based on the power supply voltage VDD and supplies the constant current OTPG to the gate line LN _OTPG in a necessary period including a period in which the read operation is performed.

Inverter An inverter, which is any of INV1 to INV5, outputs an inverted signal of an input signal to its own input terminal from its own output terminal. Specifically, when the input voltage to its input terminal is less than a predetermined threshold voltage, the inverter outputs a high-level signal sufficiently higher than the threshold voltage from its output terminal to its own input terminal. When the input voltage of is equal to or higher than a predetermined threshold voltage, a low-level signal sufficiently lower than the threshold voltage is output from its own output terminal. The inverters INV1 to INV5 are driven based on the power supply voltage VDD, and the threshold voltage of each inverter is approximately half of the power supply voltage VDD. However, a hysteresis characteristic may be added to the threshold voltage of each inverter. The output signal of the inverter INV3 is the output signal D _OUT of the storage circuit 1A. A signal corresponding to the value of the data stored in the memory unit 10 composed of the transistors M1 and M2 is output as an output signal D _OUT through a read operation.

The control terminal of the switch SW5 is connected to the output terminal of the inverter INV1. The switch SW5 is turned on and off, respectively, when the output signal of the inverter INV1 is high level and low level. The control terminal of the switch SW6 is connected to the output terminal of the inverter INV4. The switch SW6 is turned on and off, respectively, when the output signal of the inverter INV4 is high level and low level.

As described above, the transistors M1 and M2 have the same structure as each other, and have the same electrical characteristics (including the gate threshold voltage) before the execution of the program operation. Further, here, it is assumed that the configuration shown below is adopted in the storage circuit 1A (see FIG. 7). That is, the N-channel type first to fifth unit MOSFETs are formed in the storage circuit 1A, and the transistors M1, M2, and M3 are formed by the first, second, and third unit MOSFETs, respectively, while the fourth unit is formed. And the transistor M4 is formed by the parallel circuit of the fifth unit MOSFET. The first to fifth unit MOSFETs have the same structure as each other and have the same electrical characteristics (including the gate threshold voltage) before the execution of the program operation. In addition, the resistance values of the resistors R1 and R3 are set to be the same as each other, and the resistance value of the resistor R4 is set to half the resistance value of the resistor R1. The constant current IG is set to twice the constant current OTPG. Further, the transistors M1 to M14 may be transistors having the same structure and electrical characteristics (including a gate threshold voltage).

--- Read operation before program operation RD _INI ---
Hereinafter, for convenience of description, the read operation executed before the execution of the program operation may be referred to as a read operation RD _INI , and the read operation executed after the execution of the program operation may be referred to as a read operation RD _PRG . When simply referred to as a read operation, it refers to a read operation before or after the execution of the program operation.

FIG. 8 is a timing chart of the read operation RD _INI . In the read operation, the low level period of the signal XRST is referred to as a precharge period, and the period in which both the switches SW5 and SW6 are in the off state among the high level periods of the signal XRST is referred to as a read period. The read operation is realized in the read period after the precharge period has passed. The signal PRG is maintained at a low level during the period when no program operation is performed (including the precharge period and the read period). Assuming that the signal PRG is at the low level, the signal XRST is switched from the low level to the high level to transition from the precharge period to the read period, and the signal corresponding to the data stored in the memory unit 10 is generated. After the read period, it is output as an output signal D _OUT .

During the precharge period, based on the low level signals XRST and PRG, as shown in FIG. 9, switches SW1 and SW2 are turned off, while switches SW3, SW4, SW7 and SW8 are turned on, and a constant current circuit. The constant current generation and output operations by CC _IG and CC _OTPG are stopped. Further, during the low level period of the signal PRG, the switches SW9, SW11 and SW12 are turned off and the switch SW10 is turned on based on the low level signal PRG. In the period in which the program operation is not performed (including the precharge period and the read period), the electrode E1 functions as a drain and the electrode E2 functions as a source in the transistor M2.

In FIG. 8, the broken line waveform INI _V1 represents the waveform of the voltage V1 in the lead operation RD _INI , and the solid line waveform INI _V2 represents the waveform of the voltage V2 in the lead operation RD _INI . From the precharge period to the first half of the read period, the waveforms INI _V1 and INI _V2 overlap each other. Since the voltages _{VIG and VOTPG are} 0V during the precharge period, the transistors M1 to M4 and M11 to M14 are all in the off state. Further, during the precharge period, positive charges are supplied to the lines LN1 and LN2 through the switches SW4 and SW3, and the voltages V1 and V2 reach the level of the power supply voltage VDD. Therefore, during the precharge period, the output signals of the inverters INV1 and INV4 are at a low level, and as a result, the switches SW5 and SW6 are off.

The signal XRST switches from the low level to the high level to transition from the precharge period to the read period. In the read period, based on the high level signal XRST and the low level signal PRG, the switches SW1 and SW2 are turned on while the switches SW3, SW4, SW7 and SW8 are turned off as shown in FIG. Further, during the read period, constant current generation and output operation are performed by the constant current circuits CC _IG and CC _OTPG . As a result, during the read period, the gate voltage V _IG rises due to the constant current I _IG , and the gate voltage V _OTPG rises due to the constant current I _OTPG . At this time, by making the constant current I _IG larger than the constant current I _OTPG , the gate voltage V _IG rises faster than the gate voltage _VOTPG (for example, by setting “I _IG = I _OTPG × 2”, the gate voltage V _IG rises twice as fast as the gate voltage _VOTPG ), and the transistors M11-M14 can be left on before the gate voltage _VOTPG reaches the gate threshold voltage of the transistor M1 or M2. .. Note that FIG. 8 shows the waveform of one of the gate voltages _{VIG and VTPG as} a representative (the same applies to FIG. 12 described later).

During the read period, the transistors M4 and M11 to M14 are turned on as the gate voltages _{VIG and VTPG increase} , and the drain current flows through the transistors M1 to M3. During the read period, the drain current flowing through the transistor M1 is referred to by the symbol “ _ID1 ”, and the drain current flowing through the transistor M2 is referred to by the symbol “ _ID2 ” (see FIG. 10). Further, the gate voltage _VTPG in the read period corresponds to the above-mentioned read voltage. The gate voltage _VOTPG (lead voltage) minus the voltage drop of the resistor R1 is applied between the gate and source of the transistor M1, while the gate voltage _VOTPG (lead voltage) is applied between the gate and source of the transistor M2. It is added as it is (however, the on-resistance of the switch SW10 is ignored because it is sufficiently small). Therefore, in the read period before the program operation is executed, the drain current I _D2 becomes larger than the drain current I _D1 , and as a result, the voltage V2 drops faster than the voltage V1. Further, since the drain current flows through the transistor M21 in the process of lowering the voltage V2, the lowering of the voltage V1 stops at the stage where the voltage V2 drops to some extent, and the voltage V1 rises to the level of the power supply voltage VDD.

When the voltage V2 falls below the threshold voltage of the inverter INV4 in the state of "V1> V2", the output signal of the inverter INV4 is switched from the low level to the high level, and the switch SW6 is switched from the off state to the on state. As shown in FIG. 11, the signal END is a logical sum signal of the output signal of the inverter INV1 and the output signal of the inverter INV4. Therefore, when at least one of the output signals of the inverters INV1 and INV4 becomes a high level, the signal END Will be at a high level. The signal END may be understood as an internal signal generated in the control circuit 60.

In response to the signal END becoming high level, the control circuit 60 stops the generation and output operation of the constant current by the constant current circuits CC _IG and CC _OTPG , and switches the switches SW7 and SW8 from off to on. As a result, the gate voltages _{VIG and VOTPG drop} to 0V.

The signal D _OUT after the signal END becomes high level in the read operation is particularly referred to as a read confirmation signal D _OUT . The read confirmation signal D _OUT represents the value of the data stored in the memory unit 10 (the value of the data read from the memory unit 10), and the low level of the read confirmation signal D _OUT indicates that the data is at a low level. The value is "0", and the high level of the read confirmation signal D _OUT means that the value of the data is "1". In the read operation RD _INI , since the output signal of the inverter INV1 is maintained at a low level, the read confirmation signal D _OUT also becomes a low level, and “0” data (that is, initial value data) is read out. Since the read confirmation signal D _OUT representing the data of “0” continues to be output after the signal END becomes high level in the read operation RD _INI , it is not necessary to provide a latch circuit in the subsequent stage, and the read confirmation signal D _OUT is required. The read confirmation signal D _OUT can be directly supplied to the circuit (for example, a trimming switch that is turned on / off according to the stored data of the memory unit 10).

--- Read operation after program operation RD _PRG ---
FIG. 12 is a timing chart of the read operation RD _PRG (that is, the read operation performed after the execution of the program operation). In FIG. 12, the broken line waveform PRG _V1 represents the waveform of the voltage V1 in the lead operation RD _PRG , and the solid line waveform PRG _V2 represents the waveform of the voltage V2 in the lead operation RD _PRG . From the precharge period to the first half of the read period, the waveforms PRG _V1 and PRG _V2 overlap each other.

There is no difference in the content of the read operation including the state control of each switch during the precharge period and the read period between before the execution of the program operation and after the execution of the program operation. However, due to the program operation executed before the read operation RD _PRG , only the transistor M2 is deteriorated among the transistors M1 and M2, and only the gate threshold voltage of the transistor M2 is greatly increased. Therefore, during the read period in the read operation RD _PRG , the drain current I _D1 becomes larger than the drain current I _D2 , and as a result, the voltage V1 drops faster than the voltage V2. Further, since the drain current flows through the transistor M22 in the process of lowering the voltage V1, the lowering of the voltage V2 stops at the stage where the voltage V1 drops to some extent, and the voltage V2 rises to the level of the power supply voltage VDD.

When the voltage V1 falls below the threshold voltage of the inverter INV1 in the state of "V1 <V2", the output signal of the inverter INV1 is switched from the low level to the high level, and the switch SW5 is switched from the off state to the on state. Further, when the output signal of the inverter INV1 is switched from the low level to the high level, the signal END is also switched from the low level to the high level (see FIG. 11). In response to the signal END becoming high level, the control circuit 60 stops the generation and output operation of the constant current by the constant current circuits CC _IG and CC _OTPG , and switches the switches SW7 and SW8 from off to on. As a result, the gate voltages _{VIG and VOTPG drop} to 0V.

The signal D _OUT after the signal END becomes high level in the read operation is particularly referred to as a read confirmation signal D _OUT as described above. In the read operation RD _PRG , since the output signal of the inverter INV1 becomes high level due to the decrease of the voltage V1, the read confirmation signal D _OUT becomes high level and represents the data of “1”. Since the read confirmation signal D _OUT representing the data of “1” continues to be output after the signal END becomes high level in the read operation RD _PRG , it is not necessary to provide a latch circuit in the subsequent stage, and the read confirmation signal D _OUT is required. The read confirmation signal D _OUT can be directly supplied to the circuit (for example, a trimming switch that is turned on / off according to the stored data of the memory unit 10).

--- Program operation ---
As described above, the state in which the drain current ID 2 is larger than the _drain current ID ₁ in the read operation (read period) corresponds to the state in which the data of “0” is stored in the memory unit 10, and FIG. In the read operation RD _INI of, since the drain current I _D2 is larger than the drain current I _D1 , the read confirmation signal D _OUT (here, the low level signal D _OUT ) corresponding to the data of “0” is output. .. On the contrary, the state in which the drain current I _D1 is larger than the drain current I _D2 in the read operation (read period) corresponds to the state in which the data of "1" is stored in the memory unit 10, and is corresponding to the state in which the data of "1" is stored in FIG. In the read operation RD _PRG , since the drain current I _D1 is larger than the drain current I _D2 , the read confirmation signal D _OUT (here, the high level signal D _OUT ) corresponding to the data of “1” is output.

In the storage circuit 1A of FIG. 6, the program operation that causes the change from the read operation RD _INI of FIG. 8 to the read operation RD _PRG of FIG. 12 is realized as follows.

FIG. 13 shows the state of each switch in the storage circuit 1A during the period in which the program operation is executed (hereinafter referred to as the program period). During the program period, the signal XRST is set to low level and the signal PRG is set to high level, and the switches SW1, SW2, SW7 and SW10 are turned off based on those signals XRST and PRG, while the switches SW3, SW4, SW8 and SW9 are turned off. , SW11 and SW12 are turned on, and the constant current generation and output operation by the constant current circuits CC _IG and CC _OTPG is stopped. As a result, the power supply voltage VDD is applied to the electrode E2 of the transistor M2 and the gate, while the potential of the electrode E1 of the transistor M2 becomes 0V. Further, when the switch SW8 is turned on, all the transistors M11 to M14 are turned off.

During the program period, the electrode E2 functions as a drain of the transistor M2 and the electrode E1 functions as a source of the transistor M2, and a current flows from the electrode E2 toward the electrode E1. In the process of this current flowing, hot carriers are injected into the transistor M2, the characteristics of the transistor M2 deteriorate, and the gate threshold voltage of the transistor M2 increases. After maintaining the state of FIG. 13 for a time sufficient to sufficiently increase the gate threshold voltage of the transistor M2, the program operation is completed by switching the signal PRG from the high level to the low level.

--- Correspondence between storage circuits 1 and 1A ---
The description of the correspondence between the storage circuit 1 of FIG. 4 and the storage circuit 1A of FIG. 6 will be supplemented. First, it is common between the storage circuits 1 and 1A that the memory unit 10 is composed of the transistors M1 and M2.

The read voltage supply circuit 20 of FIG. 4 is mainly composed of a transistor M3, a resistor R3, a constant current circuit CC _OTPG , and a switch SW7 in the storage circuit 1A of FIG. 6, and the transistor M13 is also included in the components of the circuit 20. It is also possible to understand that. It can be said that the storage circuit 1A of FIG. 6 is provided with a drain current control circuit for permitting or cutting off the supply of drain currents ( _ID1 and _ID2 ) to the transistors M1 and M2, and the drain current control circuit is said to be provided. , M11 to M14 and M4, a resistor R4, a constant current circuit CC _IG , and a switch SW8.

The signal output circuit 30 of FIG. 4 is mainly composed of transistors M21 and M22, switches SW1 to SW6, inverters INV1 to INV5, and capacitors C1 and C2 in the storage circuit 1A of FIG. Depending on the size of the parasitic capacitance added to LN2, the capacitors C1 and C2 and the inverter INV5 may be omitted.

The program circuit 40 of FIG. 4 includes switches SW9 to SW12 in the storage circuit 1A of FIG. Since the power supply voltage VDD is naturally required for hot carrier injection, it can be understood that the power supply circuit (not shown) that generates and outputs the power supply voltage VDD is also included in the components of the program circuit 40. can. The same applies to the lead voltage supply circuit 20 and the signal output circuit 30.

The control circuit 60 of FIG. 6 is a circuit that controls the operation of the lead voltage supply circuit 20, the signal output circuit 30, and the program circuit 40 of FIG. 4 (furthermore, a circuit that controls the operation of the drain current control circuit described above). Can be understood as. Alternatively, it can be considered that the control circuit 60 is a circuit that is also used as the circuits 20, 30 and 40 for realizing the read operation and the program operation as each part of the circuits 20, 30 and 40. be.

In the storage circuits 1 and 1A, in the read operation, when “ _ID2 > _ID1 ”, the signal D _OUT (read confirmation signal D _OUT ) associated with the first value is output, and “ _ID2 <. When it is " _ID1 ", the signal D _OUT (read confirmation signal D _OUT ) associated with the second value is output. In the above operation example, the first value is "0" and the second value is "1", but as long as the first and second values are different, the first and second values are Optional. Further, the circuit configuration is modified so that the signal D _OUT associated with the first value becomes a high-level signal and the signal D _OUT associated with the second value becomes a low-level signal. You may.

[Example EX1_2]
Example EX1_2 will be described. The storage circuit 1 or 1A shown in FIG. 4 or FIG. 6 is a first non-volatile memory that stores data for one bit, but a plurality of storage circuits 1 or 1A are provided as a unit cell to store data for a plurality of bits. A second non-volatile memory for storage can also be configured.

Alternatively, a unit cell may be configured by a set of the memory unit 10 and the signal output circuit 30, and a third non-volatile memory provided with a plurality of the unit cells may be configured. In the third non-volatile memory, the read The voltage supply circuit 20 and the program circuit 40 are shared among a plurality of unit cells. That is, for example, in the third non-volatile memory, when the read operation is performed by two or more unit cells included in the plurality of unit cells, the read voltage supply circuit 20 is a transistor in each of the two or more unit cells. A lead voltage may be supplied to each of the gates of M1 and M2. Similarly, for example, in a third non-volatile memory, when a program operation is performed on two or more unit cells included in the plurality of unit cells, the program circuit 40 is connected to the transistor M2 in each of the two or more unit cells. Hot carriers may be injected.

In any case, in the non-volatile memory according to the present disclosure, the number of bits of the stored data is arbitrary as long as it is 1 or more, and the memory unit 10 is provided for the number of bits of the stored data.

[Example EX1_3]
Example EX1_3 will be described. In Example EX1_1, a circuit configuration for generating a read voltage using a constant current is given. However, in the lead voltage supply circuit 20 of FIG. 4, a DC lead voltage is applied to each gate of the transistors M1 and M2 in the read operation. It may be a DC voltage source to be supplied.

[Example EX1_4]
Example EX1_4 will be described. The non-volatile memory according to the first embodiment (for example, any non-volatile memory mentioned in the above-mentioned Example EX1_2) can be incorporated into any circuit or device that realizes a predetermined functional operation.

When a power supply voltage is supplied to a circuit or device in which the non-volatile memory is incorporated and the circuit or device is started, the circuit or device reads out the data stored in the non-volatile memory by a read operation. A predetermined functional operation is realized according to the read data.

For example, a non-volatile memory is incorporated in an amplifier circuit (not shown) that can change the amplification factor according to the trimming data, and one or more data stored in the non-volatile memory is supplied to the amplifier circuit as trimming data. It is possible to optimally adjust the amplification factor of the amplifier circuit.

Further, the non-volatile memory according to the first embodiment can be incorporated into a semiconductor integrated circuit for various purposes such as a semiconductor integrated circuit for a DC / DC converter and a semiconductor integrated circuit for a motor driver. The amplifier circuit is an example of a circuit provided in these semiconductor integrated circuits.

<< Second Embodiment >>
A second embodiment of the present disclosure will be described. As shown in FIG. 14A, a general constant voltage source 1910 that requires a corresponding current output capacity is a reference voltage source 1911 composed of a band gap reference or the like, and the output voltage of the reference voltage source 1911 with low impedance. It is composed of a buffer amplifier 1912 to be output, and outputs an output voltage Vo from the buffer amplifier 1912. FIG. 14B shows the configuration of the constant voltage source 1910 including the internal circuit example of the buffer amplifier 1912.

If a constant voltage source is required for each of the plurality of circuits in any semiconductor integrated circuit, wiring in the semiconductor integrated circuit to which the output voltage Vo of a single buffer amplifier 1912 is applied, as shown in FIG. 15A. It is necessary to route to the required place or to arrange the constant voltage source 1910 at each place where the voltage Vo is required, as shown in FIG. 15B.

However, in the method of FIG. 15A, it is necessary to consider the influence of crosstalk, noise, etc. on the wiring to be routed, and the routing itself may not be possible considering the influence. In the method of FIG. 15B, a reference voltage source 1911 composed of a bandgap reference or the like is required for each constant voltage source 1910, and the circuit area increases.

If a constant voltage source can be configured with a simple configuration, it is possible to form a constant voltage source in a small area at a required location, which is a great merit. Although the circumstances related to the constant voltage source have been described above, the same circumstances also apply to the constant current source and the comparator, and if the constant current source or the comparator can be configured with a simple configuration, the constant current source or the comparator can be formed in a small area. It is possible to do so, and the merit is great.

The second embodiment includes the following Examples EX2_1 to EX2_3, and the techniques that contribute to the simplification of the configuration and the like will be described in Examples EX2_1 to EX2_3.

[Example EX2_1]
Example EX2_1 will be described. FIG. 16 shows a circuit diagram of the constant voltage source 1100 according to the embodiment EX2_1. The constant voltage source 1100 includes transistors Ma and Mb (first and second differential transistors), transistors Mc and Md forming the current mirror circuit CM1, output transistors Mo, and resistors Rs and Rb. The constant voltage source 1100 may be configured by a semiconductor integrated circuit.

Transistors Ma and Mb are N-channel MOSFETs, and their gates are connected to each other. That is, the transistors Ma and Mb form a differential pair in which the gates are commonly connected to each other. However, as a characteristic configuration, the gate threshold voltages of the transistors Ma and Mb are different from each other. Specifically, the transistor Ma is a depletion type MOSFET and has a negative gate threshold voltage, and the transistor Mb is an enhancement type MOSFET and has a positive gate threshold voltage.

Since the transistor Ma has a negative gate threshold voltage, even if the gate potential of the transistor Ma is lower than the source potential of the transistor Ma, the gate potential of the transistor Ma (for example, -0.3V) as seen from the source potential of the transistor Ma is the transistor. If it is higher than the gate threshold voltage of Ma (for example, −0.5 V), the transistor Ma is turned on.

The transistors Mc and Md and the output transistor Mo are P-channel MOSFETs. Each source of the transistors Mc, Md and Mo is connected to a power supply voltage line LNVddd to which a predetermined positive power supply voltage Vdd is applied. The gates of the transistors Mc and Md, the drain of the transistor Mc, and the drain of the transistor Mb are connected to each other. The drain of the transistor Md, the drain of the transistor Ma, and the gate of the output transistor Mo are connected to each other. Each source of the transistors Ma and Mb is connected to ground via resistors Rs (specifically, connected to a ground line LNgnd having a ground potential). The gate of the transistor Mb is connected to the ground (that is, the ground line LNgnd) via the resistor Rb, while the gate of the transistor Ma is directly connected to the ground (that is, the ground line LNgnd). The drain of the output transistor Mo is connected to the gate of the transistor Mb.

It can be considered that the transistor Mc functions as a current input side transistor in the current mirror circuit CM1, while the transistor Md functions as a current output side transistor in the current mirror circuit CM1. Here, the transistors Mc and Md are a pair of transistors having the same structure and having the same electrical characteristics as each other. Therefore, in the current mirror circuit CM1, a drain current having the same current value as the drain current of the transistor Mc acts to flow in the transistor Md. At this time, the drain current of the transistor Mc is output toward the transistor Mb, while the drain current of the transistor Md is output toward the transistor Ma. That is, the current mirror circuit CM1 operates so that a uniform current is output toward the drain of the transistor Ma and the drain of the transistor Mb (that is, currents having the same current value are output from each other). However, "uniformity" and "same" here are concepts including errors (the same applies to any other embodiment described later). Further, for a transistor, the structure is a concept including the size of the transistor, and therefore, for any plurality of transistors, the same structure means that the sizes of the plurality of transistors are also the same. (The same applies to any other embodiment described below).

The drain of the output transistor Mo is connected to the output terminal OUT of the constant voltage source 1100, and the output voltage Vout of the constant voltage source 1100 is generated at the output terminal OUT. The constant voltage source 1100 can supply a current to the load of the constant voltage source 1100 (not shown; a load that receives the output voltage Vout) through the output transistor Mo and the output terminal OUT. In the example of FIG. 16, in order to form the output transistor Mo, two basic MOSFETs having the same structure as the transistor Mc or Mb are prepared, and the output transistor Mo is formed by the parallel circuit of the two basic MOSFETs.

In FIG. 17, the waveform C_Ma represents the relationship between the gate-source voltage and the drain current in the transistor Ma, and the waveform C_Mb represents the relationship between the gate-source voltage and the drain current in the transistor Mb.

With the above configuration, the circuit can be balanced in a state where the values of the drain currents of the transistors Ma and Mb are the same as each other. When the values of the drain currents of the transistors Ma and Mb are the same, the gate voltage _{VG_Mb} of the transistor Mb becomes higher than the gate voltage of the transistor Ma due to the difference in the electrical characteristics of the transistors Ma and Mb. In FIG. 17, the current value I_blns represents the value of each drain current of the transistors Ma and Mb in the balanced state. The voltage V _GS _Ma_blns represents the gate-source voltage of the transistor Ma when the drain current of the current value I_blns flows through the transistor Ma, and the voltage V _GS _Mb_blns is the transistor when the drain current of the current value I_blns flows through the transistor Mb. Represents the gate-source voltage of Mb.

While the gate voltage of the transistor Ma is zero, the gate voltage _{VG_Mb} of the transistor Mb is the sum of the gate-source voltage of the transistor Mb and the voltage drop V_Rs at the resistor Rs.

The voltage (V_Rs + _{VGS_Mb_blns} ), which is the sum of the voltage drop V_Rs and the voltage _{VGS_Mb_blns} , is referred to as a balanced gate voltage. The balanced gate voltage has a positive voltage value corresponding to the electrical characteristics of the transistors Ma and Mb. Since the gate voltage of the output transistor Mo is adjusted by the transistors Ma to Md so that the gate voltage _{VG_Mb} of the transistor Mb matches the balanced gate voltage, the output voltage Vout is stabilized by the balanced gate voltage (substantially). Matches the balance gate voltage). That is, the output voltage Vout corresponding to the balance gate voltage is generated.

By the method of this embodiment, a constant voltage source can be formed with a simple configuration (hence, with a small area). In the configuration according to this embodiment, the accuracy of the output voltage Vout is not necessarily high. However, there are many applications for constant voltage sources that do not require such high voltage accuracy, and the configuration according to this embodiment is particularly suitable for such applications.

The constant voltage source 1100 includes a voltage output circuit that generates an output voltage Vout according to the gate voltage ( _{VG_Mb} ) of the transistor Mb based on the drain voltage of the transistor Ma. In the configuration of FIG. 16, the voltage output circuit includes an output transistor Mo. By applying a predetermined DC voltage (Vdd) to the series circuit of the output transistor Mo and the resistor Rb, the output voltage Vout is generated through the output transistor Mo.

In the configuration of FIG. 16, the output voltage Vout has the same voltage value as the gate voltage _{VG_Mb} of the transistor Mb, but even if the constant voltage source 1100 is modified so that the output voltage Vout and the gate voltage _{VG_Mb} are different. good. For example, the constant voltage source 1100 of FIG. 16 may be modified as shown in the constant voltage source 1100'of FIG. In the constant voltage source 1100'in FIG. 18, the resistor Rb'is inserted between the connection node 1121 between the drain of the output transistor Mo and the output terminal OUT and the connection node 1122 between the gate of the transistor Mb and the resistor Rb. .. Except for this insertion, the configurations of the constant voltage sources 1100 and 1100'are common. When the resistance Rb'is inserted, a predetermined DC voltage (Vdd) is applied to the series circuit of the output transistor Mo, the resistance Rb'and Rb, and the gate voltage _{VG_Mb} and the resistances Rb and Rb' The output voltage Vout is stabilized at a voltage determined by the resistance value ratio between them.

If the gate threshold voltages of the transistors Ma and Mb are different from each other, both the transistors Ma and Mb may be enhancement type MOSFETs (the same applies to any other embodiment described later). However, in that case, it is necessary to apply a positive bias voltage to the gate of the transistor Ma. Further, although the configuration in which the resistance Rs is inserted between each source of the transistors Ma and Mb and the ground is mentioned, instead of the resistance Rs, an active load is inserted between each source of the transistors Ma and Mb and the ground. It may be (the same applies to any other embodiment described later).

[Example EX2_2]
Example EX2_2 will be described. A constant current source can also be formed by applying the configuration shown in Example EX2_1. FIG. 19 shows a circuit diagram of the constant current source 1200 according to the example EX2_2. The constant current source 1200 includes transistors Ma and Mb (first and second differential transistors), transistors Mc and Md forming the current mirror circuit CM1, transistors Me and Mf forming the current mirror circuit CM2, and resistors Rs. And Rb. The constant current source 1200 may be configured by a semiconductor integrated circuit.

In the constant current source 1200, the transistors Ma, Mb, Mc and Md and the resistors Rs and Rb are the same as those shown in Example EX2_1, and their connection relationships are as shown in Example EX2_1. That is, each source of the transistors Mc and Md is connected to the power supply voltage line LNVdd to which a predetermined positive power supply voltage Vdd is applied. The gates of the transistors Mc and Md, the drain of the transistor Mc, and the drain of the transistor Mb are connected to each other, and the drains of the transistors Ma and Md are connected to each other. Each source of the transistors Ma and Mb is connected to ground via resistors Rs (specifically, connected to a ground line LNgnd having a ground potential). The gate of the transistor Mb is connected to the ground (that is, the ground line LNgnd) via the resistor Rb, while the gate of the transistor Ma is directly connected to the ground (that is, the ground line LNgnd).

In the current mirror circuit CM1, a drain current having the same current value as the drain current of the transistor Mc acts to flow through the transistor Md. At this time, the drain current of the transistor Mc is output toward the transistor Mb, while the drain current of the transistor Md is output toward the transistor Ma. That is, the current mirror circuit CM1 operates so that a uniform current is output toward the drain of the transistor Ma and the drain of the transistor Mb (that is, currents having the same current value are output from each other).

Transistors Me and Mf are P-channel type MOSFETs. The sources of the transistors Me and Mf are connected to the power supply voltage line LNVdd, and the gates of the transistors Me and Mf are connected to the drain of the transistor Ma. The drain of the transistor Me is connected to the gate of the transistor Mb.

It can be considered that the transistor Me functions as a current input side transistor in the current mirror circuit CM2, while the transistor Mf functions as a current output side transistor in the current mirror circuit CM2. Here, the transistors Me and Mf are a pair of transistors having the same structure and the same electrical characteristics as each other, and therefore, a drain current having the same current value as the drain current of the transistor Me flows through the transistor Mf ( However, it is assumed that a load (not shown in FIG. 19) is connected to the drain of the transistor Mf). In the example of FIG. 19, in order to form the transistor Me, two basic MOSFETs having the same structure as the transistor Mc or Mb are prepared, and the transistor Me is formed by the parallel circuit of the two basic MOSFETs. The same applies to the transistor Mf.

Similar to the configuration of FIG. 16, the configuration of FIG. 19 balances the circuit in a state where the values of the drain currents of the transistors Ma and Mb are the same as each other. Therefore, as in the case described in Example EX2_1, the gate voltages of the transistors Me and Mf are adjusted by the transistors Ma to Md so that the gate voltage _{VG_Mb} of the transistor Mb matches the balance gate voltage. As a result, a drain current having a current value obtained by dividing the balance gate voltage by the value of the resistor Rb flows through the transistor Me, and a constant current _ICC having the same current value as the current value flows as the drain current of the transistor Mf (however, FIG. 19). Assuming a load not shown in is connected to the drain of the transistor Mf).

In the constant current source 1200 of FIG. 19, a predetermined DC voltage (Vdd) is applied to the series circuit of the transistor Me and the resistor Rb, but between the drain of the transistor Me and the gate of the transistor Mb and the resistor Rb. Another resistor (not shown) may be inserted between the connection node and the connection node.

Further, the value of the constant current _ICC may be adjusted by arbitrarily adjusting the ratio between the number of basic MOSFETs constituting the transistor Me and the number of basic MOSFETs constituting the transistor Mf.

Further, one or more other transistors (not shown) having the same structure and the same electrical characteristics as the transistor Me or Mf are added to the current mirror circuit CM2, and each gate of the transistor Me or Mf and one or more other transistors are added. If the gate of the transistor is connected in common, a constant current can be obtained from the drain of one or more other transistors.

By the method of this embodiment, a constant current source can be formed with a simple configuration (hence, with a small area).

For example, the constant current source 1200 according to the embodiment EX2_2 may be used to form at least one of the constant current circuits CC _IG and CC _OTPG (see FIG. 6) shown in the first embodiment. In this case, when the constant current circuit _{CC IG} is formed by using the constant current source 1200, the constant current ICC functions as the constant current IG (see FIG. 6), and the constant current source 1200 is used to form the constant current. When forming the circuit _{CC OTPG} , the constant current ICC functions as a constant current OTPG (see FIG. 6). When the second embodiment (particularly Example EX2_2) is combined with the first embodiment, the power supply voltage lines LNVdd and LN _VDD point to the same one (hence “Vdd = VDD”), and the ground lines LNgnd and LN _GND refer to each other. It is understood that they refer to the same thing (see FIGS. 6 and 19).

As shown in FIG. 20, a configuration may be adopted in which the drain of the transistor Mf in the constant current source 1200 is connected to the ground via the resistor Rf. In the configuration of FIG. 20, an output voltage Vout'having a voltage value determined by each value of the resistance Rf and the constant current _ICC is generated between both ends of the resistance Rf. That is, the configuration of FIG. 20 functions as a constant voltage source. At this time, for example, if the values of the resistors Rb and Rf are set to be the same, a voltage that duplicates the gate voltage _{VG_Mb} (balanced gate voltage) of the transistor Mb can be obtained as the output voltage Vout'.

[Example EX2_3]
Example EX2_3 will be described. A comparator can also be formed by applying the configuration shown in Example EX2_1. FIG. 21 shows a circuit diagram of the comparator 1300 according to the example EX2_3. The comparator 1300 includes transistors Ma and Mb (first and second differential transistors), transistors Mc and Md forming the current mirror circuit CM1, resistors Rs, and an output circuit 1310. The comparator 1300 may be configured by a semiconductor integrated circuit.

In the comparator 1300, the transistors Ma, Mb, Mc and Md and the resistance Rs are the same as those shown in Example EX2_1, and their connection relationships are as shown in Example EX2_1. That is, each source of the transistors Mc and Md is connected to the power supply voltage line LNVdd to which a predetermined positive power supply voltage Vdd is applied. The gates of the transistors Mc and Md, the drain of the transistor Mc, and the drain of the transistor Mb are connected to each other, and the drains of the transistors Ma and Md are connected to each other. Each source of the transistors Ma and Mb is connected to ground via resistors Rs (specifically, connected to a ground line LNgnd having a ground potential). The gate of the transistor Ma is directly connected to the ground (that is, the ground line LNgnd).

In the current mirror circuit CM1, a drain current having the same current value as the drain current of the transistor Mc acts to flow through the transistor Md. At this time, the drain current of the transistor Mc is output toward the transistor Mb, while the drain current of the transistor Md is output toward the transistor Ma. That is, the current mirror circuit CM1 operates so that a uniform current is output toward the drain of the transistor Ma and the drain of the transistor Mb (that is, currents having the same current value are output from each other). However, whether a uniform current is actually output depends on the input voltage Vin.

In the comparator 1300 of FIG. 21, the output circuit 1310 is composed of an inverter. Therefore, the output circuit 1310 is also referred to as an inverter 1310. The input terminal of the inverter 1310 is connected to the drain of the transistor Ma, and the signal CMPout is output from the output terminal of the inverter 1310. The inverter 1310 outputs an inverted signal of an input signal to its own input terminal from its own output terminal. Specifically, the inverter 1310 outputs a high-level signal from its own output terminal when the input voltage to its own input terminal is less than a predetermined threshold voltage, and the input voltage to its own input terminal has a predetermined threshold voltage. When the voltage is higher than the voltage, a low level signal is output from its own output terminal. The inverter 1310 is driven based on the power supply voltage Vdd, and the threshold voltage of the inverter 1310 is approximately half of the power supply voltage Vdd. However, a hysteresis characteristic may be added to the threshold voltage of the inverter 1310.

In the comparator 1300, a voltage Vin is input to the gate of the transistor Mb. The voltage Vin is an input voltage to the comparator 1300, and the comparator 1300 outputs a signal CMPout indicating a high-low relationship between the input voltage Vin and a predetermined voltage. This predetermined voltage is the balance gate voltage determined by the electrical characteristics of the transistors Ma and Mb.

When the input voltage Vin becomes lower than the balance gate voltage based on the state where the input voltage Vin matches the balance gate voltage, the drain voltage of the transistor Ma drops and falls below the threshold voltage of the inverter 1310, so that the signal CMPout is at a high level. On the contrary, when the input voltage Vin becomes higher than the balance gate voltage, the drain voltage of the transistor Ma rises and exceeds the threshold voltage of the inverter 1310, so that the signal CMPout becomes a low level. That is, the signal CMPout shows the high-low relationship between the input voltage Vin and the predetermined voltage (balance gate voltage).

By the method of this embodiment, the comparator can be formed with a simple configuration (hence, with a small area).

The output circuit 1310 may be a circuit other than the inverter (for example, a buffer circuit). The output circuit 1310 can output a first level signal based on the decrease in the drain voltage of the transistor Ma in response to the input voltage Vin being lower than the balanced gate voltage, and the input voltage Vin is higher than the balanced gate voltage. Any circuit may be used as long as it can output a second level signal based on an increase in the drain voltage of the responsive transistor Ma (the first and second levels are different from each other).

[Appendix 1]
A supplementary note is provided regarding the present disclosure in which a specific configuration example is shown in the above-described embodiment.

The non-volatile memory according to the present disclosure has a first transistor, a second transistor having a gate commonly connected to the gate of the first transistor, and first and second ends, and is a source of the first transistor. With respect to the resistor to which the first end is connected, between the gate of the first transistor and the second end of the resistor, and between the gate and the source of the second transistor, the first and the above. In a lead voltage supply circuit configured to supply a lead voltage for turning on at least one of the second transistors, and in a read operation in which the lead voltage is supplied by the lead voltage supply circuit. , A signal output circuit configured to output a signal associated with the first value or a signal associated with the second value based on the drain currents of the first and second transistors. It is a configuration (first configuration).

In the non-volatile memory according to the first configuration, the signal output circuit corresponds to the first value when the drain current of the second transistor is larger than the drain current of the first transistor in the read operation. The attached signal is output, and when the drain current of the first transistor is larger than the drain current of the second transistor, the signal associated with the second value is output (second configuration). There may be.

In the non-volatile memory according to the second configuration, a configuration further comprising a program circuit configured to perform a program operation for increasing the gate threshold voltage of the second transistor by injecting hot carriers into the second transistor ( It may be the third configuration).

In the read operation executed before the program operation in the non-volatile memory according to the third configuration, the drain current of the second transistor is larger than the drain current of the first transistor and is executed after the program operation. In the read operation, the drain current of the first transistor is larger than the drain current of the second transistor as the gate threshold voltage of the second transistor increases due to the program operation (fourth configuration). It may be.

In the non-volatile memory according to the third or fourth configuration, the first and second transistors have the same structure as each other, and the first and second transistors have the same gate threshold voltage as each other before the program operation. It may have a configuration (fifth configuration).

The other non-volatile memory according to the present disclosure has a first transistor, a second transistor having a gate commonly connected to the gate of the first transistor, and first and second ends, and the first transistor. A lead voltage supply circuit configured to be able to supply a resistor to which the first end is connected to the source of the above and a read voltage for turning on at least one of the first and second transistors. In the read operation in which the lead voltage is supplied by the lead voltage supply circuit, the signal associated with the first value or the second value is supported based on the drain currents of the first and second transistors. It is a configuration (sixth configuration) including a signal output circuit configured to be able to output the attached signal.

In the non-volatile memory according to the sixth configuration, the signal output circuit is the first when the drain current of the second transistor is larger than the drain current of the first transistor when the read operation is performed. It is configured to be able to output the signal associated with the value of, and when the drain current of the first transistor is larger than the drain current of the second transistor, the signal associated with the second value can be output. It may be a configured configuration (seventh configuration).

The non-volatile memory according to the seventh configuration further includes a program circuit configured to be able to execute a program operation for increasing the gate threshold voltage of the second transistor by injecting hot carriers into the second transistor. (Eighth configuration) may be used.

In the non-volatile memory according to the eighth configuration, when the read operation is executed before the program operation, the drain current of the second transistor is larger than the drain current of the first transistor in the read operation. When the read operation is executed after the program operation, in the read operation, the drain current of the first transistor becomes the drain current of the second transistor as the gate threshold voltage of the second transistor increases due to the program operation. The configuration may be larger than the drain current (9th configuration).

In the non-volatile memory according to the eighth or ninth configuration, the first and second transistors have the same structure as each other, and the first and second transistors have the same gate threshold voltage as each other before the program operation. It may have a configuration (tenth configuration).

[Appendix 2]
A description of the constant voltage source according to the present disclosure, which is a specific example in the second embodiment, will be added.

The constant voltage source (see FIG. 16) according to the present disclosure is a differential pair composed of a first differential transistor (Ma) and a second differential transistor (Mb) in which the sources are connected to each other and have different gate threshold voltages. And a drain side circuit (CM1) connected to each drain of the first and second differential transistors and outputting a current toward the drain of the first differential transistor and the drain of the second differential transistor. It has a configuration _WB1 including a voltage output circuit (Mo) that generates an output voltage (Vout) corresponding to the gate voltage of the second differential transistor based on the drain voltage of the first differential transistor.

In the constant voltage source according to the configuration _WB1 , the first differential transistor is a depletion type MOSFET, the second differential transistor is an enhancement type MOSFET, and the gate of the first differential transistor is ground. The gate of the second differential transistor may be configured _WB2 connected to the ground via a resistor (Rb) while being directly connected to the second differential transistor.

In the constant voltage source according to the configuration _WB2 , the voltage output circuit has an output transistor (Mo) that receives the drain voltage of the first differential transistor as a gate voltage, and is a series circuit including the output transistor and the resistor. On the other hand, the configuration _WB3 may be such that a predetermined DC voltage (Vdd) is applied and the output voltage is generated through the output transistor.

In the constant voltage source according to any one of the configurations _WB1 to _WB3 , the drain side circuit operates so as to output a uniform current toward the drain of the first differential transistor and the drain of the second differential transistor. It may be the configuration _WB4 which is the drain side current mirror circuit (CM1).

The constant current source according to the present disclosure (see FIG. 19) is a differential pair composed of a first differential transistor (Ma) and a second differential transistor (Mb) in which the sources are connected to each other and have different gate threshold voltages. And a drain side circuit (CM1) connected to each drain of the first and second differential transistors and outputting a current toward the drain of the first differential transistor and the drain of the second differential transistor. It has a configuration _WC1 that generates a constant current ( _ICC ) based on the drain voltage of the first differential transistor and the gate voltage of the second differential transistor.

In the constant current source according to the configuration _WC1 , the first differential transistor is a depletion type MOSFET, the second differential transistor is an enhancement type MOSFET, and the gate of the first differential transistor is ground. The gate of the second differential transistor may be configured _WC2 connected to ground via a resistor while being directly connected to.

Configuration The constant current source according to _WC2 includes a current mirror circuit (CM2) composed of a plurality of transistors that receive the drain voltage of the first differential transistor as a gate voltage, and the plurality of transistors are transistors for the first mirror (Me). ) And a second mirror transistor (Mf), a predetermined DC voltage (Vdd) is applied to the series circuit including the first mirror transistor and the resistor, and the constant current is applied through the second mirror transistor. May be the configuration _WC3 to which is output.

In the constant current source according to any one of the configurations _{WC1 to WC3 ,} the drain side circuit operates so as to output a uniform current toward the drain of the first differential transistor and the drain of the second differential transistor. It may be the configuration _WC4 which is the drain side current mirror circuit (CM1).

The comparator (see FIG. 21) according to the present disclosure includes a differential pair composed of a first differential transistor (Ma) and a second differential transistor (Mb) in which sources are connected to each other and have different gate threshold voltages. A drain side circuit (CM1) connected to each of the drains of the first and second differential transistors and outputting a current toward the drain of the first differential transistor and the drain of the second differential transistor is provided. It has a configuration WD1 that receives an input voltage (Vin) at the gate of the second differential transistor and outputs a signal ( _CMPout ) indicating a high-low relationship between the input voltage and a predetermined voltage.

In the comparator according to the configuration _WD1 , the first differential transistor is a depletion type MOSFET, the second differential transistor is an enhancement type MOSFET, and the gate of the first differential transistor is connected to the ground. It may be the configuration _WD2 to be formed.

In the comparator according to the configuration _WD2 , the predetermined voltage is determined based on the electrical characteristics of each differential transistor, and the height relationship between the input voltage and the predetermined voltage is determined based on the drain voltage of the first differential transistor. The configuration _WD3 may be such that the signal shown above is output.

In the comparator according to any one of the configurations _WD1 to _WD3 , the drain side circuit operates to output a uniform current toward the drain of the first differential transistor and the drain of the second differential transistor. It may be a configuration _WD4 which is a side current mirror circuit (CM1).

<< Deformation, etc. >>
The embodiments of the present disclosure can be appropriately modified in various ways within the scope of the technical idea shown in the claims. The above embodiments are merely examples of the embodiments of the present disclosure, and the meanings of the terms of the present disclosure or each constituent requirement are not limited to those described in the above embodiments. The specific numerical values shown in the above description are merely examples, and as a matter of course, they can be changed to various numerical values.

For any signal or voltage, the relationship between the high level and the low level can be reversed from the above, without compromising the above-mentioned gist.

The types of FET (field effect transistors) channels shown in each embodiment are examples, so that the N-channel type FET is changed to a P-channel type FET, or the P-channel type FET is an N-channel. The configuration of the circuit containing the FET can be modified so that it is changed to a type FET.

The above-mentioned arbitrary transistor may be any kind of transistor as long as no inconvenience occurs. For example, any transistor described above as a MOSFET can be replaced with a junction FET, an IGBT (Insulated Gate Bipolar Transistor) or a bipolar transistor as long as no inconvenience occurs. Any transistor has a first electrode, a second electrode and a control electrode. In the FET, one of the first and second electrodes is a drain, the other is a source, and the control electrode is a gate. In the IGBT, one of the first and second electrodes is a collector, the other is an emitter, and the control electrode is a gate. In a bipolar transistor that does not belong to an IGBT, one of the first and second electrodes is a collector, the other is an emitter, and the control electrode is a base.

1 Storage circuit 10 Memory unit 20 Read voltage supply circuit 30 Signal output circuit 40 Program circuit

Claims (10)

1. With the first transistor
   A second transistor having a gate commonly connected to the gate of the first transistor,
   A resistance having a first end and a second end and having the first end connected to the source of the first transistor,
   At least one of the first and second transistors is turned on between the gate of the first transistor and the second end of the resistor and between the gate and the source of the second transistor. A lead voltage supply circuit configured to supply lead voltage for
   In the read operation in which the lead voltage is supplied by the lead voltage supply circuit, the signal associated with the first value or the second value is supported based on the drain currents of the first and second transistors. A non-volatile memory comprising a signal output circuit configured to output the attached signal.
2. In the read operation, the signal output circuit outputs a signal associated with the first value when the drain current of the second transistor is larger than the drain current of the first transistor, and the first transistor outputs a signal associated with the first value. The non-volatile memory according to claim 1, wherein when the drain current of the second transistor is larger than the drain current of the second transistor, a signal associated with the second value is output.
3. The non-volatile memory according to claim 2, further comprising a program circuit configured to perform a program operation for increasing the gate threshold voltage of the second transistor by injecting hot carriers into the second transistor.
4. In the read operation executed before the program operation, the drain current of the second transistor is larger than the drain current of the first transistor.
   In the read operation executed after the program operation, the drain current of the first transistor is larger than the drain current of the second transistor as the gate threshold voltage of the second transistor increases due to the program operation. Item 3. The non-volatile memory according to Item 3.
5. The first and second transistors have the same structure as each other and have the same structure.
   The non-volatile memory according to claim 3 or 4, wherein the first and second transistors have the same gate threshold voltage before the program operation.
6. With the first transistor
   A second transistor having a gate commonly connected to the gate of the first transistor,
   A resistance having a first end and a second end and having the first end connected to the source of the first transistor,
   A read voltage supply circuit configured to be able to supply a read voltage for turning on at least one of the first and second transistors.
   In the read operation in which the lead voltage is supplied by the lead voltage supply circuit, the signal associated with the first value or the second value is supported based on the drain currents of the first and second transistors. A non-volatile memory comprising a signal output circuit configured to be able to output the attached signal.
7. The signal output circuit can output a signal associated with the first value when the drain current of the second transistor is larger than the drain current of the first transistor when the read operation is performed. The non-volatile property according to claim 6, wherein the signal associated with the second value can be output when the drain current of the first transistor is larger than the drain current of the second transistor. memory.
8. The non-volatile memory according to claim 7, further comprising a program circuit configured to be able to execute a program operation for increasing the gate threshold voltage of the second transistor by injecting hot carriers into the second transistor.
9. When the read operation is executed before the program operation, the drain current of the second transistor is larger than the drain current of the first transistor in the read operation.
   When the read operation is executed after the program operation, in the read operation, the drain current of the first transistor becomes the drain of the second transistor as the gate threshold voltage of the second transistor increases due to the program operation. The non-volatile memory according to claim 8, which is larger than the current.
10. The first and second transistors have the same structure as each other and have the same structure.
    The non-volatile memory according to claim 8 or 9, wherein the first and second transistors have the same gate threshold voltage before the program operation.

Images