JPWO2003028214A1

JPWO2003028214A1 - Multistable circuit

Info

Publication number: JPWO2003028214A1
Application number: JP2003531610A
Authority: JP
Inventors: 鈴木　利康; 利康鈴木
Original assignee: Individual
Current assignee: Individual
Priority date: 2001-09-19
Filing date: 2001-09-19
Publication date: 2005-01-13
Also published as: WO2003028214A1

Abstract

その安定状態に応じた電圧もしくは電位を出力できる多安定回路で、用途は多値メモリー・セル、多値メモリー、多値記憶手段、多値論理回路、多値コンピュータ、多値制御手段などである。例えば、１０安定回路の場合、電源線（Ｖ１）から電源線（Ｖ１０）の方へ行くのに従って順々にその電位は高くなり、電源線（Ｖ１）と入出力端子（Ｔｉｏ）の間に「負性抵抗特性を持つプル・ダウン手段」を接続し、電源線（Ｖ２）から電源線（Ｖ９）までの各電源線と入出力端子（Ｔｉｏ）の間に「その負性抵抗特性を双方向に持つ双方向性プル手段」を１つずつ接続し、電源線（Ｖ１０）と入出力端子（Ｔｉｏ）の間に「その負性抵抗特性を持つプル・アップ手段」を接続している。その負性抵抗特性は「その両端電圧の大きさが小さくなるとその抵抗が小さくなり、その両端電圧の大きさが大きくなるとその抵抗が大きくなる負性抵抗特性」である。前記双方向性プル手段を８つ用いたので、読み出し不能も、読み出し時の安定状態の変化も、誤った読み出しも無くなり、読み出し時間が早くなる。Multi-stable circuit that can output voltage or potential according to its stable state, and is used for multi-value memory cell, multi-value memory, multi-value storage means, multi-value logic circuit, multi-value computer, multi-value control means, etc. . For example, in the case of a 10-stable circuit, the potential increases in order as it goes from the power supply line (V1) to the power supply line (V10). "Pull-down means with negative resistance characteristics" is connected, and the negative resistance characteristics are bidirectional between the power supply lines (V2) to the power supply line (V9) and the input / output terminals (Tio). Are connected one by one, and “pull-up means having the negative resistance characteristic” is connected between the power supply line (V10) and the input / output terminal (Tio). The negative resistance characteristic is “a negative resistance characteristic in which the resistance decreases as the voltage across the terminal decreases and the resistance increases as the voltage across the terminal increases”. Since eight bi-directional pulling means are used, there is no reading failure, no change in the stable state during reading, no erroneous reading, and the reading time is shortened.

Description

技術分野
この発明は、その安定状態の数が３又は３以上で、その安定状態に応じた電圧もしくは電位を出力できる多安定回路に関する。この多安定回路は多値のメモリー・セル、多値メモリー又は多値記憶手段として利用できるので、多値論理回路、多値コンピュータ又は多値の制御手段などにも利用できる。
背景技術
従来の多安定回路として本発明者の先行技術である特許第２８５３０４１号の第１４図〜第１５図や特開２０００−８３３６９号の図２７〜図３６に開示された多安定回路のうち、１０安定回路の１例を第４図に示す。
第４図でＶ１〜Ｖ１０は１０本の電源線で、電源線Ｖ１から電源線Ｖ１０の方へ行くに従い順々にその電位は高くなって行く。各電源線と入出力端子Ｔｉｏとの間に１つずつ接続される「Ｐ、Ｎチャネルの接合型ＦＥＴ２つの接続体」は第５図の通り構成され、その両ＦＥＴがノーマリィ・オンであるためその接続体は「その両端電圧の大きさが小さくなるとその抵抗が小さくなり、その両端電圧の大きさが大きくなるとその抵抗が大きくなる負性抵抗特性」を持つ負性抵抗手段である。但し、第５図の負性抵抗手段は逆方向（図の下から上の方向）の電圧、電流に対して阻止能力が無い逆導通型の負性抵抗手段である。（参考：特開昭５１−２９２１号の第１図）
そして、「電源線Ｖ１０に接続される負性抵抗手段」だけがプル・アップ手段として機能し、「電源線Ｖ９〜Ｖ１それぞれに１つずつ接続される負性抵抗手段」はプル・ダウン手段として機能するので、第４図の多安定回路は１０の安定状態を持つことができる。これら負性抵抗手段は逆導通型である為「電源線Ｖ９〜Ｖ２に接続される各負性抵抗手段」に逆阻止用ダイオードが１つずつ直列接続され、１方向性の負性抵抗手段が８つ構成されている。
その接続理由は、例えば入出力端子Ｔｉｏが電源線Ｖ１の電位または電圧を出力するとき「電源線Ｖ９〜Ｖ２に接続される各負性抵抗手段から逆方向電流が電源線Ｖ１へ流れ込んで、その逆方向電流が電源線Ｖ１に接続される負性抵抗手段のプル・ダウン動作を妨げる」のを防ぐ為である。
尚、第４図の多安定回路において「各電源線間の電位差の大きさ」と「各ＦＥＴの完全オフ駆動電圧の大きさ」の関係に関して、その１０の負性抵抗手段のうち１つはオンで、残り９つはオフであるが、各オフが完全なオフであれば、どの安定状態の時でも「少なくとも２つ以上の負性抵抗手段を同時に流れる漏洩電流」が無く、消費電流ゼロで、都合が良い。そのためには「各電源線間の電位差の大きさ」は「オフである９つの負性抵抗手段それぞれの各ＦＥＴの完全オフ駆動電圧の大きさ」以上の大きさのゲート逆バイアス電圧をそのＦＥＴに供給できる大きさでなければならない。
また、第６図〜第８図に他の負性抵抗手段の例を３つ示す。但し、一般的なＩＧＢＴはノーマリィ・オフのＭＯＳＦＥＴ構造を内蔵しているが、そのＭＯＳＦＥＴをノーマリィ・オンにすれば、当然そのＩＧＢＴはノーマリィ・オンになる。もちろん、第４図の回路において各負性抵抗手段の代わりに第６図〜第８図の負性抵抗手段のうちどれかを１つずつ使うことができる。
（参考：特開２０００−８３３６９号の図８１〜図１００の各負性抵抗手段と、ノーマリィ・オンのＳＩサイリスタを用いた図３５〜図３６。）
さらに、第４図の回路において第８図の負性抵抗手段を１０個用いる回路の場合、「電源線Ｖ９〜Ｖ２に接続されるＩＧＢＴ」が全て逆阻止型ならば、「第４図に示される８つの逆阻止用ダイオード」は必要無く、その全ての負性抵抗手段を入出力端子Ｔｉｏに直結することができる。この事は逆阻止型のノーマリィ・オンのＳＩサイリスタを使う場合も同じである。
しかしながら、「電源線Ｖ９〜Ｖ２に接続される負性抵抗手段」それぞれはその安定状態に応じてプル・ダウン機能を持つ一方、プル・アップ機能を持たないために、『読み出し不能になったり、又は、読み出しが遅かったり、あるいは、読み出しの際にその安定状態が変わり（すなわち、記憶内容が書き換えられ）、誤った安定状態の電位または電圧（すなわち、誤った記憶内容）が読み出されてしまう』という第１の問題点が有る。
（第１の問題点）
例えば、選択スイッチでデータ線を入出力端子Ｔｉｏに接続して、入出力端子Ｔｉｏからその安定状態の電位（又は電圧）を読み出す時そのデータ線の電位が「その読み出す時の安定状態の電位」よりも低い場合、「電源線Ｖ１０に接続される負性抵抗手段」ならプル・アップできるが、「電源線Ｖ９〜Ｖ２に接続される各負性抵抗手段」ではプル・アップすることができない。この事が読み出し不能または遅い読み出しとなる。又は、逆にそのデータ線が入出力端子Ｔｉｏの電位をプル・ダウンしてその安定状態を変化させ、誤った安定状態の電位が読み出されてしまう。つまり、記憶内容が書き換えられ、誤った記憶内容が読み出されてしまう。
その問題を解決するために「電源線Ｖ１０に接続される負性抵抗手段」の代わりに例えばプル・アップ抵抗などのプル・アップ手段を接続する方法が考えられるが、今度は『安定状態のときの消費電流が増えてしまう』という第２の問題点が新たに生じる。（第２の問題点）
尚、「第４図の回路に対して電圧極性もしくは電圧方向に関して対称的な関係に有る回路」すなわち「第４図の回路において各トランジスタを『それと相補関係に有るトランジスタ（例：ＮチャネルＦＥＴに対するＰチャネルＦＥＴ。）』で１つずつ置き換え、電圧極性もしくは電圧方向の有る各構成要素（例：直流電源、ダイオード。）の向きを逆にした多安定回路」では、電源線Ｖ１０〜Ｖ１の電位の高低が正反対にひっくり返り、８つの逆阻止用ダイオードの向きが逆になるので、前述したプル・アップ機能の補足、強化ではなくプル・ダウン機能の補足、強化が必要になる。
この場合も、プル・ダウン抵抗などのプル・ダウン手段が接続されるため、大きなシンク電流（吸い込み電流）を供給する必要が有り、やはり『安定状態の時の消費電流が増えてしまう』という第２の問題点が新たに生じる。
そこで、本発明は、『安定状態のときの消費電流を増やさずに、読み出し不能も、読み出し時の安定状態の変化も、誤った安定状態の電位または電圧（もしくは誤った記憶内容）の読み出しも無く、かつ、読み出し時間が早い』多安定回路を提供することを目的としている。
発明の開示
即ち、本発明は請求の範囲第１項に記載された通りの多安定回路である。本発明は、少なくとも「最高電位の電位供給線手段（例えば電源線など。）と最低電位の電位供給線手段の間に有る電位供給線手段」のそれぞれに接続される各負性抵抗手段に「その両端電圧の大きさが小さくなるとその抵抗が小さくなり、その両端電圧の大きさが大きくなるとその抵抗が大きくなる負性抵抗特性」を双方向に対して持つ双方向性プル手段を１つずつ用いている。ただし、その電位供給線手段の数は３又は３以上の所定数であるから、本発明の多安定回路は３安定回路もしくはそれ以上の安定回路である。
このことによって、その双方向性プル手段それぞれはプル・アップとプル・ダウンの両機能を持っている。このため、外部データ線がこの多安定回路の入出力端子に接続されて、その入出力端子からその安定状態の電位を読み出す時、たとえその外部データ線の電位が「その読み出す時の安定状態」の電位より高かろうが低かろうが、その外部データ線はその安定状態に応じてプル・アップされたり、あるいは、プル・ダウンされたりするので、『読み出し不能も、読み出し時の安定状態の変化も、誤った安定状態の電位または電圧（もしくは誤った記憶内容）の読み出しも無く、読み出し時間が早い』という第１の効果が本発明の多安定回路に有る。（第１の効果）
それから、前述した様なプル・アップ抵抗などのプル・アップ手段またはプル・ダウン抵抗などのプル・ダウン手段が必要無いので、『安定状態の時の消費電流が増えない』という第２の効果が本発明の多安定回路に有る。
（第２の効果）
尚、「その最高電位の電位供給線手段に接続される、負性抵抗特性を持つプル・アップ手段」が前述した様な双方向性プル手段でももちろん構わないし、「最低電位の電位供給線手段に接続される、負性抵抗特性を持つプル・ダウン手段」が前述した様な双方向性プル手段でももちろん構わない。両方とも双方向性プル手段である多安定回路は、請求の範囲第２項記載の多安定回路に対応する。
発明を実施するための最良の形態
本発明をより詳細に説明するために、添付図面に従ってこれを説明する。第１図に示す１実施例は「請求の範囲第１項に記載中の所定数Ｎ」が１０である１０安定回路で、電源線Ｖ１から電源線Ｖ１０の方へ行くに従い順々にその電位は高くなって行く。第１図の実施例の各構成手段は次の通り請求の範囲第１項に記載中の各構成手段に相当する。
ａ）電源線Ｖ１〜Ｖ１０それぞれが同項記載中の第１電位供給線手段から第１０電位供給線手段までのそれぞれにこの順序で。
ｂ）出力端子Ｔｏｕｔが請求項１記載中の出力端子に。
ｃ）「電源線Ｖ１と出力端子Ｔｏｕｔの間に接続されるＰ、Ｎチャネルの接合型ＦＥＴ計２つの接合体」が請求項１記載中のプル・ダウン手段に。
ｄ）「電源線Ｖ２〜Ｖ９それぞれと出力端子Ｔｏｕｔの間に１つずつ接続されるＰ、Ｎチャネルの接合型ＦＥＴ計４つの接合体」が請求項１記載中の双方向性プル手段に。
ｅ）「電源線Ｖ１０と出力端子Ｔｏｕｔの間に接続されるＰ、Ｎチャネルの接合型ＦＥＴ計２つの接合体」が請求項１記載中のプル・アップ手段に。
当然の事ながら、それぞれの電源線間には直流電源手段（図示せず。）が１つずつ存在する。電源線Ｖ１０、Ｖ１それぞれと入出力端子Ｔｉｏの間に従来と同じ様に「Ｐ、Ｎチャネルの接合型ＦＥＴ２つの接続体」が１つずつ接続され、各接続体はプル・アップ手段とプル・ダウン手段として機能する。
一方、電源線Ｖ９〜Ｖ２それぞれと入出力端子Ｔｉｏの間には双方向性の負性抵抗手段が１つずつ接続され、それらの負性抵抗手段は「プル・アップ機能とプル・ダウン機能を持つ双方向性プル手段」として機能する。それら双方向性の負性抵抗手段は「第５図に示される負性抵抗手段２つが直列接続されたもの」であるが、両方の逆導通方向は互いに正反対であるため、その双方向性の負性抵抗手段は「その両端電圧の大きさが小さくなるとその抵抗が小さくなり、その両端電圧の大きさが大きくなるとその抵抗が大きくなる負性抵抗特性」を双方向に持つことができる。
このため、「電源線Ｖ１０〜Ｖ２に接続される負性抵抗手段」それぞれはプル・アップ手段として機能できるので、例えばデータ読み出しの際に選択スイッチが外部データ線を入出力端子Ｔｉｏに接続した時その外部データ線の電位が「その読み出す時の安定状態の電位」より低くても、容易に「電源線Ｖ１０〜Ｖ２に接続される負性抵抗手段」それぞれはその外部データ線の電位をプル・アップすることができる。そして、「電源線Ｖ９〜Ｖ１に接続される負性抵抗手段」それぞれはプル・ダウン手段として機能できるので、例えばデータ読み出し時に選択スイッチが外部データ線を入出力端子Ｔｉｏに接続した時その外部データ線の電位が「その読み出す時の安定状態の電位」より高くても、「電源線Ｖ９〜Ｖ１に接続される負性抵抗手段」それぞれは容易にその外部データ線の電位をプル・ダウンすることができる。
その結果、前述通り『読み出し不能も、読み出し時の安定状態の変化も、誤った安定状態の電位または電圧（もしくは誤った記憶内容）の読み出しも無く、読み出し時間が早くなる』という第１効果が、第１図の実施例を含め、本発明の多安定回路に有る。（第１効果）
読み出し時間が早くなるのはその外部データ線の電荷の充放電がすべての安定状態において速やかに行われる様になるからである。
それから、前述した様な「プル・アップ抵抗などのプル・アップ手段」や「プル・ダウン抵抗などのプル・ダウン手段」が必要無いので、『安定状態のときの消費電流が増えない』という第２効果が、第１図の実施例を含め、本発明の多安定回路に有る。（第２効果）
尚、「電源線Ｖ１０、Ｖ１それぞれに接続される負性抵抗手段」が「電源線Ｖ９〜Ｖ２それぞれに接続される双方向性の負性抵抗手段」と同じ双方向性の負性抵抗手段であっても、回路動作上で全く問題無い。その部品点数の増加が問題にならないのなら、むしろその方が『全ての負性抵抗手段が同じ構成になるため、ＩＣ化の際に都合が良い』という利点が有るし、『電源の接続を間違えて電源線Ｖ１０から電源線Ｖ１の方へ行くに従って順々にその電位が高くなって行っても全く問題が無いし、又は、積極的に電源線の電位の高低を入れ換える使い方もできる』という利点も有る。これらの事は後述する第２図〜第３図の各実施例についても言うことができる。
第２図〜第３図に示す各実施例も、「請求の範囲第１項に記載中の所定数Ｎ」が１０である１０安定回路である。「電源線Ｖ９〜Ｖ２それぞれに接続される双方向性の負性抵抗手段」として第２図に示す実施例では「第５図の負性抵抗手段とダイオード・ブリッジ接続型整流回路を組み合わせた双方向性の負性抵抗手段」を１つずつ使用し、第３図に示す実施例では「第５図の負性抵抗手段と逆阻止用ダイオードを直列接続した１方向性の負性抵抗手段を２つ逆並列接続した双方向性の負性抵抗手段」を１つずつ使用している。
最後に補足する事として第１図〜第３図の各実施例は「請求の範囲第１項に記載中の所定数Ｎ」が１０である１０安定回路であるが、所定数Ｎは当然１０に限定されず、３又はそれ以上ならいくつでも構わない。例えば４、５、８、１２、１５、１６、２０、２５、３０、３２、４５、６０、６４等。
また、第１図〜第３図の各実施例において「電源線Ｖ１０、Ｖ１それぞれに接続される負性抵抗手段」の代わりに「第５図の負性抵抗手段と逆阻止用のダイオードを直列接続した１方向性の負性抵抗手段」を１つずつ用いても良い。この事は接合型ＦＥＴを使わない負性抵抗手段の場合でも言える。
さらに、「第１図〜第３図の各実施例」又は「それから派生する各実施例」においてＰチャネルの接合型ＦＥＴの代わりに「駆動用の逆バイアス電圧極性がプラスで、ノーマリィ・オンのスイッチング手段」なら何でも使うことができ、Ｎチャネルの接合型ＦＥＴの代わりに「駆動用の逆バイアス電圧極性がマイナスで、ノーマリィ・オンのスイッチング手段」なら何でも使うことができる。
それから、第３図の実施例で各接合型ＦＥＴの代わりに逆阻止型ＩＧＢＴの様にノーマリィ・オンの逆阻止型スイッチング手段を１つずつ使う場合、逆阻止用ダイオードは１つも要らない。
そして、「第１図〜第３図の各実施例」又は「それから派生する各実施例」において「それぞれの電源線間の電位差の大きさ」と「各負性抵抗手段を構成するノーマリィ・オンの各スイッチング手段の完全オフ駆動電圧の大きさ」の関係に関して、そのすべての負性抵抗手段のうち１つはオンで、その残りはオフであるが、各オフが完全なオフであれば、どの安定状態の時でも「少なくとも２つ以上の負性抵抗手段を同時に流れる漏洩電流」が全く無く、ＣＭＯＳメモリーの様に安定状態での消費電流はゼロで、都合良い。そのためには「それぞれの電源線間の電位差の大きさ」は「オフであるその残りの負性抵抗手段それぞれの各スイッチング手段の完全オフ駆動電圧の大きさ」以上の大きさの駆動逆バイアス電圧をそのスイッチング手段に供給できる大きさでなければならない。
産業上の利用可能性
半導体の高集積化による高機能化もそろそろ限界に達していると言われており、別の手段、方法が模索されている。その１つの答えが多値化であるが、本発明にかかる多安定回路は多値メモリー・セル、多値メモリーもしくは多値記憶手段として有用であり、多値論理回路、多値コンピュータもしくは多値制御手段などに用いるのに適している。
【図面の簡単な説明】
第１図〜第３図それぞれは本発明の実施例の回路を１つずつ示す回路図であり、第４図は従来の多安定回路の１例を示す回路図であり、第５図〜第８図それぞれは負性抵抗手段の例を１つずつ示す回路図である。TECHNICAL FIELD The present invention relates to a multi-stable circuit having three or more stable states and capable of outputting a voltage or potential according to the stable state. Since this multi-stable circuit can be used as a multi-value memory cell, multi-value memory or multi-value storage means, it can also be used as a multi-value logic circuit, a multi-value computer or a multi-value control means.
BACKGROUND ART Among the multistable circuits disclosed in FIGS. 14 to 15 of Japanese Patent No. 2853041 and FIGS. 27 to 36 of Japanese Patent Laid-Open No. 2000-83369, which are prior arts of the present inventor, as conventional multistable circuits. An example of a 10-stable circuit is shown in FIG.
In FIG. 4, V1 to V10 are 10 power supply lines, and the potential increases in order from the power supply line V1 toward the power supply line V10. “Connected body of two P and N channel junction type FETs” connected one by one between each power line and the input / output terminal Tio is configured as shown in FIG. 5 and both FETs are normally on. The connection body is a negative resistance means having “negative resistance characteristics in which the resistance decreases when the voltage across the terminal decreases, and the resistance increases when the voltage across the terminal increases”. However, the negative resistance means in FIG. 5 is a reverse conduction type negative resistance means having no blocking ability against voltage and current in the reverse direction (from the bottom to the top of the figure). (Reference: Fig. 1 of Japanese Patent Laid-Open No. 51-2921)
Only “negative resistance means connected to power supply line V10” functions as pull-up means, and “negative resistance means connected to power supply lines V9 to V1 one by one” serves as pull-down means. Because it functions, the multistable circuit of FIG. 4 can have ten stable states. Since these negative resistance means are reverse conducting types, one reverse blocking diode is connected in series to each negative resistance means connected to the power supply lines V9 to V2, and one-way negative resistance means is provided. Eight are configured.
The reason for the connection is, for example, when the input / output terminal Tio outputs the potential or voltage of the power supply line V1, “the reverse current flows from each negative resistance means connected to the power supply lines V9 to V2 into the power supply line V1, This is to prevent the reverse current from hindering the pull-down operation of the negative resistance means connected to the power supply line V1.
In the multi-stable circuit of FIG. 4, regarding the relationship between “the magnitude of the potential difference between the power supply lines” and “the magnitude of the complete OFF drive voltage of each FET”, one of the ten negative resistance means is ON and the remaining 9 are OFF, but if each OFF is completely OFF, there is no “leakage current flowing through at least two negative resistance means simultaneously” in any stable state, and no current consumption And convenient. For this purpose, “the magnitude of the potential difference between the power supply lines” is set to a gate reverse bias voltage larger than “the magnitude of the complete off drive voltage of each FET of each of the nine negative resistance means that are off”. Must be large enough to supply.
FIGS. 6 to 8 show three examples of other negative resistance means. However, a general IGBT has a normally-off MOSFET structure, but if the MOSFET is normally turned on, the IGBT is naturally turned on. Of course, any one of the negative resistance means of FIGS. 6 to 8 can be used one by one in place of each negative resistance means in the circuit of FIG.
(Reference: FIGS. 35 to 36 using the negative resistance means shown in FIGS. 81 to 100 of JP-A-2000-83369 and normally-on SI thyristors.)
Further, in the circuit of FIG. 4, in the case of a circuit using 10 negative resistance means of FIG. 8, if “IGBTs connected to the power supply lines V9 to V2” are all reverse blocking type, “shown in FIG. The eight reverse blocking diodes "are not necessary, and all the negative resistance means can be directly connected to the input / output terminal Tio. The same is true when using a reverse-blocking normally-on SI thyristor.
However, since each of the “negative resistance means connected to the power supply lines V9 to V2” has a pull-down function according to its stable state, it does not have a pull-up function. Or, reading is slow, or the stable state changes at the time of reading (that is, the stored content is rewritten), and an incorrect stable state potential or voltage (that is, the incorrect stored content) is read. There is a first problem.
(First problem)
For example, when the data line is connected to the input / output terminal Tio with a selection switch and the stable potential (or voltage) is read from the input / output terminal Tio, the potential of the data line is “the stable potential at the time of reading”. If it is lower, the “negative resistance means connected to the power supply line V10” can be pulled up, but the “respective negative resistance means connected to the power supply lines V9 to V2” cannot be pulled up. This makes reading impossible or slow reading. Or, conversely, the data line pulls down the potential of the input / output terminal Tio to change its stable state, and an erroneously stable potential is read out. That is, the stored content is rewritten and the wrong stored content is read out.
In order to solve the problem, a method of connecting pull-up means such as a pull-up resistor instead of “negative resistance means connected to the power supply line V10” can be considered. The second problem is that the current consumption increases. (Second problem)
It should be noted that “a circuit having a symmetric relationship with respect to the voltage polarity or voltage direction with respect to the circuit of FIG. 4”, that is, “transistors in the circuit of FIG. P channel FET.) ”Is replaced one by one, and in the“ stable circuit in which the direction of each component having a voltage polarity or voltage direction (eg, DC power supply, diode) is reversed ”, the potentials of the power supply lines V10 to V1 Since the heights of the eight reverse blocking diodes are reversed in opposite directions, the pull-up function is supplemented and strengthened instead of the above-described pull-up function.
In this case as well, a pull-down means such as a pull-down resistor is connected, so it is necessary to supply a large sink current (sink current). Two new problems arise.
Therefore, the present invention provides the following: “Reading is impossible without increasing the current consumption in the stable state, the change in the stable state at the time of reading, and the reading of the incorrect stable state potential or voltage (or the wrong stored contents). The purpose is to provide a multi-stable circuit that is free of reading time.
DISCLOSURE OF THE INVENTION That is, the present invention is a multi-stable circuit as set forth in claim 1. According to the present invention, each negative resistance means connected to each of at least “the potential supply line means between the highest potential supply line means (for example, a power supply line) and the lowest potential supply line means”. When the voltage at both ends is reduced, the resistance is reduced, and when the voltage at both ends is increased, the resistance is increased. Used. However, since the number of potential supply line means is 3 or a predetermined number of 3 or more, the multistable circuit of the present invention is a tristable circuit or more.
Thus, each of the bidirectional pull means has both a pull-up function and a pull-down function. Therefore, when an external data line is connected to the input / output terminal of this multi-stable circuit and the potential of the stable state is read from the input / output terminal, even if the potential of the external data line is `` stable state when reading '' The external data line is either pulled up or pulled down depending on its stable state, whether it is higher or lower than the potential. The first effect of the present invention is that there is no change, no reading of an erroneously stable potential or voltage (or incorrect stored contents), and a quick reading time ”. (First effect)
Then, since there is no need for pull-up means such as the pull-up resistor or pull-down resistance as described above, the second effect is that “the current consumption does not increase in a stable state”. It exists in the multistable circuit of this invention.
(Second effect)
Of course, the “pull-up means having negative resistance characteristics connected to the potential supply line means having the highest potential” may be the bidirectional pull means as described above. Of course, the pull-down means having a negative resistance characteristic connected to the above may be the bidirectional pull means as described above. The multistable circuit, which is a bidirectional pull means, corresponds to the multistable circuit described in claim 2.
BEST MODE FOR CARRYING OUT THE INVENTION In order to explain the present invention in more detail, it will be described with reference to the accompanying drawings. One embodiment shown in FIG. 1 is a 10-stable circuit whose “predetermined number N described in claim 1” is 10, and its potential is sequentially increased from the power supply line V1 toward the power supply line V10. Goes higher. Each constituent means of the embodiment of FIG. 1 corresponds to each constituent means described in claim 1 as follows.
a) Each of the power supply lines V1 to V10 is arranged in this order from the first potential supply line means to the tenth potential supply line means in the same paragraph.
b) The output terminal Tout is the output terminal according to claim 1.
The pull-down means according to claim 1, wherein c) “two junctions of P and N channel junction FETs connected between the power supply line V 1 and the output terminal Tout”.
d) The bidirectional pull means according to claim 1, wherein “a total of four P and N channel junction FETs connected one by one between the power supply lines V2 to V9 and the output terminal Tout”.
The pull-up means according to claim 1, wherein e) “two junctions of P and N channel junction FETs connected between the power supply line V10 and the output terminal Tout”.
As a matter of course, one DC power source means (not shown) exists between each power line. As in the prior art, “two connected bodies of P and N channel junction FETs” are connected one by one between the power supply lines V10 and V1 and the input / output terminal Tio, and each connected body is connected to the pull-up means and the pull-up means. Functions as a down means.
On the other hand, one bidirectional negative resistance means is connected between each of the power supply lines V9 to V2 and the input / output terminal Tio, and these negative resistance means have “pull-up function and pull-down function”. It functions as a “bidirectional pull means”. These bidirectional negative resistance means are “two negative resistance means shown in FIG. 5 connected in series”, but both reverse conduction directions are opposite to each other. The negative resistance means can have a “negative resistance characteristic in which the resistance decreases when the voltage across the terminal decreases and the resistance increases when the voltage across the terminal increases” in both directions.
Therefore, each of the “negative resistance means connected to the power supply lines V10 to V2” can function as a pull-up means. For example, when the selection switch connects the external data line to the input / output terminal Tio at the time of data reading. Even if the potential of the external data line is lower than “the potential of the stable state at the time of reading”, each of the “negative resistance means connected to the power supply lines V10 to V2” easily pulls the potential of the external data line. Can be up. Since each of the “negative resistance means connected to the power supply lines V9 to V1” can function as a pull-down means, for example, when the selection switch connects the external data line to the input / output terminal Tio at the time of data reading, the external data Even if the potential of the line is higher than “the potential of the stable state at the time of reading”, the “negative resistance means connected to the power supply lines V9 to V1” can easily pull down the potential of the external data line. Can do.
As a result, as described above, the first effect is that “reading is not possible, there is no change in the stable state at the time of reading, there is no reading of an incorrect stable state potential or voltage (or wrong stored contents), and the reading time is shortened”. 1 includes the multi-stable circuit of the present invention, including the embodiment of FIG. (First effect)
The reason why the read time is shortened is that the charge and discharge of the external data line are performed quickly in all stable states.
And since there is no need for "pull-up means such as pull-up resistors" or "pull-down means such as pull-down resistors" as described above, the "current consumption does not increase in the stable state" There are two effects in the multistable circuit of the present invention including the embodiment of FIG. (Second effect)
The “negative resistance means connected to each of the power supply lines V10 and V1” is the same bidirectional negative resistance means as the “bidirectional negative resistance means connected to each of the power supply lines V9 to V2”. Even if there is, there is no problem in the circuit operation. If the increase in the number of parts does not become a problem, rather, it has the advantage that it is convenient for making an IC because all negative resistance means have the same configuration. There is no problem even if the potential increases in sequence as the power line V10 goes from the power line V1 to the power line V1, or there is no problem or the power line potential can be positively switched. ” There are also advantages. These things can be said also about each Example of FIG. 2-FIG. 3 mentioned later.
Each of the embodiments shown in FIGS. 2 to 3 is also a 10-stable circuit in which “the predetermined number N described in claim 1” is 10. In the embodiment shown in FIG. 2 as “bidirectional negative resistance means connected to each of power supply lines V9 to V2,” “both combining the negative resistance means of FIG. 5 and a diode bridge connection type rectifier circuit” One directional negative resistance means "is used one by one. In the embodiment shown in FIG. 3, the unidirectional negative resistance means in which the negative resistance means of FIG. 5 and a reverse blocking diode are connected in series is used. Two bidirectional negative resistance means connected in reverse parallel are used one by one.
As a final supplement, each of the embodiments shown in FIGS. 1 to 3 is a 10-stable circuit in which the “predetermined number N in the first claim” is 10, but the predetermined number N is naturally 10 The number is not limited, and any number of three or more is acceptable. For example, 4, 5, 8, 12, 15, 16, 20, 25, 30, 32, 45, 60, 64, etc.
1 to FIG. 3, in place of “negative resistance means connected to power supply lines V10 and V1,” “negative resistance means of FIG. 5 and reverse blocking diode are connected in series. One connected negative resistance means "may be used one by one. This is true even in the case of negative resistance means that does not use a junction FET.
Furthermore, instead of the P-channel junction FET in “Embodiments of FIGS. 1 to 3” or “Embodiments derived therefrom”, “the reverse bias voltage polarity for driving is positive and normally on Any "switching means" can be used, and any "switching means with a negative polarity of drive reverse bias voltage and normally on" can be used instead of an N-channel junction FET.
Then, in the embodiment of FIG. 3, when one normally-on reverse blocking switching means such as a reverse blocking IGBT is used instead of each junction FET one by one, no reverse blocking diode is required.
Further, in “Embodiments of FIGS. 1 to 3” or “Embodiments derived therefrom”, “the magnitude of the potential difference between the respective power supply lines” and “normally on constituting each negative resistance means” As for the relationship of “the magnitude of the completely off drive voltage of each switching means”, one of all the negative resistance means is on and the rest are off, but if each off is completely off, In any stable state, there is no “leakage current flowing through at least two negative resistance means simultaneously”, and the current consumption in the stable state is zero as in the CMOS memory, which is convenient. For this purpose, “the magnitude of the potential difference between the respective power supply lines” is equal to or greater than “the magnitude of the completely off drive voltage of each switching means of each of the remaining negative resistance means that is off”. Must be large enough to supply the switching means.
Industrial applicability It is said that high functionality by high integration of semiconductors is approaching its limit, and other means and methods are being sought. One answer is multi-leveling, but the multi-stable circuit according to the present invention is useful as a multi-level memory cell, multi-level memory or multi-level storage means, multi-level logic circuit, multi-level computer or multi-level. Suitable for use as a control means.
[Brief description of the drawings]
1 to 3 are circuit diagrams each showing a circuit according to an embodiment of the present invention. FIG. 4 is a circuit diagram showing an example of a conventional multi-stable circuit. FIGS. FIG. 8 is a circuit diagram showing one example of negative resistance means.

Claims

When N is a predetermined number of 3 or 3 or more,
A first potential supply line means to an Nth potential supply line means for supplying N potentials whose potentials increase in numerical order from the first potential to the Nth potential;
Input / output terminals for input / output of signals;
The negative potential is connected between the first potential supply line means and the input / output terminal. “The resistance decreases as the voltage across the terminal decreases, and the resistance increases when the voltage across the terminal increases. Pull-down means with "resistance characteristics";
One is connected between each of the potential supply line means from the second potential supply line means to the (N-1) th potential supply line means and the input / output terminal. (N-2) bidirectional pulling means having a negative resistance characteristic that the resistance increases as the resistance decreases and the magnitude of the voltage across the terminal increases.
Connected between the N-th potential supply line means and the input / output terminal, “the resistance decreases as the voltage across the terminal decreases, and the resistance increases when the voltage across the terminal increases. A multi-stable circuit comprising pull-up means having a resistance characteristic.

The pull-down means functions as “bidirectional pull means having bidirectional negative resistance characteristics”, and the pull-up means “bidirectional pull characteristics having bidirectional negative resistance characteristics”. The multistable circuit according to claim 1, which functions as a “means”.