JPH10341149A - Bipolar level shift circuit - Google Patents
Bipolar level shift circuitInfo
- Publication number
- JPH10341149A JPH10341149A JP9151399A JP15139997A JPH10341149A JP H10341149 A JPH10341149 A JP H10341149A JP 9151399 A JP9151399 A JP 9151399A JP 15139997 A JP15139997 A JP 15139997A JP H10341149 A JPH10341149 A JP H10341149A
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- Prior art keywords
- potential
- circuit
- type mosfet
- low
- electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は絶縁ゲート電界効果
型トランジスタ（以下ＭＯＳＦＥＴと略す）を用いた半
導体集積回半導体集積回路装置、もしくは該部品を用い
た装置において、負極性および正極性の計４電位以上の
電源を用い、各回路において異なる電位の低電圧系（小
振幅）の信号を高電位系（大振幅）の信号に変換するレ
ベルシフト回路の構成に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device using an insulated gate field effect transistor (hereinafter abbreviated as a MOSFET) or a device using such parts, which has a negative polarity and a positive polarity. The present invention relates to a configuration of a level shift circuit that converts a low-voltage (small-amplitude) signal having a different potential into a high-potential (large-amplitude) signal in each circuit using a power supply having a potential or higher.
【０００２】[0002]
【従来の技術】従来の代表的なレベルシフト回路は図６
の特公昭５７−５９６９０号公報の如く、片側の信号レ
ベルのみの変換回路であった。あるいは小振幅を大振幅
に変換するという意味においては図７のようにコンパレ
ータ回路、もしくはオペアンプ回路で小振幅を電源の電
位まで増幅して変換していた。2. Description of the Related Art A typical conventional level shift circuit is shown in FIG.
As shown in Japanese Patent Publication No. 57-59690, a conversion circuit for only one signal level is used. Alternatively, in the sense of converting a small amplitude into a large amplitude, a small amplitude is amplified to a power supply potential and converted by a comparator circuit or an operational amplifier circuit as shown in FIG.
【０００３】[0003]
【発明が解決しようとする課題】さて、前述した従来の
片側のレベル信号レベルのみの変換回路では４電位以上
の多電源の回路には適用できないという問題点があっ
た。またコンパレータ回路もしくはオペアンプ回路によ
る方法では常時、多大な電流が流れ続けるという問題点
があった。There is a problem in that the above-described conventional conversion circuit of one side only having a level signal level cannot be applied to a circuit of multiple power supplies having four or more potentials. Further, the method using the comparator circuit or the operational amplifier circuit has a problem that a large amount of current always flows.
【０００４】そこで本発明はこのような問題点を解決す
るもので、その目的とするところは４電位以上の多電源
回路における低電位系（小振幅）の信号を高電位系（大
振幅）の信号に、つまり正極性側も負極性側も同時に変
換し、かつ一度変換された後にはリーク電流が存在しな
い回路構成、つまり低消費電力のレベルシフト回路を提
供することである。Accordingly, the present invention is to solve such a problem. It is an object of the present invention to convert a signal of a low potential system (small amplitude) in a multi-power supply circuit of four or more potentials into a signal of a high potential system (large amplitude). An object of the present invention is to provide a circuit configuration in which a signal, that is, both a positive polarity side and a negative polarity side are converted at the same time, and after conversion once, there is no leakage current, that is, a low power consumption level shift circuit.
【０００５】[0005]
【課題を解決するための手段】本発明の両極性レベルシ
フト回路は、低電位系の電源に接続され、かつ出力端子
にダイオード手段を有した低電位系信号駆動回路と、高
電位系の電源に接続され、インバータ回路をたすきがけ
した高電位系ラッチ回路からなり、前記低電位系信号駆
動回路の信号を前記高電位系ラッチ回路に直接加えたこ
とを特徴とする。According to the present invention, there is provided a bipolar level shift circuit connected to a low potential power supply and having a diode means at an output terminal, and a high potential power supply. And a high-potential-system latch circuit connected to an inverter circuit, and a signal of the low-potential-system signal drive circuit is directly applied to the high-potential-system latch circuit.
【０００６】[0006]
【作用】本発明の上記の構成によれば、高電位系ラッチ
回路はインバータ回路のたすきがけで出来ているので、
低電位系信号駆動回路の信号によって高電位系のラッチ
回路を反転することができる。また、低電位系信号駆動
回路の出力端子にはダイオード手段を有しているので高
電位系の電源から低電位系の電源への逆流が防げる。以
上によりリーク電流のない低消費電力の両極性のレベル
変換ができる。According to the above configuration of the present invention, since the high-potential-system latch circuit is formed by crossing the inverter circuit,
A high-potential latch circuit can be inverted by a signal from the low-potential signal driver circuit. In addition, since the output terminal of the low-potential-system signal drive circuit has a diode means, backflow from the high-potential-system power supply to the low-potential-system power supply can be prevented. As described above, low power consumption bipolar level conversion without leakage current can be performed.
【０００７】[0007]
【発明の実施の形態】以下、実施例により本発明の詳細
を示す。図１は本発明の第１の実施例を示す回路図であ
る。図１において破線２０に囲まれた中の回路は低電位
系信号駆動回路である。低電位系信号駆動回路２０は−
ＶＳＳ１、＋ＶＤＤ１の電源を用いている。破線２３に
囲まれた回路は高電位系ラッチ回路である。高電位系ラ
ッチ回路２３は−ＶＳＳ２、＋ＶＤＤ２の電源を用いて
いる。ここで−ＶＳＳ２、−ＶＳＳ１、＋ＶＤＤ１、＋
ＶＤＤ２の各電源電位の関係を図示したのが図２であ
る。図２において−ＶＳＳ２は負極性の第２電源電位、
−ＶＳＳ１は負極性の第１電源電位、＋ＶＤＤ１は正極
性の第１電源電位、＋ＶＤＤ２は正極性の第２電位であ
る。さて、図１の破線２０の中において１１、１２はＰ
型ＭＯＳＦＥＴであり、１３、１４はＮ型ＭＯＳＦＥＴ
である。Ｐ型ＭＯＳＦＥＴ１１のソース電極は＋Ｖ
ＤＤ１に接続され、ドレイン電極はＰ型ＭＯＳＦＥＴ１
２のソース電極に接続されている。Ｐ型ＭＯＳＦＥＴ１
２のゲート電極とドレイン電極は互いに接続されてい
る。Ｎ型ＭＯＳＦＥＴ１３のソース電極は−ＶＳＳ１に
接続され、ドレイン電極はＮ型ＭＯＳＦＥＴ１４のソー
ス電極に接続されている。Ｎ型ＭＯＳＦＥＴ１４のゲー
ト電極とドレイン電極は互いに接続され、かつＰ型ＭＯ
ＳＦＥＴ１２のドレイン電極に接続されているとともに
低電位系信号駆動回路２０の出力端子２２となってい
る。またＰ型ＭＯＳＦＥＴ１１とＮ型ＭＯＳＦＥＴ１３
のそれぞれのゲート電極は互いに接続されれ、かつ低電
位系信号駆動回路２０の入力端子２１となっている。な
お、ＭＯＳＦＥＴ１１、１２、１５、１６、１７、１８
の基板電位はソース電位と同一電位となるように接続さ
れているが、ＭＯＳＦＥＴ１２、１４は例外であって、
Ｐ型ＭＯＳＦＥＴ１２の基板は＋ＶＤＤ２に、Ｎ型ＭＯ
ＳＦＥＴ１４の基板は−ＶＳＳ２に接続されている。ま
た、破線２３の中において、１５、１６はＰ型ＭＯＳＦ
ＥＴであり、Ｎ型ＭＯＳＦＥＴ１７、１８はＮ型ＭＯＳ
ＦＥＴである。Ｐ型ＭＯＳＦＥＴ１５、１６のソース電
極は＋ＶＤＤ２に接続されている。Ｎ型ＭＯＳＦＥＴ１
７、１８のソース電極は−ＶＳＳ２に接続されている。
Ｐ型ＭＯＳＦＥＴ１５とＮ型ＭＯＳＦＥＴ１７のゲート
電極とドレイン電極はともにそれぞれ接続され、第１の
インバータ回路を形成している。またＰ型ＭＯＳＦＥＴ
１６とＮ型ＭＯＳＦＥＴ１８のゲート電極とドレイン電
極はともにそれぞれ接続され、第２のインバータ回路を
形成している。また第１のインバータ回路の出力端子は
高電位系ラッチ回路２３の反転出力端子２４となってい
るとともに第２のインバータ回路のゲート入力端子に接
続されている。また第２のインバータ回路の出力端子は
高電位系ラッチ回路２３の出力端子２５となっていると
ともに第１のインバータ回路のゲート入力端子に接続さ
れている。DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail with reference to examples. FIG. 1 is a circuit diagram showing a first embodiment of the present invention. In FIG. 1, a circuit surrounded by a broken line 20 is a low-potential-system signal driving circuit. The low potential signal drive circuit 20
V SS1, are using the power of + V DD1. A circuit surrounded by a broken line 23 is a high potential latch circuit. The high-potential-system latch circuit 23 uses a power supply of -VSS2 and + VDD2 . Here, -VSS2 , -VSS1 , + VDD1 , +
FIG. 2 illustrates the relationship between the power supply potentials of VDD2 . In FIG. 2, -VSS2 is a second power supply potential of negative polarity,
-VSS1 is a negative first power supply potential, + VDD1 is a positive first power supply potential, and + VDD2 is a positive second potential. By the way, in the broken line 20 in FIG.
13 and 14 are N-type MOSFETs
It is. The source electrode of the P-type MOSFET 11 is + V
DD1 and the drain electrode is a P-type MOSFET1
2 source electrodes. P-type MOSFET1
The gate electrode and the drain electrode are connected to each other. The source electrode of the N type MOSFET13 are connected to -V SS1, the drain electrode is connected to the source electrode of the N-type MOSFET 14. The gate electrode and the drain electrode of the N-type MOSFET 14 are connected to each other, and
It is connected to the drain electrode of the SFET 12 and serves as an output terminal 22 of the low-potential signal drive circuit 20. P-type MOSFET 11 and N-type MOSFET 13
Are connected to each other and serve as input terminals 21 of the low-potential-system signal drive circuit 20. The MOSFETs 11, 12, 15, 16, 17, 18
Are connected so as to have the same potential as the source potential, except for MOSFETs 12 and 14,
The substrate of the P-type MOSFET 12 is connected to + V DD2 and the N-type
Substrate SFET14 is connected to the -V SS2. In the broken line 23, 15 and 16 are P-type MOSFs.
ET, and N-type MOSFETs 17 and 18 are N-type MOS
FET. The source electrode of the P-type MOSFET15,16 is connected to + V DD2. N-type MOSFET1
Source electrodes 7 and 18 are connected to -VSS2 .
The gate electrode and the drain electrode of the P-type MOSFET 15 and the N-type MOSFET 17 are both connected to each other to form a first inverter circuit. Also P-type MOSFET
The gate electrode and the drain electrode of the N-type MOSFET 16 and the N-type MOSFET 18 are connected together to form a second inverter circuit. The output terminal of the first inverter circuit is the inverted output terminal 24 of the high-potential latch circuit 23 and is connected to the gate input terminal of the second inverter circuit. The output terminal of the second inverter circuit is the output terminal 25 of the high-potential latch circuit 23 and is connected to the gate input terminal of the first inverter circuit.
【０００８】さて、低電位系信号駆動回路２０の入力端
子２１に正の極性の信号が入力したとすると、出力端子
２２には−ＶＳＳ１もしくはＮ型ＭＯＳＦＥＴ１４のス
レッショルド電圧分だけ降下（上昇）した電位が発生
し、高電位系ラッチ回路２３の反転出力端子２４に加わ
る。このとき、Ｐ型ＭＯＳＦＥＴ１５の駆動能力より、
Ｎ型ＭＯＳＦＥＴ１３、１４の駆動能力を充分に高く設
定しておくと、Ｐ型ＭＯＳＦＥＴ１６とＮ型ＭＯＳＦＥ
Ｔ１８からなる第２のインバータ回路は反転して出力端
子２５に＋ＶＤＤ２を出力するとともにＰ型ＭＯＳＦＥ
Ｔ１５とＮ型ＭＯＳＦＥＴ１７からなる第１のインバー
タ回路も反転して反転出力端子２４は−ＶＳＳ２とな
る。なお、このときＮ型ＭＯＳＦＥＴ１４のソース電極
とドレイン電極に−ＶＳＳ２と−ＶＳＳ１が加わること
になるが、ゲート電極が接続されている電極側に−Ｖ
ＳＳ２が加わっているので電流が流れることはない。低
電位系信号駆動回路２０の入力端子２１に負の極性の信
号が入力した場合には以上のほぼ逆なことが起こり、出
力端子２５には＋ＶＤＤ２が出力され、Ｐ型ＭＯＳＦＥ
Ｔ１２のソース電極とドレイン電極に＋ＶＤＤ２と＋Ｖ
ＤＤ１が加わることになるが、ゲート電極が接続されて
いる電極側に＋ＶＤＤ２が加わっているので電流が流れ
ることはない。以上より、−ＶＳＳ１、＋ＶＤＤ１の低
電位系信号駆動回路２０の信号が高電位系ラッチ回路２
３を経ることにより、−ＶＳＳ２、＋ＶＤＤ２の信号に
置き変わり、かつ静止状態においてはリーク電流の生じ
ない両極性のレベルシフト回路となっていることが解
る。If a signal having a positive polarity is input to the input terminal 21 of the low-potential-system signal drive circuit 20, the output terminal 22 drops (rises) by -VSS1 or the threshold voltage of the N-type MOSFET 14. A potential is generated and applied to the inverting output terminal 24 of the high potential latch circuit 23. At this time, due to the driving capability of the P-type MOSFET 15,
If the driving capabilities of the N-type MOSFETs 13 and 14 are set sufficiently high, the P-type MOSFET 16 and the N-type MOSFET
P-type MOSFE with the second inverter circuit consisting of T18 and outputs the + V DD2 to the output terminal 25 is inverted
T15 in the first inverter circuit inverting an output terminal 24 be inverted of N type MOSFET17 becomes -V SS2. At this time, -VSS2 and -VSS1 are applied to the source electrode and the drain electrode of the N-type MOSFET 14, but -V SS2 is applied to the electrode side to which the gate electrode is connected.
Since SS2 is added, no current flows. When a signal of a negative polarity is input to the input terminal 21 of the low-potential-system signal drive circuit 20, the reverse of the above occurs substantially, and + V DD2 is output to the output terminal 25, and the P-type MOSFE
+ V DD2 and + V are applied to the source and drain electrodes of T12.
Although DD1 is applied, no current flows because + V DD2 is applied to the electrode side to which the gate electrode is connected. From the above, -V SS1, + signal of the low-potential system signal driving circuit 20 of V DD1 a high potential system latch circuit 2
It can be seen that after going through 3, the signal is replaced with the signals of -VSS2 and + VDD2 , and the bipolar level shift circuit does not generate a leak current in the stationary state.
【０００９】図３は本発明の第２の実施例である。図３
の破線で示す低電位系信号駆動回路３０の中の３２、３
４はＰ＋拡散とＮ＋拡散からなるダイオードであり、図
１のＭＯＳＦＥＴ１２、１４を置き換えたものである。FIG. 3 shows a second embodiment of the present invention. FIG.
32, 3 in the low-potential-system signal drive circuit 30 indicated by the broken line
Reference numeral 4 denotes a diode composed of P + diffusion and N + diffusion, which replaces the MOSFETs 12 and 14 in FIG.
【００１０】図４は本発明の第３の実施例である。図４
において、４０、４１はともに低電位系信号駆動回路で
ある。第１の低電位系信号駆動回路４０は図１の回路と
同様であるが、図４の第２の低電位系信号駆動回路４１
の入力端子にはインバータ回路４９を通した反転信号が
加えられ、出力端子４６は高電位系ラッチ回路４３の出
力端子４５に加えられている。この回路手法では高電位
系ラッチ回路４３に二本の差動信号が入力するので応答
性が高まる特長がある。FIG. 4 shows a third embodiment of the present invention. FIG.
, 40 and 41 are low-potential-system signal drive circuits. The first low-potential-system signal drive circuit 40 is the same as the circuit of FIG.
The inverted signal passed through the inverter circuit 49 is applied to the input terminal of the high-potential system latch circuit 43, and the output terminal 46 is applied to the output terminal 45 of the high-potential latch circuit 43. This circuit method has a feature that the responsiveness is improved because two differential signals are input to the high-potential-system latch circuit 43.
【００１１】図５は本発明の第４の実施例である。図５
においては図４のインバータ回路４９を省略して第１の
低電位系信号駆動回路５０から第２の低電位系信号駆動
回路５１の入力信号を得ている。この回路は図４の回路
に比較して若干素子数が減少する特長がある。FIG. 5 shows a fourth embodiment of the present invention. FIG.
In FIG. 4, the input signal of the second low-potential-system signal driving circuit 51 is obtained from the first low-potential-system signal driving circuit 50 by omitting the inverter circuit 49 of FIG. This circuit has a feature that the number of elements is slightly reduced as compared with the circuit of FIG.
【００１２】また、以上は計４電位の場合を説明してき
たが、５電位以上であってその間のレベル変換であって
もよい。In the above description, the case of a total of four potentials has been described. However, a level conversion of five potentials or more may be used.
【００１３】[0013]
【発明の効果】以上、述べたように本発明によれば、低
電位系（小振幅）の信号を高電位系（大振幅）の信号に
正極側と負極側同時に変換できるという効果がある。As described above, according to the present invention, there is an effect that a signal of a low potential system (small amplitude) can be simultaneously converted into a signal of a high potential system (large amplitude) on the positive electrode side and the negative electrode side.
【００１４】また、動作が終了した静止状態においては
リーク電流が流れず、低消費電力であるという効果があ
る。Further, there is an effect that no leakage current flows in the stationary state where the operation is completed, and the power consumption is low.
【図１】本発明の第１の実施例を示す回路図である。FIG. 1 is a circuit diagram showing a first embodiment of the present invention.
【図２】本発明が使用される多電源系の各電位の関係を
示した電位関係図である。FIG. 2 is a potential relationship diagram showing a relationship between respective potentials of a multiple power supply system in which the present invention is used.
【図３】本発明の第２の実施例を示す回路図である。FIG. 3 is a circuit diagram showing a second embodiment of the present invention.
【図４】本発明の第３の実施例を示す回路図である。FIG. 4 is a circuit diagram showing a third embodiment of the present invention.
【図５】本発明の第４の実施例を示す回路図である。FIG. 5 is a circuit diagram showing a fourth embodiment of the present invention.
【図６】従来例のレベルシフト回路を示す回路図であ
る。FIG. 6 is a circuit diagram showing a conventional level shift circuit.
【図７】従来例の小振幅を大振幅に変換する回路例を示
す回路図である。FIG. 7 is a circuit diagram showing an example of a conventional circuit for converting a small amplitude into a large amplitude.
１１、１２、１５、１６・・・Ｐ型ＭＯＳＦＥＴ １３、１４、１７、１８・・・Ｎ型ＭＯＳＦＥＴ ２０、３０、４０、４１、５０、５１・・・低電位系信
号駆動回路 ２１、２２、２４、２５、４５、４６・・・端子 ２３、４３・・・高電位系ラッチ回路 ４９・・・インバータ回路11, 12, 15, 16 ... P-type MOSFET 13, 14, 17, 18 ... N-type MOSFET 20, 30, 40, 41, 50, 51 ... Low-potential-system signal drive circuit 21, 22, 24, 25, 45, 46 terminal 23, 43 high-potential latch circuit 49 inverter circuit
Claims (5)
源電位を有する絶縁ゲート電界効果型トランジスタ（以
下ＭＯＳＦＥＴと略す）を用いた半導体集積回路装置に
おいて、 ｂ）第４電位の電源にソース電位を接続した第１、第２
Ｐ型ＭＯＳＦＥＴと第１電位の電源にソース電位を接続
した第１、第２Ｎ型ＭＯＳＦＥＴとからなり、前記第１
Ｐ型ＭＯＳＦＥＴと第１Ｎ型ＭＯＳＦＥＴのそれぞれの
ゲート電極、およびドレイン電極は互いに接続され第１
インバータ回路を形成し、前記第２Ｐ型ＭＯＳＦＥＴと
第２Ｎ型ＭＯＳＦＥＴのそれぞれのゲート電極、および
ドレイン電極は互いに接続され第２インバータ回路を形
成し、該第１、第２インバータ回路の入力端子となるゲ
ート電極と出力端子となるドレイン電極はそれぞれ互い
にたすきがけに接続されている以上の構成からなる高電
位系ラッチ回路と、 ｃ）第３電位の電源にソース電極を接続した第３Ｐ型Ｍ
ＯＳＦＥＴと、前記第３Ｐ型ＭＯＳＦＥＴのドレイン電
極に正側の電極を接続した第１のダイオード手段と、前
記第１のダイオード手段の負側の電極に正側の電極を接
続した第２のダイオード手段と、前記第２のダイオード
手段の負側の電極にドレイン電極を接続し、かつソース
電極は第２電位の電源に接続した第３Ｎ型ＭＯＳＦＥＴ
とからなり、前記第３Ｐ型ＭＯＳＦＥＴと第３Ｎ型ＭＯ
ＳＦＥＴのゲート電極は互いに接続され低電位系の信号
入力端子となり、前記第１のダイオードと第２のダイオ
ードの接続点が出力端子となっている以上の構成からな
る低電位系信号駆動回路とからなり、 ｄ）前記低電位系信号駆動回路の出力端子が前記高電位
系ラッチ回路の反転出力端子に接続されていることを特
徴とする両極性レベルシフト回路。1. A semiconductor integrated circuit device using an insulated gate field effect transistor (hereinafter abbreviated as a MOSFET) having first, second, third and fourth power supply potentials. First and second power sources connected to a four-potential power source
A first N-type MOSFET having a source potential connected to a power source of a first potential;
The gate electrode and the drain electrode of the P-type MOSFET and the first N-type MOSFET are connected to each other and
An inverter circuit is formed, and a gate electrode and a drain electrode of the second P-type MOSFET and the second N-type MOSFET are connected to each other to form a second inverter circuit, which is an input terminal of the first and second inverter circuits. A high-potential-system latch circuit having a configuration in which a gate electrode and a drain electrode serving as an output terminal are connected to each other at a cross-point; and c) a third P-type M in which a source electrode is connected to a third potential power supply.
An OSFET, first diode means having a positive electrode connected to the drain electrode of the third P-type MOSFET, and second diode means having a positive electrode connected to the negative electrode of the first diode means. And a third N-type MOSFET having a drain electrode connected to the negative electrode of the second diode means and a source electrode connected to a power supply of a second potential.
And the third P-type MOSFET and the third N-type MO
The gate electrodes of the SFETs are connected to each other to serve as a low-potential signal input terminal, and a low-potential-system signal driving circuit having a configuration in which the connection point between the first diode and the second diode serves as an output terminal. D) The bipolar level shift circuit, wherein an output terminal of the low-potential-system signal drive circuit is connected to an inverted output terminal of the high-potential-system latch circuit.
極とドレイン電極を互いに接続したＭＯＳＦＥＴからな
ることを特徴とする両極性レベルシフト回路。2. A bipolar level shift circuit according to claim 1, wherein said diode means comprises a MOSFET having a gate electrode and a drain electrode connected to each other.
源電位を有する絶縁ゲート電界効果型トランジスタ（以
下ＭＯＳＦＥＴと略す）を用いた半導体集積回路装置に
おいて、 ｂ）第４電位の電源にソース電位を接続した第１、第２
Ｐ型ＭＯＳＦＥＴと第１電位の電源にソース電位を接続
した第１、第２Ｎ型ＭＯＳＦＥＴとからなり、前記第１
Ｐ型ＭＯＳＦＥＴと第１Ｎ型ＭＯＳＦＥＴのそれぞれの
ゲート電極、およびドレイン電極は互いに接続され第１
インバータ回路を形成し、前記第２Ｐ型ＭＯＳＦＥＴと
第２Ｎ型ＭＯＳＦＥＴのそれぞれのゲート電極、および
ドレイン電極は互いに接続され第２インバータ回路を形
成し、該第１、第２インバータ回路の入力端子となるゲ
ート電極と出力端子となるドレイン電極はそれぞれ互い
にたすきがけに接続されている以上の構成からなる高電
位系ラッチ回路と、 ｃ）第３電位の電源にソース電極を接続した第３Ｐ型Ｍ
ＯＳＦＥＴと、前記第３Ｐ型ＭＯＳＦＥＴのドレイン電
極に正側の電極を接続した第１のダイオード手段と、前
記第１のダイオード手段の負側の電極に正側の電極を接
続した第２のダイオード手段と、前記第２のダイオード
手段の負側の電極にドレイン電極を接続し、かつソース
電極は第２電位の電源に接続した第３Ｎ型ＭＯＳＦＥＴ
とからなり、前記第３Ｐ型ＭＯＳＦＥＴと第３Ｎ型ＭＯ
ＳＦＥＴのゲート電極は互いに接続され低電位系の信号
入力端子となり、前記第１のダイオードと第２のダイオ
ードの接続点が出力端子となっている以上の構成からな
る第１低電位系信号駆動回路と、 ｄ）第３電位の電源にソース電極を接続した第４Ｐ型Ｍ
ＯＳＦＥＴと、前記第４Ｐ型ＭＯＳＦＥＴのドレイン電
極に正側の電極を接続した第３のダイオード手段と、前
記第３のダイオード手段の負側の電極に正側の電極を接
続した第４のダイオード手段と、前記第４のダイオード
手段の負側の電極にドレイン電極を接続し、かつソース
電極は第２電位の電源に接続した第４Ｎ型ＭＯＳＦＥＴ
とからなり、前記第４Ｐ型ＭＯＳＦＥＴと第４Ｎ型ＭＯ
ＳＦＥＴのゲート電極は互いに接続され低電位系の信号
入力端子となり、前記第３のダイオードと第４のダイオ
ードの接続点が出力端子となっている以上の構成からな
る第２低電位系信号駆動回路とからなり、 ｅ）前記第２低電位系信号駆動回路の入力端子には前記
第１低電位系信号駆動回路の入力端子とは反転した信号
が加えられ、前記第１低電位系信号駆動回路の出力端子
が前記高電位系ラッチ回路の反転出力端子に接続され、
前記第２低電位系信号駆動回路の出力端子が前記高電位
系ラッチ回路の出力端子に接続されていることを特徴と
する両極性レベルシフト回路。3. A semiconductor integrated circuit device using an insulated gate field effect transistor (hereinafter abbreviated as a MOSFET) having power supply potentials of first, second, third, and fourth potentials. First and second power sources connected to a four-potential power source
A first N-type MOSFET having a source potential connected to a power source of a first potential;
The gate electrode and the drain electrode of the P-type MOSFET and the first N-type MOSFET are connected to each other and
An inverter circuit is formed, and a gate electrode and a drain electrode of the second P-type MOSFET and the second N-type MOSFET are connected to each other to form a second inverter circuit, which is an input terminal of the first and second inverter circuits. A high-potential-system latch circuit having a configuration in which a gate electrode and a drain electrode serving as an output terminal are connected to each other at a cross-point; and c) a third P-type M in which a source electrode is connected to a third potential power supply.
An OSFET, first diode means having a positive electrode connected to the drain electrode of the third P-type MOSFET, and second diode means having a positive electrode connected to the negative electrode of the first diode means. And a third N-type MOSFET having a drain electrode connected to the negative electrode of the second diode means and a source electrode connected to a power supply of a second potential.
And the third P-type MOSFET and the third N-type MO
A first low-potential-system signal drive circuit having a configuration in which the gate electrodes of the SFETs are connected to each other to serve as a low-potential-system signal input terminal, and the connection point between the first diode and the second diode serves as an output terminal. And d) a fourth P-type M having a source electrode connected to a power supply of a third potential.
An OSFET, third diode means having a positive electrode connected to the drain electrode of the fourth P-type MOSFET, and fourth diode means having a positive electrode connected to the negative electrode of the third diode means. And a fourth N-type MOSFET having a drain electrode connected to the negative electrode of the fourth diode means and a source electrode connected to a power supply of a second potential.
The fourth P-type MOSFET and the fourth N-type MO
A second low-potential-system signal drive circuit having a configuration in which the gate electrodes of the SFETs are connected to each other to serve as a low-potential-system signal input terminal, and the connection point between the third diode and the fourth diode serves as an output terminal. E) a signal inverted from the input terminal of the first low-potential-system signal drive circuit is applied to the input terminal of the second low-potential-system signal drive circuit, and Is connected to the inverted output terminal of the high-potential latch circuit,
An output terminal of the second low-potential-system signal drive circuit is connected to an output terminal of the high-potential-system latch circuit.
極とドレイン電極を互いに接続したＭＯＳＦＥＴからな
ることを特徴とする両極性レベルシフト回路。4. A bipolar level shift circuit according to claim 3, wherein said diode means comprises a MOSFET having a gate electrode and a drain electrode connected to each other.
の入力端子に加えられる信号が第１低電位系信号駆動回
路から形成されることを特徴とする両極性レベルシフト
回路。5. A bipolar level shift circuit according to claim 3, wherein the signal applied to the input terminal of the second low-potential-system signal drive circuit is formed from the first low-potential-system signal drive circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15139997A JP3624629B2 (en) | 1997-06-09 | 1997-06-09 | Bipolar level shift circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15139997A JP3624629B2 (en) | 1997-06-09 | 1997-06-09 | Bipolar level shift circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH10341149A true JPH10341149A (en) | 1998-12-22 |
| JP3624629B2 JP3624629B2 (en) | 2005-03-02 |
Family
ID=15517747
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15139997A Expired - Fee Related JP3624629B2 (en) | 1997-06-09 | 1997-06-09 | Bipolar level shift circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3624629B2 (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001211065A (en) * | 2000-01-26 | 2001-08-03 | Sanyo Electric Co Ltd | Level shift circuit |
| JP2005150989A (en) * | 2003-11-13 | 2005-06-09 | New Japan Radio Co Ltd | Level shift circuit |
| US7049876B2 (en) | 2004-10-25 | 2006-05-23 | Delphi Technologies, Inc. | Level shift circuits and related methods |
| JP2008067224A (en) * | 2006-09-08 | 2008-03-21 | Fuji Electric Device Technology Co Ltd | Level shift circuit and dc/dc converter |
| CN106899289A (en) * | 2017-02-23 | 2017-06-27 | 电子科技大学 | A kind of controllable type level displacement circuit |
-
1997
- 1997-06-09 JP JP15139997A patent/JP3624629B2/en not_active Expired - Fee Related
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001211065A (en) * | 2000-01-26 | 2001-08-03 | Sanyo Electric Co Ltd | Level shift circuit |
| JP2005150989A (en) * | 2003-11-13 | 2005-06-09 | New Japan Radio Co Ltd | Level shift circuit |
| US7049876B2 (en) | 2004-10-25 | 2006-05-23 | Delphi Technologies, Inc. | Level shift circuits and related methods |
| JP2008067224A (en) * | 2006-09-08 | 2008-03-21 | Fuji Electric Device Technology Co Ltd | Level shift circuit and dc/dc converter |
| CN106899289A (en) * | 2017-02-23 | 2017-06-27 | 电子科技大学 | A kind of controllable type level displacement circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3624629B2 (en) | 2005-03-02 |
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