JPS62105427A - Manufacture of glass-coated semiconductor chip - Google Patents

Abstract

PURPOSE:To reduce the unnecessary use of glass material to no avail as well as to decrease the generation of poor characteristics in reverse direction such as the deterioration in bias and the like by a method wherein a glass-coated layer is not formed on all over the main surface of a semiconductor substrate, and the glass-coated layer is formed only on the surface and the circumferential part of a groove. CONSTITUTION:SiO2 films 12 and 13 are formed by thermal oxidization on the main surface of a silicon substrate 1 consisting of an N<+> type substrate region 2, an N-type region 3 and a P<+> type region 4. A deep groove 6 reaching the N<+> type region 2 is formed in a shallow groove 14, and a P-N junction 5 is exposed. Then, a glass-coated layer 7 is formed on the surface of the grooves 6 and 14 by performing an electrophotoretic method. Subsequently, the circumferential part of the glass-coated layer 7 is removed by performing a selective etching using the mixed acid of hydrofluoric acid and hydrochloric acid, and at the same time, the SiO2 film 12 is also removed by etching, and an aperture 8 to be used for electrode is formed. Then, Ni electrodes 9 and 10 are formed in the aperture part 8 on the remaining part 7a of the glass-coated layer 7 and the lower surface of the substrate 1 by performing an electroless plating method. Then, the substrate 1 is cut along a groove 15 which functions as a marker line, and it is separated into diode chips 11c.

Description

DETAILED DESCRIPTION OF THE INVENTION [Eleventh Industrial Field] The present invention relates to a method of manufacturing a glass-covered semiconductor chip such as a diode chip in which a pn junction extending through a groove sK is covered with glass.

[Conventional technology]

Typical manufacturing methods for glass-covered diode chips include the method shown in Figure 7 and the method shown in Figure 8. n
n on the type substrate region (2) by epitaxial growth.
A silicon substrate provided with a mold region (3) is prepared. Next, boron is diffused to form an n-type region (41), and gold is further diffused as a lifetime killer. After the three-layer structure is formed, the thickness of each region is equal to that of the p-type region (4
) is 20 μm, the n-type region (3; is 20 μm, and the n-type substrate region (21) is 240 μm. In this diode.

Reach-through breakdown (when reverse voltage EJJ is applied, p-n junction (5
The depletion 1- extending from ; to the n-type region (3) as a king is n
The specific resistance and thickness of the n-type region (3) are set so that the resistance to F is determined by the breakdown dust phenomenon that occurs upon reaching the type region (2).

Next, as shown in FIG. 7 (B+), a groove (61) reaching the n-type region (21) is formed by etching using a hydrofluoric acid-nitric acid mixture. Junction +51 pieces are exposed.

Next, as shown in FIG. 7, a glass coating layer (71) made of passivation glass made of PbO thread is grown on the main surface of the silicon substrate (1) having grooves (61).

In addition, the glass coating layer (7) is formed by a method of forming a glass layer with a relatively uniform thickness even on a flat or non-flat surface. Then, an electric field is generated in the solution using a silicon substrate placed in a solution as an electrode. It is formed by attaching a glass powder to a substrate, followed by heat treatment and firing of the glass powder.

Next, as shown in FIG. 7), the diglass substrate M1 (717) is etched with a mixed acid of hydrofluoric acid and hydrochloric acid to form an opening +81 for the electrode.

Next, as shown in FIG. 7 IE+, Ni @pole 19+ is applied to the exposed silicon surface of the substrate (1) by electroless plating.
001 is formed. Then, at the bottom of the groove 5 (61), the substrate t
Cut xt and diode chip +1la) Y5'2
make it happen

- 10,000, in another conventional method shown in FIG.

As shown in FIG. Prepare, pUo
S by thermal oxidation 40. A film 021 (13) is formed.

next,#! As shown in Figure 8 (Bl), the fc groove (6) is provided as in Figure 7 (81).

next,#! As shown in Figure 8m8, the glass coating layer (7) is formed by the R4 pneumophoresis method. In the electrophoresis method, 8i0. Membrane a′L! Since the glass powder does not adhere to the soil in the Ja row, a glass coating layer (7) is selectively formed on the groove (61).
In addition, a glass coating layer (71) is also formed around the membrane opening (71) by an end electric field concentration effect frame in the electrophoresis method.

Next, as shown in Figure 8), Ji! Remove 8701 film 07JY by etching leaving 1 side edge 1. At this time, form a hole (81) for the electrode.

Sin and film α leakage on the lower surface of the substrate ill are also removed.

Next, as shown in the 8th mm, an electrode hole is formed, the cutting groove (6) is adjusted, and a diode chip (llb) is formed.
) Kaoru is completed.

[The problem that the invention attempts to solve]

In the conventional method shown in FIG. 7, a thick glass coating layer (7) is formed on the upper surface of the n-type region, but a glass coating layer (7) is not formed on the surface of the groove (6), which is important as a passivation film. The layer (7) is formed to be relatively thin. Therefore, in order to form the glass coating layer (71) into a groove (61) with a sufficient thickness without pinholes, the n-type region (4) must be
A glass coating layer (7) is formed around the required circumference on the upper surface. Therefore, the glass material is wasted and the working time for the glass nuclide is extended.

- The sword, according to the conventional method of Fig. 8, is roughly resolved between the methods of Fig. 7. 1-7 or 1. Therefore, in diode products that are tabulated using the method shown in Fig. 8, and that use chip 1llb3k, symmetry (hereinafter referred to as bias deterioration) is likely to occur, in which the withstand voltage deteriorates during application of reverse turtle pressure. found. Bias deterioration is 1. When a reverse voltage group is added, a p-n junction (51
In a reach-through breakdown type product, the depletion layer extending from the n-type region (21) is designed to break down before reaching the n-type region (21).
It was clearly observed. Sota, n-type region (41 often occurred when shallow).

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a method for easily manufacturing a glass conductor chip having excellent reverse direction characteristics and reliability.

[Means to resolve disputes]

A method for manufacturing a glass-coated semiconductor chip according to the present invention in order to solve the above-mentioned problems and achieve the objectives of the present invention is as follows:
A step of forming at least one pn junction on a semiconductor substrate and forming an insulating film on the semiconductor substrate, and forming a groove at a depth to expose the pn junction on one main surface of the semiconductor substrate. (form the finale.

Before or after the formation of the groove C, the insulating film is removed from the periphery of the groove C, and the surface of the groove and the periphery of the groove from which the insulating film has been removed are coated with a horizontal plane. A protective glass layer thicker than the insulating film is formed in one step, and a part of the glass layer surrounding the groove and the ilP! A step of forming an open locus enclosed in the remainder of the previous day's pygalus nuclide by simultaneously or separately removing the membrane.

4. A step of forming an electrode on the surface of the semiconductor substrate exposed by the opening, and a step of cutting the conductor substrate outside the front groove or the groove.

[Function] In the method of the present invention described above, the glass covering a layer is not formed over the entire main surface of a part of the semiconductor substrate.

Compared to the conventional 7J method shown in FIG. 7, there is less waste of glass material and the working time for glass nuclides is shorter. Moreover, Mll of the groove
Since there is no insulating film on the edge, there is less occurrence of reverse characteristic defects such as bias deterioration compared to the conventional method of factor 8.
stomach.

〔Example〕

Next, a method for manufacturing a glass nuclide diode chip according to an embodiment of the present invention will be described with reference to FIGS. 1 to 5.

As shown in Figure 1, the n-type board thin wire (
21, an n-type region (3), and a p-type region (41), and the other main surface is thermally oxidized with S.
In, those with membrane 0Z03 are shown in Figure 8 (false) and inner 1M.
! It is formed in

Next, as shown in Figure 1 (Bl), shallow grooves were formed on the soil surface of the substrate (11) by etching using a mixed acid of hydrofluoric acid and nitric acid, and at the same time, leakage markers were placed on the bottom surface of the substrate (11). Form the floor @a for the line.The groove on the soil surface is old!

p+ type @ Hani (part of 41 has been removed, but 8i
0. Since the purpose is to remove the film U force, it is formed sufficiently shallow so as not to expose the pn junction (5). Furthermore, the matu of C is 810. It is formed in an annular shape so that the film Q41 remains in an island shape. @a~ on the bottom surface provides a marker line when cutting the substrate (11) into a plurality of chips.

Next, as shown in FIG. 1 (O) and FIG.
A deep groove (6) different from the mold region (21) is formed to expose the pn junction (5). Therefore, 5iO1 film O2
remains in the form of an island, with grooves +61 (141) forming a circular ring.

Next, as shown in FIG. 1, a glass coating layer (7) is formed on the surface of the groove (6) by electrophoresis. Almost no glass layer (7) is formed except in the surrounding area.
, Inglobil alcohol is used as #M,
An ammonia casing or a dedicated surfactant is used as the electrolyte to charge the glass powder bed.

Next, as shown in Fig. 1 (sleeve), a portion (part) of the periphery of the glass laminated layer (71) was selectively etched away using a mixed acid of hydrofluoric acid and hydrochloric acid, and at the same time, all of the yc, 8i0, and film aZ were also etched. Remove the opening (8) for the electrode.

At the same time as S+0 on the bottom surface of substrate +II. The film (13) is also etched away.

Next, as shown in Fig. 1 jp+ and Fig. 3, <,! li board +
The opening (within 81) of the glass covered layer (remaining part (7a) of 71) on the soil surface of No. 11.

A Ni electrode (91a) was formed on the bottom surface of the substrate (1) by a fM fieldless plating method, and then the substrate (1) was cut along the marker line and the groove rows (7) to form individual diode chips. Separate into (llc).

When the diode chip (IIC) is manufactured by the method shown in Figs. 1 to 3, glass powder is attached only to the groove (6) and its periphery, so there is less waste of glass material, and there is no work required to attach the glass powder. The time is right. It was a cabinet. The thickness of the periphery of the glass remaining portion (7a), that is, the periphery of the opening (8) is thinner than in the conventional method shown in FIG.
81'! It is superior to the conventional method shown in FIG. 7 in terms of 'f# degree and ladle-likeness. Call me, Sin.

Since there is no mG force remaining, there are fewer defects in the reverse direction!
Bias deterioration is significantly reduced to 12%, and it is clearly superior to the conventional example shown in FIG. 8 in terms of characteristics and reliability.

The reason for the decrease in reverse direction defects is not clearly defined, but it is thought to be of the first order. FIG. 8 (The conventional diode chip of FIG. 4 showing an enlarged view of a part of D (iib)
), since the thermal expansion coefficient of Sin and membrane zero force is about an order of magnitude smaller than that of Sinofun, S10. There is residual strain near the interface between the film a force and the p+ type region 141 due to the difference in thermal expansion coefficients of (t''I, etc.).This residual strain is
It occurs concentrated at the edge 112a) where the film has zero force, and the influence of residual φ on the silicon crystal remains in the vicinity of the 11th wire, and when the influence of residual strain reaches the pn junction dimension, it becomes a reverse failure mode. It's dusty. In particular, since the region (Itil) is located at the corner of the boundary between the main surface of the silicon crystal and the 1111 plane, the silicon crystal is exposed to the influence of residual strain.

There is a high probability that residual strain will affect the pn junction (51) [2
In addition, the surface of the groove (6) including the exposed portion (5a) of the p-n junction (5), which has a large effect on characteristic fluctuations, is 810. The edge of the membrane (1
Since it is close to 2a), there is a high probability that the influence of residual φ will be exerted. In fact, the influence of the potential caused by glass charges such as Na ions present in the 8-layer Oa also affects the surface of the groove (6), contributing to the reverse failure mode.

- In the case of the diode chip (IIC) in Figure 25, which shows an enlarged view of part i in Figure 1 (b), the Srow film 021
is being removed. Therefore, the negative reputation of residual distortion and electric charge≦
Therefore, the occurrence of reverse direction failure mode is less tr(
Become.

[Modified example]

The invention is not limited to the embodiments described above.

For example, the following variants are possible.

lal * Form Q4J and make a p type porcelain (without etching at 41 cm,
Only the film oz was removed by etching as shown in Figure 6.
The remainder of the glass encrusting layer (7
a) and a diode chip (l) as shown in FIG.
id) may be created. In the case of Tashiko, 8rOH
Since it is not possible to perform the etching of 12+ at the same time as the formation process of T10!il, when forming I!I! A series of selective etching steps (image, etching, photoresist removal) will be added once.

(bl groove (I41 etching process or S102 win (1) corresponding to groove 041 as shown in Figure 6)
The etching process 21 may be performed as a post-step process for forming the deep grooves 61.

+CI Although we have shown an example of using an epitaxial rubber as the silicon base &+1+, it is also possible to form a p-n-n" three-layer diode structure by forming a p-type region and an n-type region on an n-type substrate by impurity diffusion. You may give it.

(The present invention can be applied to transistors and thyristors other than diodes.In the case of a type of semiconductor chip whose breakdown voltage is specified by a single-chip breakdown in 15 cm, the present invention has a remarkable improvement effect JJ. However, it can also be applied to non-reach-through breakdown type semiconductor chips, in which avalanche breakdown is used to punish reach-through breakdown.

〔Effect of the invention〕

As is clear from the above, according to the present invention, the incidence of reverse direction failures such as bias deterioration is significantly reduced. It is possible to manufacture glass-backed semiconductor chips with excellent reverse characteristics and reliability with high productivity and manufacturing yield.

[Brief explanation of drawings]

1A to 1G are cross-sectional views for explaining the manufacturing process of a glass diode chip according to an embodiment of the present invention, and FIG. FIG. 3 is a plan view of the diode chip of FIG. 1 (G). FIG. 4 and FIG. A sectional view partially showing an enlarged view of -81 of 'l. FIG. 6 is a cross section 1g1 showing a glass-coated diode chip according to a modification of the present invention, and FIG. 7 IAIN is a cross-sectional view of a conventional glass nuclide diode chip manufacturing process. Figures 8) to 1 are cross-sectional views for explaining the manufacturing process of another conventional glass diode chip. )・・
・P-type region, (51...pn junction, (6)...groove, (7
)... Glass laminated, (8)... Opening. (9)...1 pole, a',! J...S iO, membrane, ■
...shallow groove. Agent Norihiro Takano Tsugumi 2nd figure 3rd cause 4th figure 5th figure 1) U taste

Claims (3)

[Claims] (1) Forming at least one pn junction on a semiconductor substrate and forming an insulating film on the semiconductor substrate, and forming a groove in one main surface of the semiconductor substrate to a depth that exposes the pn junction. and removing the insulating film at the periphery of the groove before or after forming the groove; The glass coating layer is formed by forming a protective glass coating layer that is thicker than the insulating film, and simultaneously or separately removing a portion of the glass coating layer in the area surrounded by the groove and the insulating film. forming an electrode on the surface of the semiconductor substrate exposed by the opening; and cutting the semiconductor substrate at the groove or outside the groove. A method for manufacturing a glass-coated semiconductor chip, comprising: (2) The step of forming the groove and removing the insulating film includes forming a shallow groove having a depth that does not expose the pn junction so that the insulating film remains in an island shape. a step of removing the insulating film, and adding the p-p into the shallow trench.
2. The method of manufacturing a glass-covered semiconductor chip according to claim 1, further comprising the step of forming a deep groove having a depth that exposes the n-junction. (3) The step of forming the groove and removing the insulating film includes: removing only the insulating film so that the insulating film remains in an island shape; 2. The method of manufacturing a glass-covered semiconductor chip according to claim 1, further comprising the step of forming a groove so as to expose a pn junction.