JP3070705B2 - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JP3070705B2
JP3070705B2 JP35928091A JP35928091A JP3070705B2 JP 3070705 B2 JP3070705 B2 JP 3070705B2 JP 35928091 A JP35928091 A JP 35928091A JP 35928091 A JP35928091 A JP 35928091A JP 3070705 B2 JP3070705 B2 JP 3070705B2
Authority
JP
Japan
Prior art keywords
semiconductor device
electrode
active layer
layer
substrate layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP35928091A
Other languages
Japanese (ja)
Other versions
JPH06112206A (en
Inventor
泰男 長谷川
日出男 山口
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Origin Electric Co Ltd
Original Assignee
Origin Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Origin Electric Co Ltd filed Critical Origin Electric Co Ltd
Priority to JP35928091A priority Critical patent/JP3070705B2/en
Publication of JPH06112206A publication Critical patent/JPH06112206A/en
Application granted granted Critical
Publication of JP3070705B2 publication Critical patent/JP3070705B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【産業上の利用分野】本発明は半導体装置,特に面実装
される半導体装置に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a surface-mounted semiconductor device.

【従来技術】従来の面実装型の半導体装置,例えばショ
ットキーバリアダイオードとしては,例えば図4に示す
ような構造がある。図4にしたがって説明すると,半導
体基板層1上にカソード電極5aを取り出すためには予
め,高抵抗の能動層2a,2b に不純物拡散等を行い, 低抵
抗層9を形成しておく必要があった。この低抵抗層9は
本来必須のものではなく,カソード電極を取り出すため
の媒介物である。また,この半導体装置を回路基板上に
実装する際は,この半導体装置の全表面を保護樹脂8で
モールドしておく必要がある。このような従来の面実装
型の半導体装置では半導体の製造工程と保護樹脂の封止
工程が煩雑であった。
2. Description of the Related Art A conventional surface-mount type semiconductor device, for example, a Schottky barrier diode has a structure as shown in FIG. Referring to FIG. 4, in order to take out the cathode electrode 5a on the semiconductor substrate layer 1, it is necessary to previously diffuse the impurities into the high-resistance active layers 2a and 2b to form the low-resistance layer 9. Was. The low-resistance layer 9 is not essentially essential, but is a medium for extracting the cathode electrode. When the semiconductor device is mounted on a circuit board, it is necessary to mold the entire surface of the semiconductor device with the protective resin 8. In such a conventional surface mount type semiconductor device, a semiconductor manufacturing process and a protective resin sealing process are complicated.

【発明が解決しようとする課題】本発明は,面実装型の
半導体装置において,能動層の下層にある基板層に直接
に接続電極を形成させる断面構造を有する半導体装置を
得ること,及び保護樹脂の封止工程を簡略化させるを課
題とするものである。
SUMMARY OF THE INVENTION It is an object of the present invention to provide a semiconductor device having a sectional structure in which a connection electrode is formed directly on a substrate layer below an active layer in a surface mount type semiconductor device. It is an object to simplify the sealing step.

【課題を解決するための手段】本発明はこのような課題
を解決するため,接続電極を取り出す方法として能動層
をエッチングにより除去し基板層から直接電極を取る方
法と,その周囲を金属電極で囲みカソード電極と接続す
る。さらに前記の周囲電極の上部及び側面を樹脂で被覆
するものである。
In order to solve the above-mentioned problems, the present invention solves such a problem by removing the active layer by etching to remove the active layer directly from the substrate layer, and by using a metal electrode around the periphery. Connect to the surrounding cathode electrode. Further, the upper and side surfaces of the peripheral electrode are covered with a resin.

【実施例】図1は本発明の一実施例であるショットキー
バリアダイオードの製造工程を示す図である。図1(a)
に示すように,まず基板層1の上層に能動層2が形成さ
れ,さらに最上層には酸化膜3が形成される。そして能
動層2の上面にはガードリング21a,21b が形成される。
つぎに図1(b) に示すように能動層2のエピタキシャル
ウェーハーにおいて半導体装置を形成する領域を残し,
その他の領域の能動層2を基板層1の上面に達するまで
エッチングにて除去し,能動層2a,2b の二つの素子領域
を残す。つぎに図1(c) に示すように,一部露出した基
板層1の表面には金属電極5a,5b,5cを形成する。これら
の金属電極5a,5b,5cらは図2(h) に示すように能動層2
a,2b のそれぞれの上に形成される素子領域を取り囲む
ように形成され,カソード電極およびカソード周囲電極
となる。また酸化膜3a,3b のそれぞれの中心部を除去し
て能動層2a,2b の上に金属電極4a,4b を形成してそれぞ
れアノード電極とする。つぎに図1(d) に示すように,
ポリイミド等の感光性の熱可塑性樹脂を用いフォトリソ
グラフィー工程で金属電極4a,4b 及び金属電極5aを除い
て被覆する。被覆保護樹脂は8aは基板層1と金属電極5b
と能動層2aと酸化膜3aと金属電極4aとそれらの相互境界
面を被覆する。保護樹脂8b,8c,8dについても同様であ
る。つぎに図1(e) に示すように,金属電極4a,4b 及び
金属電極5aにはそれぞれ半田付け印刷工程または銀メッ
キ工程によりバンプ電極6a,6b,7 を形成する。以上でシ
ョットキーバリアダイオードが完成するが,これらの工
程は縦方向・横方向それぞれ多数が連なって一枚のウェ
ーハで同時に形成される。そして上記の工程が完成した
のちに各半導体装置の縁をダイシングで切断する。完成
図は図2に示す。図2(f) は電気回路図,図2(g) は完
成断面図,図2(h) は半切断見取図であって金属電極等
の配置を判りやすくするため,保護樹脂8a,8b,8c,8d と
バンプ電極6a,6b,7 を省いて示している。このように形
成されたショットキーバリアダイオードにおいて,能動
層2のエッチングにより容易に基板層1の表面に金属電
極5aによるカソード電極を形成することができる。また
前記エッチングと同時に行われる素子領域の周囲のエッ
チング後に,基板層1の表面に金属電極5b,5c が形成さ
れる。これら金属電極5b,5c はカソード周囲電極はして
作用し,ラテラル方向(図1の左右方向)の電流集中が
緩和される。さらに,素子の周辺部には能動層がなくな
り,基板層1より内側に能動層2a,2b が位置して,その
部分は保護樹脂8a,8b,8c,8c 等で被覆される構造となる
ため,従来のような全表面にわたる樹脂封止工程を必要
とせず,チップ化(ダイシング工程)後にそのまま実装
に供することができる。以上はショットキーバリアダイ
オードについての実施例を説明したが,本発明は一般の
pn接合ダイオードやトランジスタ等についても適用でき
るものである。図3は素子領域をpn接合にした実施例の
部分図であって,能動層2aにp 型半導体を拡散により形
成し,その上部に金属電極4aを形成する。その他の構造
については,図1乃至図2に示すものと同一である。
FIG. 1 is a view showing a manufacturing process of a Schottky barrier diode according to an embodiment of the present invention. Fig. 1 (a)
As shown in FIG. 1, an active layer 2 is first formed on a substrate layer 1, and an oxide film 3 is formed on the uppermost layer. Then, guard rings 21a and 21b are formed on the upper surface of the active layer 2.
Next, as shown in FIG. 1 (b), a region for forming a semiconductor device is left on the epitaxial wafer of the active layer 2,
The active layer 2 in the other area is removed by etching until the active layer 2 reaches the upper surface of the substrate layer 1, leaving two element areas of the active layers 2a and 2b. Next, as shown in FIG. 1 (c), metal electrodes 5a, 5b, 5c are formed on the partially exposed surface of the substrate layer 1. These metal electrodes 5a, 5b, 5c are connected to the active layer 2 as shown in FIG.
It is formed so as to surround an element region formed on each of a and 2b, and serves as a cathode electrode and a cathode peripheral electrode. The central portions of the oxide films 3a and 3b are removed, and metal electrodes 4a and 4b are formed on the active layers 2a and 2b, respectively, to form anode electrodes. Next, as shown in Fig. 1 (d),
Using a photosensitive thermoplastic resin such as polyimide, the metal electrodes 4a, 4b and the metal electrode 5a are covered by a photolithography process. The coating protective resin 8a is composed of the substrate layer 1 and the metal electrode 5b.
, The active layer 2a, the oxide film 3a, the metal electrode 4a, and their mutual interface. The same applies to the protective resins 8b, 8c, 8d. Next, as shown in FIG. 1 (e), bump electrodes 6a, 6b, 7 are formed on the metal electrodes 4a, 4b and 5a by a soldering printing process or a silver plating process, respectively. The Schottky barrier diode is completed as described above, and these processes are simultaneously formed on a single wafer by connecting a large number of each in the vertical and horizontal directions. After the above steps are completed, the edge of each semiconductor device is cut by dicing. The completed drawing is shown in FIG. FIG. 2 (f) is an electric circuit diagram, FIG. 2 (g) is a completed cross-sectional view, and FIG. 2 (h) is a half-cut sketch, in which protective resins 8a, 8b, 8c , 8d and the bump electrodes 6a, 6b, 7 are omitted. In the Schottky barrier diode thus formed, the cathode electrode formed of the metal electrode 5a can be easily formed on the surface of the substrate layer 1 by etching the active layer 2. After the etching around the element region, which is performed simultaneously with the etching, the metal electrodes 5b and 5c are formed on the surface of the substrate layer 1. These metal electrodes 5b and 5c function as cathode peripheral electrodes, and current concentration in the lateral direction (the left-right direction in FIG. 1) is reduced. Further, there is no active layer at the periphery of the element, and the active layers 2a and 2b are located inside the substrate layer 1, and the portion is covered with the protective resin 8a, 8b, 8c, 8c, etc. In addition, it is not necessary to perform a resin sealing step over the entire surface as in the conventional case, and the chip can be directly mounted after dicing (dicing step). Although the embodiment of the present invention has been described with reference to a Schottky barrier diode, the present invention
The present invention can be applied to a pn junction diode, a transistor, and the like. FIG. 3 is a partial view of an embodiment in which the element region is a pn junction. A p-type semiconductor is formed in the active layer 2a by diffusion, and a metal electrode 4a is formed thereon. Other structures are the same as those shown in FIGS.

【発明の効果】本発明は以上述べたように能動層へのエ
ッチングにより,金属電極を半導体基板層表面に取り出
してカソード及びカソード周囲電極とする。また能動層
を被覆する保護樹脂を有する構造としたため,電極の基
板表面への取り出しが容易になり,またラテラル方向の
電流集中を緩和することができる。またチップ化後の樹
脂封止工程を必要としないため工程,材料共に経済的と
なる。 それにより薄形化が可能になり実装密度が向上
する。
According to the present invention, as described above, a metal electrode is taken out to the surface of a semiconductor substrate layer by etching into an active layer to form a cathode and a cathode peripheral electrode. In addition, since the structure having the protective resin covering the active layer is adopted, it is easy to take out the electrode to the substrate surface, and it is possible to reduce the current concentration in the lateral direction. Further, since a resin sealing step after chip formation is not required, both steps and materials are economical. As a result, the thickness can be reduced, and the mounting density can be improved.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明によるショットキーバリアダイオードの
工程を示す図である。
FIG. 1 is a view showing a process of a Schottky barrier diode according to the present invention.

【図2】本発明によるショットキーバリアダイオードの
構造図である。
FIG. 2 is a structural diagram of a Schottky barrier diode according to the present invention.

【図3】本発明によるダイオードの構造の部分図であ
る。
FIG. 3 is a partial view of the structure of a diode according to the present invention.

【図4】従来のショトキーバリアダイオードの構造の一
例を示す図である。
FIG. 4 is a diagram showing an example of the structure of a conventional Schottky barrier diode.

【符号の説明】[Explanation of symbols]

1…基板層 2,2a,2b …能動層 21a,21b …ガードリング 22…p 層 3, 3a,3b …酸化膜 4a,4b …電極金属(アノード) 5a,5b,5c…電極金属(カソード) 6a,6b …バンプ電極(アノード) 7…バンプ電極(カソード) 8a,8b,8c,8d …保護樹脂 DESCRIPTION OF SYMBOLS 1 ... Substrate layer 2, 2a, 2b ... Active layer 21a, 21b ... Guard ring 22 ... P layer 3, 3a, 3b ... Oxide film 4a, 4b ... Electrode metal (anode) 5a, 5b, 5c ... Electrode metal (cathode) 6a, 6b… Bump electrode (anode) 7… Bump electrode (cathode) 8a, 8b, 8c, 8d… Protective resin

Claims (2)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】面実装型半導体装置において,エッチング
により能動層を素子領域を残して一部除去し,その除去
した能動層の下部の基板層に直接電極金属を形成し,そ
の電極金属上にバンプ電極を設けてなることを特徴とす
る半導体装置。
In a surface mount type semiconductor device, an active layer is partially removed except for an element region by etching, an electrode metal is directly formed on a substrate layer below the removed active layer, and an electrode metal is formed on the electrode metal. A semiconductor device comprising a bump electrode.
【請求項2】前記バンプ電極を除いた上面に熱可塑性樹
脂で被覆することを特徴とする請求項1記載の半導体装
置。
2. The semiconductor device according to claim 1, wherein an upper surface excluding said bump electrodes is covered with a thermoplastic resin.
JP35928091A 1991-12-27 1991-12-27 Semiconductor device Expired - Fee Related JP3070705B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP35928091A JP3070705B2 (en) 1991-12-27 1991-12-27 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP35928091A JP3070705B2 (en) 1991-12-27 1991-12-27 Semiconductor device

Publications (2)

Publication Number Publication Date
JPH06112206A JPH06112206A (en) 1994-04-22
JP3070705B2 true JP3070705B2 (en) 2000-07-31

Family

ID=18463693

Family Applications (1)

Application Number Title Priority Date Filing Date
JP35928091A Expired - Fee Related JP3070705B2 (en) 1991-12-27 1991-12-27 Semiconductor device

Country Status (1)

Country Link
JP (1) JP3070705B2 (en)

Also Published As

Publication number Publication date
JPH06112206A (en) 1994-04-22

Similar Documents

Publication Publication Date Title
US4524376A (en) Corrugated semiconductor device
JP3070705B2 (en) Semiconductor device
JP2940306B2 (en) Heterojunction bipolar transistor integrated circuit device and method of manufacturing the same
JP2000294805A (en) Schottky barrier diode and its manufacture
JP5811110B2 (en) Manufacturing method of semiconductor device
US5229313A (en) Method of making a semiconductor device having multilayer structure
JPS584815B2 (en) Manufacturing method of semiconductor device
JPH0526745Y2 (en)
JPS59150471A (en) Semiconductor device
JPS61134063A (en) Semiconductor device
JPH0654794B2 (en) Semiconductor integrated circuit
JPS6032986B2 (en) Manufacturing method for semiconductor devices
JPH0121569Y2 (en)
JPH0414266A (en) High breakdown strength planar type semiconductor element and its manufacture
JPS62122290A (en) Light emitting element
JPS6341228B2 (en)
JPH10275919A (en) Varactor diode
JPH0669092B2 (en) Method of manufacturing gate turn-off thyristor
JP2006237210A (en) Semiconductor device
JPH07335913A (en) Semiconductor device
JP2003332493A (en) Method of manufacturing semiconductor device
JPS62105427A (en) Manufacture of glass-coated semiconductor chip
JPH04323832A (en) Semiconductor device and manufacture thereof
JPH0697422A (en) Planar semiconductor device
JPS60170268A (en) Schottky barrier diode

Legal Events

Date Code Title Description
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20000510

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20090526

Year of fee payment: 9

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20090526

Year of fee payment: 9

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20100526

Year of fee payment: 10

LAPS Cancellation because of no payment of annual fees