JPS6197767A - 9-16-bit parallel output circuit of microcomputer - Google Patents

Abstract

PURPOSE:To process output data in a short time and to output it in parallel by constituting such that output data of 9-16 bits is outputs through a high- order address bus and data bus of an address bus. CONSTITUTION:A CPU of eight bits shows a parallel output circuit of 16 bits. Instead of four conventional registers, two registers 1B and 2B are installed, to which high-order address buses A9-A15 and data buses D0-D7 are connected, respectively. At the CK terminal of the registers 1B and 2B the write command WR of an output cycle goes to a low level during the active state. In the register 1B contents of the register B, which are outputted to high-order signals of the high-order address buses A8-A15, are stored, while in the register 2B contents of a register E, which are outputted to the address buses D0-D7, are stored.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field to which the Invention Pertains] The present invention relates to an output circuit in a CPU of a microcomputer, and particularly to improvements in a 9- to 16-bit output circuit.

[Prior art and its problems]

Conventionally, a 9- to 16-bit output circuit in this type of CPU is generally configured to output output data to a data bus in two parts: 8 bits and the remaining bits. For example, as a 16-bit output circuit of the CPU, the second
A device configured as shown in the figure is known. In general, in a CPU, A, B: C, D, E, L.

An 8-bit general-purpose register consisting of (1) is provided.However, in the circuit shown in FIG. 1, a bare register that can be used as a 16-bit register is provided.

Now, in the circuit shown in Figure 2, if switches ISW and 2SW are all closed and jumper IJ is connected as shown, the data in registers D and E will be output to output terminals OUT O to 0UT15. The program for this is structured as follows.

Program Nemo Operand State Number
2+11 LD A, E 4 (Transfers the contents of register E to register A) (210UT (0), A 11 (outputs the contents of register A to the data bus, lower signal “0” of the address bus) +3) LD A, D 4 (Transfers the contents of register D to register A) (4) OUT (1), A 11 (Outputs the contents of the register to the data bus 2. Lower signal “1” of the address bus) (51 OUT
(2), A 11 (outputs the contents of register A to the data bus, lower signal “2” of the address bus) Total 41 First, when program (1) is executed, the contents of register E are transferred to register A. Retained.

Next, when program (2) is executed, the CPU shifts to the output cycle shown in FIG. At this time, 0'' is output to the lower signal of address bus AO-A7, and the contents of register A are output to data bus DO-D7.This causes the write command Wl?'l of this output cycle.
(While active, the CK line terminal of register 2A becomes low level, and register A is output to data buses DO to D7.
The contents (contents of register E) are stored in register 2A.

Next, when program (3) is executed, the contents of register D are transferred to register A and held there.

Next, when the program (4) is executed, the CPU shifts to the output cycle shown in FIG. The contents of register A are output. As a result, the CK line terminal of register IA becomes low level while the write command m is active in this output cycle, and the contents of register A (contents of register D) output to data bus Do-D7 are stored in register IA. .

After that, when program (5) is executed, the CPU enters the output cycle shown in FIG. 3, and at this time, the address bus A
2'' is output to the lower signals of O to A7. As a result, while the write command (2) of this output cycle is active, the register 3A.

The GK terminal of 4A becomes low level, and the previous stage register I
The data stored in A, 2A is transferred to subsequent registers 3A, 4.
A is input and stored, and the output terminal OUT O~o OT
The contents of registers D and E are output to 15.

In this way, with the 9- to 16-bit output circuit in a conventional CPU, the processing time to output the contents of registers D and E is slow because 41 states are required, and the circuit configuration is also complicated. However, the manufacturing cost also increases.

[Purpose of the invention]

An object of the present invention is to process the output data in a short time and output it in parallel in an output circuit that obtains 9 to 16 bits of output data using an 8-bit CPU, and to manufacture it at low cost with a simple circuit configuration. can 9
- To provide a 16-bit parallel output circuit.

[Key points of the invention]

The 9- to 16-bit parallel output circuit of the microcomputer according to the present invention has a 9- to 16-bit parallel output circuit by an 8-bit CPU.
The output circuit of a microcomputer that obtains bit output data is characterized in that it is configured to output 9 to 16 bit output data via an upper address bus of an address bus and a data bus.

In the 9- to 16-bit parallel output circuit described above, two registers each obtaining 8-bit output data are provided,
An upper address bus is connected to one register and a data bus is connected to the other register, and a write command is simultaneously given to each register to read 9 to 16 bits of output data supplied from the upper address bus and data bus. It is preferable to configure the output terminals of each of the registers to simultaneously output the signals.

[Embodiments of the invention]

Next, embodiments of a 9- to 16-bit parallel output circuit for a microcomputer according to the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 shows a 16-bit parallel output circuit representing one embodiment of the present invention. For convenience of explanation, the same reference numerals are given to the same parts as the conventional components shown in FIG. 2, and detailed explanation thereof will be omitted. That is, in the circuit of this embodiment, two registers IB and 2B are provided in place of the conventional registers IA to 4A, and upper address buses A9 to A15 and data bus Do-D7 are connected to these registers, respectively. Become.

However, in this embodiment, the switches ISW and 2
When all SWs are closed and jumpers IJ are connected as shown, a program for outputting data in registers D and E to output terminals OUT O to UT15 is constructed as follows.

Program Nemo Operand State Number
Nick (11LDC, 07 (transfers 0″ to register C) +21 LDB, D 4 (register D
Transfer the contents of register B to register B) (31 OUT (C), E 12 (output the contents of register E to the data bus) First, when program (1) is executed, O'' is set in register C.

Next, when program (2) is executed, register D
The contents of are transferred to register B and held there.

Next, when program (3) is executed, the CPU shifts to the output cycle shown in FIG. 1Iofi is output to the signals of lower address buses AO to A7, and the contents of register E are output to data buses DO to D7.

As a result, the GK terminals of register IB and register 2B have the active frontage level of write command 7 of the output cycle, and register IB has the contents of register B ( The contents of register D) are stored, and the contents of register E output to data buses Do to D7 are stored in register 2B. In this way, the contents of register D and register E are output simultaneously to output terminals OUT O to 0UT15. Further, the processing time for these is 23 states, which is 18 fewer states than in the conventional output circuit, and the processing time is shortened by that amount.

〔Effect of the invention〕

As is clear from the embodiments described above, according to the present invention,
Utilizing the address space available in the CPU's I10 device address space, 9 to 16 bit output data is transferred to the upper signals of upper address buses A8 to A■5 and data bus Do-0.
7, it is possible to easily realize parallel output of 9 to 16 bits.

Further, according to the present invention, the 9- to 16-bit parallel output circuit can be configured with a simple circuit configuration, and data output processing can be speeded up to increase the processing speed of the entire system.
A microcomputer with excellent processing power can be easily obtained at low cost.

Although the preferred embodiments of the present invention have been described above, it goes without saying that various design changes can be made without departing from the spirit of the present invention.

[Brief explanation of drawings]

FIG. 1 shows the microcomputer 9 to 16 according to the present invention.
Circuit diagram illustrating an embodiment of a bit parallel output circuit, Part 2
The figure is a main part circuit diagram of a 16-bit output circuit in a conventional microcomputer, and FIG. 3 is an operation waveform diagram showing the output characteristics of the address bus and data bus during the output cycle of the circuit shown in FIGS. 1 and 2. . AO~A? ,,,address bus (lower) 88~A
15, . . . Upper address buses DO to D 7 , . . . Data buses ISW, 2SW, 0. switch IJ, jumper

Claims (2)

[Claims] (1) In the output circuit of a microcomputer that obtains 9- to 16-bit output data by an 8-bit CPU, it is configured to output 9- to 16-bit output data via an upper address bus and a data bus. A 9- to 16-bit parallel output circuit for a microcomputer. (2) In the 9- to 16-bit parallel output circuit according to claim 1, two registers each obtaining 8-bit output data are provided, and an upper address bus is connected to one register, and the upper address bus is connected to the other register. A data bus is connected, a write command is given to each of the registers at the same time, and 9 to 16 bits of output data supplied from the upper address bus and the data bus are simultaneously output to the output ends of each of the registers. 9-16 bit parallel output circuit for microcomputer.