JPH042973B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a microprocessor that allows not only logical operations but also mathematical arithmetic operations to be effectively executed by a simple program.

[Background of the Invention] For example, in a microprocessor equipped with an 8-bit data bus, in order to execute a logical operation between bits, the operation must be performed by making extensive use of bit shift instructions. Therefore, very inefficient arithmetic control must be performed. For example, using a Motorola microprocessor MC6801 equipped with P10 to P17 as input port P1 and P30 to P37 as output port P3, a bit-wise AND operation is performed from input ports P10 and P11, and the result is The program that outputs to output port P32 is as follows.

LDAA P1 ROLA ANDA P1 ROLA ANDA #$04 STAA MEMORY LDAA P3 ANDA #$FB ORA MEMORY STAA P3 Here, the value shown as MEMORY represents an arbitrary address in the RAM that can be accessed by the MC6801. In other words, in this example, 10 steps are required to perform a very simple logical operation.

In order to efficiently execute such logic operations in units of bits, for example, a 1-bit microprocessor MC14500 manufactured by Motorola Corporation can be effectively used. However, when such a 1-bit microprocessor is used to perform operations on a plurality of bits, such as a counting operation, the efficiency is extremely low. In other words, if we try to implement a 6-stage counter circuit using such a 1-bit microprocessor, a 9-step program is required for each stage of the counter, and an additional 5-step program is required for the clock. state. Therefore, a total of 59 steps are required. In other words, assuming that each command is one word, it consumes 59 words of program memory and 13 bits of data memory.

[Purpose of the Invention] The present invention has been made in view of the above points, and provides, for example, a method that enables efficient execution of logical operations in units of bits, as well as effective execution of arithmetic operations using multiple bits. The present invention aims to provide a microprocessor that can be effectively used in various control devices.

It is also an object of the present invention to enable the data memory portion to have a sufficiently simple common configuration while allowing arithmetic operations to be executed in addition to logical operations as described above.

[Summary of the Invention] That is, the microprocessor according to the present invention is provided with a logic unit that mainly performs logical operations in bit units and an arithmetic operation unit that performs arithmetic operations on multiple bits, and for each of these units. A dedicated data bus is set for each. In addition, in this case, the first and second
The data memory is set in a common state for the above data buses, and this data memory is used to connect the bit conversion circuit connected to each of the above data buses, and to connect the internal bus to this bit conversion circuit. It consists of an internal memory with a common bit configuration that is connected and set via the

[Embodiment of the Invention] An embodiment of the invention will be described below with reference to the drawings. Figure 1 shows its configuration.
This microprocessor includes first and second data buses 11 and 12. The first data bus 11 is a data bus having n1 bits, such as 1 bit, and is used to perform logical operations in bit units,
Alternatively, the first arithmetic unit 13 (Logic Unit, or
Arithmetic Logic Unit (ALU) is connected. Further, the second data bus 12 is
The second data bus 12 has an n2 bit configuration, for example 8 bits, which is different from n1, and a second arithmetic unit 14 is connected to the second data bus 12.

The data memory 15 is connected to the first and second data buses 11 and 12, which are set in parallel in this way, in a common state, and the input/output port 16 is connected to them. There is.

The microprocessor section set in this way is supplied with the clock signal generated by the clock generation circuit 17, and the system clock signal generated by the clock generation circuit 17 is as follows. The program counter 18 is operated, and the address of the program memory 19 is designated by the count output of the counter 18. This addressed program memory 19 outputs data corresponding to the address, and this output data is decoded by the instruction decoder 20.

This instruction decoder 20 couples an instruction output to the first data bus 11 or the second data bus 12, and the instruction decoded by the instruction decoder 20 is transmitted in units of n1 bits. If the instruction specifies an operation that can be executed by the first arithmetic unit 13, the first data bus 11 is selected. Then, together with the first arithmetic unit 13, the data memory 15 and the input/output port 16 are accessed.

Further, the instruction decoded by the instruction decoder 20 is an n2-bit unit arithmetic operation instruction (for example,
INCA instruction), the second data bus 12 of n2 bit configuration is selected, and the second arithmetic unit 14, data memory 15, and input/output port 16 are accessed.

Here, in the microprocessor configured as above, the microprocessor described above
If we program the above-mentioned bit-wise logical operation example using the MC14500 instruction system, we can use the first data bus 11 to have a 1-bit configuration and execute the bit-wise AND operation in the first arithmetic unit 13. becomes as follows.

LD P10 AND P11 STO P32 Also, an operation that treats the 8-bit input data of input port P1 in bytes as a numerical value, increments the data value by +1, and outputs it to output port P3 in bytes. In the case of
If you program it using the command system of the MC6801, it will look like this:

LADD P1 INCA STAA P3 That is, the first arithmetic unit 13 that mainly executes logical operations in bit units, and the first data bus 1 connected to this unit 13.
1, and an arithmetic program using a second arithmetic unit 14 that mainly executes multi-bit operations, and a second data bus 12 with a multi-bit configuration connected to this unit 14. The calculation program is executed by one microprocessor, and data processing efficiency is effectively improved.

Here, the data memory 15 set in a common state for the first and second data buses 11 and 12 having different bit configurations from n1 and n2 as described above is configured as shown in FIG. There is.
In other words, this data memory 15 has an m-bit configuration independent of the number of bits used in the data buses 11 and 12.
51, this internal data memory 15
First and second bit conversion circuits 153 and 154 are connected to the bit conversion circuit 1 via an internal data bus 152. The first and second bit conversion circuits 153 and 154 exchange data with the first and second data buses 11 and 12, respectively.
converts n1-bit data into m-bit data, and converts m-bit data into n1-bit data. Further, the second bit conversion circuit 154 converts data having an n2 bit configuration into data having an m bit configuration, and further converts data having an m bit configuration into data having a n2 bit configuration.

Figure 3 shows an example of a specific configuration of the data memory 15 as described above, in which n1 is set to 1 bit, n2 is set to 8 bits, and m is set to 8 bits. It shows.

That is, the first data bus 11 has a 1-bit configuration, and the second data bus 12 has an 8-bit configuration, and the "1-8" bit conversion circuit that becomes the first bit conversion circuit 153 is It consists of an 8-channel multiplexer 153a (TC4051BP) and a bus terminator 153b (CD40117B). Further, the second bit conversion circuit 154
8" bit conversion, an 8-bit bus buffer 154a (TC40H245) is used, and the internal data memory 151 is "2048 bytes x
8-bit” static RAM 151a
(TC5517AP) is used. In the figure, 21
is an address bus, and 155 is a control bus.

Next, the operating state of the microprocessor configured as described above will be explained using an example where address 00 of the data memory 15 (A0 to A6 are all 0) is accessed from each data bus 11 and 12. . However, each address in the data memory above has 1
This is what the bit data corresponds to.

(a) From the first data bus 11 to the data memory 15
When writing to the internal memory 15
1 RAM151a is set to read state, and data at addresses 00 to 07 is sent to output pins i/o1 to
It outputs to i/o8 and latches its state at bus terminator 153b via 8-bit internal data bus 152. After that, the above RAM1
51a is returned to the disabled state. Next, when the multiplexer 153a is enabled, its input pins A, B, and C are all in the 0 state, so the 1-bit data of the first data bus 11 is output to the pin D0.
Only D0 of internal data bus 152 is updated.
When the RAM 151a is set to the write state in this state, D0 which has undergone the above change and the other data D1 to D7 are stored in the RAM 151a as data at addresses 00 to 07, respectively.

(b) From the second data bus 12 to the data memory 15
When writing to bus buffer 1
54a is enabled and 8-bit data on the second data bus 12 is output from A1 to A8, this data is transferred to the internal data bus 152.
will be output on D0 to D7. In this state, when the RAM 151a is set to the write state, the data on the internal data bus 152 is stored as data at addresses 00 to 07, respectively.

(c) When reading data from the data memory 15 to the first data bus 11, first
51a is set to a read state. Therefore,
The data at addresses 00 to 07 is the internal data bus 15.
When the multiplexer 153a is enabled in this state, D0 is selected and the data at address 00 is placed on the first data bus 11.

(d) When reading data from the data memory 15 to the second data bus 12, first
51a is set to a read state. And 00~
The data at address 07 is output onto the internal data bus 152. In this state, the bus buffer 154a is enabled and the data on the internal data bus 152 is output to pins B1 to B7, and the data at addresses 00 to 07 are transferred to the second data bus 12. It becomes like this.

That is, in this microprocessor, the data memory 15 is connected to the 1-bit data bus 1.
From 1 onwards, as a RAM with a 128 x 1 bit configuration,
From the 8-bit data bus 12, the RAM operates as a 16×8-bit RAM.

Note that in the above embodiment, the first bit configuration has a different bit configuration.
Although the description has been made regarding the data memory accessed from the second data bus, it goes without saying that the data memory may be configured to be accessed from a larger number of different data buses. Furthermore, the bit configurations of the first data bus 11 and the second data bus 12 are set to 1 bit and 8 bits, respectively.
Although the state is shown in terms of bits, this can be similarly implemented in any relation of the number of bits as long as the bit configurations are different from each other.

[Effects of the Invention] As described above, according to the present invention, a plurality of data buses with bit configurations in different states are set, and arithmetic units corresponding to the bit configurations are respectively assigned to the data buses. It is set. In this case, a common data memory is set for the plurality of data buses, and this data memory is commonly used for arithmetic operations with different bit configurations. This allows a single microprocessor to easily perform arithmetic control using data with different bit configurations.
It will be possible to effectively apply it to various control systems.

[Brief explanation of drawings]

FIG. 1 is a block diagram illustrating a microprocessor according to an embodiment of the present invention, FIG. 2 is a block diagram showing in detail a portion related to the data memory used in the above embodiment, and FIG. 2 is a diagram showing the data memory portion in further detail. 11...first data bus, 12...second data bus, 13...first arithmetic unit, 14...
...Second arithmetic unit, 15...Data memory,
16...I/O port, 151...Internal data memory, 152...Internal data bus, 153...First bit conversion circuit, 154...Second bit conversion circuit.

Claims (1)

[Claims] 1 n1 bit configuration first data bus and the above
A second data bus having an n2-bit configuration different from n1, and a first and second data bus that perform mainly n1-bit operations and mainly n2-bit operations, respectively, are connected to the first and second data buses. 2 arithmetic units, and a data memory that is accessed in common from each of the first and second data buses, and this data memory is connected to the first data bus. ” bit conversion circuit, and “n2” which is connected to the second data bus.
-m'' bit conversion circuit, and an internal data memory having an m-bit configuration connected to both of the bit conversion circuits via an internal bus.