JPH0215342A - Memory device - Google Patents

Abstract

PURPOSE:To shorten memory reading time by immediately outputting latch data from a data latch to a data bus in a bus master when a coincidence signal is outputted from an address comparator. CONSTITUTION:The address comparator 23 compares the value of the address latch 21 latching upper address x-2 bits when memory blocks 4 to 7 are read out in the preceding time with the upper address x-2 bits of a current memory leading address. When a coincidence output is generated from the comparator 23, a memory controller 25 does not read out the blocks 4 to 7 and a multiplexer 32 selects data latches 27 to 30 latching read data obtained at the time of reading out the blocks 4 to 7 in the preceding time by the lower address 2 bits of the current memory reading address. An enable signal of the data latch concerned out of the data latches 27 to 30 is made effective and latch data from the data latches 27 to 30 are outputted to the data bus 12 in the bus master.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a memory device for a personal computer, a word processor, etc. equipped with a microcomputer.

BACKGROUND OF THE INVENTION In recent years, in personal computers and word processors equipped with microcomputers, there has been a remarkable improvement in the execution speed of application software and data processing speed as the speed of microcomputers, ROMs, and RAMs has increased.

Hereinafter, a conventional memory device will be explained based on the block diagram of FIG.

FIG. 2 shows a block diagram of a conventional memory device when it has four memory blocks, that is, when the number of 2fi memory blocks is n=2. In this memory device, when a bus master (not shown) performs a memory read operation, the lower address 2 of a memory read address consisting of X bits (or a positive integer where X>n) is output from the bus master.
A memory block is selected by the bit, a memory cell of the memory block is selected by the upper address (x-2), and read data from the memory cell of the selected memory block is output to the data bus of the bus master.

In FIG. 2, reference numeral 1 denotes a memory controller, and when a memory read request is received from the bus master via the control signal line 2, the read request is determined by the lower 2 bits of the memory read address output from the bus master to the address bus 3. It determines which of the four memory blocks 4, 5, 6.7 the memory block is, and connects the control signal lines 8, 9 to the corresponding memory block 4, 5, 6.7.
The first to fourth read control signal groups for memory reading are outputted through the terminals 10 and 11. Memory block 4゜5.
6.7 consists of a ROM or RAM (ROM in the drawing) that stores the bus master's program or read-only data, and has the same number of input/output lines as the bus master's data bus 12 (ROM only has output lines). In the first memory block 4, a memory cell selected by the first read control signal group of the memory controller 1 and the upper address (x-2) bits of the memory read address of the bus master is read, Read data is output to data bus 12. The second memory block 5 receives the second read control signal group of the memory controller 1 and the upper address (x
-2) The memory cell selected by the bit is read, and the third memory block 6 reads the memory cell selected by the third read control signal group and the upper address (z-2) bit of the memory read address. In the fourth memory block 7, the memory cell selected by the fourth read control signal group and the upper address (z-2) bit of the memory read address is read, and each read data is output to the data bus 12. be done.

Problem to be Solved by the Invention However, in the above conventional configuration, the read time is limited to the RAM or ROM constituting the memory blocks 4, 5, 6.
Therefore, to shorten the lead time, use expensive RAM or RO with short access time.
The problem was that M had to be used.

The present invention solves the above problem and solves the problem of expensive RAM.
Another object of the present invention is to provide a memory device that can shorten read time without using a ROM.

Means for Solving the Problems In order to solve the above-mentioned problems, the present invention consists of two memory elements each storing a bus master program or read-only data, each having the same number of input/output lines as the number of data buses of the bus master.゜ memory blocks (n is a positive integer) are provided, and X bits (x is X) of the bus master are provided.
> n positive integer) of the memory read address, the lower address n bits select the memory block, the upper address (x-n) bits select the memory cell of each memory block, and the selected memory block is read. A memory device that outputs read data from a memory cell to the data bus of the path master, wherein the upper address (x-n) bits of the memory read address when a read operation was previously performed from the memory block are stored. The address latch to be latched, the value of the address latch, and the upper address (x-n) of the current memory read address.
) an address comparator that compares bits, 2n data latches that each latch read data of the memory block, and a read request from the bus master;
Only when the coincidence output of the address comparator is invalid (mismatch), the read control signal # is simultaneously output to all of the 2n memory blocks, and the upper address (of the current memory read address) is read from the 2n memory blocks. x, -
n) a memory controller that outputs a strobe, which is a timing signal for reading data in a memory cell selected by a bit and latching the 2n pieces of read data in the data latch, and a read request from the bus master; select the data latch from the lower address n bits of the current memory read address when
A multiplexer is provided for outputting an enable signal to the data latch and outputting the latched data of the data latch to the data bus of the bus master.

Effect With the above configuration, when the upper address (x-n) bits for selecting the memory cell of the memory read address are the same as the previous one and the match output of the address comparator becomes valid (match), the memory controller selects the memory of the memory block. Latch data of the data latch selected by the output of the multiplexer is output to the data bus without executing cell read. This makes it possible to realize a memory device that is faster than a conventional memory device that always reads memory blocks, and allows the use of inexpensive ROMs and Makoto memory devices.

Example Hereinafter, one embodiment of the present invention will be described based on the drawings.

FIG. 1 is a block diagram of a memory device having 2n memory blocks and n=2, that is, 4 memory blocks, showing one embodiment of the present invention. Components that are the same as those of the conventional example shown in FIG. 2 are designated by the same reference numerals, and the description thereof will be omitted. Furthermore, the memory read address output from the bus master to the address bus 3 has the same structure as the conventional example.

In Figure 1, 2n is the previous memory block 4゜5
．． This is an address latch that latches the upper address (x-2) bits of the memory read address of the bus master (not shown) when a read operation is performed for 6.7, and the value of address latch 2n is the address It is output to the address comparator 23 via the bus 22. The value of this address latch 2n and the upper address (x-2) bits of the memory read address of the current bus master are determined by the address comparator 2.
3, and if they match, a match output signal is output to the memory controller 25 via the control signal line 24. The memory controller 25 selects the memory cell selected by the upper address (x-2) bits of the read address of the bus master only when there is a read request from the bus master and the coincidence output signal of the address comparator 23 is invalid (mismatch). memory blocks 4, 5, 6.7 blocks 4, 5
, 6.7, the respective memory blocks 4, 5, and 6.
Data latches 27 and 28 provided corresponding to 6.7
, 29, and 30, a strobe, which is a timing signal, is outputted via a control signal line 31yt. 32 is a multiplexer which, when there is a read request from the bus master, selects the corresponding data latches 27, 28, 29, 2 bits from the lower address of the current memory read address.
30 to select the enable signal on the control signal line 33
, 34, 35, and 36, and the latched data latched in the data latches 27, 28, 29, and 30 is output to the data bus 12.

The operation of the memory device having the above configuration will be described below.

First, a memory read address and a read request are output by the memory read operation of the bus master.

The address comparator 23 indicates that the previous memory block 4.5.
6. Compare the value of address latch 2n, which latches the upper address (x-2) bits when 7 is read, with the upper address (x-2) bits of the current memory read address, and the address comparator If the coincidence output of 23 is invalid (mismatch), the memory controller 25 simultaneously outputs a group of read control signals to memory blocks 4.5 and 6.7, and selects the read control signal group with the upper address (x-2) bit of the memory read address. The memory cells to be stored in each memory block 4, 5,
Read from 6.7, and output by memory controller 25, lead data from each memory block 4, 5, 6.7 is data latch 27, 28, 29,
30 respectively, and the multiplexer 32 selects the lower address 2 of the current memory read address of the bus mask.
Data latches 27°28 selected by bits,
29, 30, thereby enabling the corresponding data latch 27, 28.

One of 29 and 30 outputs latched data to data bus 12. Further, if the upper address (x-2) bits for selecting the previous and current memory cells are the same and the match output of the address comparator 23 is valid (match), the memory controller 25 selects the memory block 45.6.7i. The data latches 27 and 28 each latch the read data when the memory blocks 4, 5, and 6.7 were read last time without being read.

29.3(l) is selected by the multiplexer 32 with the lower 2 bits of the current memory read address, and the enable signals of the corresponding data latches 27, 28, 29, and 30 are enabled;
9, 30 latte data to the data bus 1 of the bus master.
Output to 2.

In this way, the 42nd address (x-2) bit of the memory read address at the time of the current bus master's read request is
If it matches the upper address (x-2) bits from the previous read of lζ memory blocks 4, 5, 6.7, read the memory read address without reading memory blocks 4, 5, 6.7. Data latches 27, 28, 29 corresponding to the lower 2 bits of the address.

30 latch data to data bus]2
This makes it possible to shorten the average memory read time from the bus master.

In this embodiment, the number of memory blocks is 4 (in the case of 2n memory blocks and [1-2)], but when the number of memory blocks is 2n (n is a positive integer), the number of memory blocks is 4. and the number of memory latches + 2 n, and the memory read address processed by the address latch 2n8 and the address comparator 23 is the (x-n) bit of the upper address, and the memory read address input to the memory block and selecting the memory cell is (x-n) bits of the upper address, the input address line of the multiplexer 32 is 0, that is, the lower address n bits of the memory read address are input, and the output is 2n, that is, the input address line for the multiplexer 32 is 0. It is sufficient to use one 2t.

Effects of the Invention As described above, according to the present invention, when the bus master outputs a memory read request and the coincidence output of the address comparator is invalid (mismatch), the same operation as the conventional memory device is performed, but the address comparison By immediately outputting the latch data from the data latch to the data bus of the bus mask when the match output of the device is a valid C match), the average memory read time can be reduced by 1m compared to conventional memory devices, and the memory When there are many blocks, the average memory read time can be further reduced.

Moreover, even if conventional low-cost RAM and ROM are used, an excellent memory device can be realized that can obtain the same effect as using high-cost, high-speed RAM and ROM.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a memory device δ showing an embodiment of the present invention, and FIG. 2 is a block diagram of a conventional memory device. 3...Address bus, 4,5,6.7...Memory block, 12...Data bus, 2n...Address latch, 23...Address comparator, 25...Memory controller, 27 , 28, 29-. 30--data latch, 32--multiplexer.

Claims (1)

[Claims] 1. Consisting of a memory element that stores the bus master's program or read-only data, each having the same number of input and output lines as the bus master's data buses2^n
(n is a positive integer) memory blocks are provided, and the memory block is selected by the lower address n bits of the memory read address consisting of x bits (x is a positive integer where x>n) of the bus master, and the upper A memory device that selects a memory cell of each memory block using address (x-n) bits and outputs read data from the memory cell of the selected memory block to the data bus of the bus master, An address latch that latches the upper address (x-n) bits of the memory read address when a read operation is performed from the block, and the value of the address latch and the upper address (x-n) bits of the current memory read address. There is an address comparator that compares the read data of the memory block, 2^n data latches that each latch the read data of the memory block, and a read request from the bus master, and the match output of the address comparator is invalid (mismatch). Only when the read control signal group is simultaneously output to all of the 2^n memory blocks,
Reads the data of the memory cell selected by the upper address (x-n) bits of the current memory read address from the 2^n memory blocks, and latches the 2^n read data in the data latch. When there is a read request from the memory controller and the bus master, which outputs a strobe, which is a timing signal for
A memory device comprising a multiplexer that selects the data latch from n bits of a lower address of a current memory read address, outputs an enable signal to the data latch, and outputs the latched data of the data latch to the data bus of the bus master.