JPH03268135A - Microcomputer - Google Patents

Abstract

PURPOSE:To prevent instruction codes from becoming complicate and processing speeds of branch instructions and interruptions from decreasing by transferring instruction codes held in respective temporary registers to an instruction register, one by one, in time series, and executing the instruction codes by a central arithmetic unit. CONSTITUTION:The central arithmetic unit 1 executes various instruction codes each consisting of a specific number of bits in order and the instruction register 2 holds the instruction codes and outputs them to the central arithmetic unit 1. The instruction codes are held temporarily in the temporary registers 3 and transferred to the instruction register 2, instruction by instruction, in time series, input terminals 4 are provided by as many as bits of each instruction code corresponding to the temporary registers 3, and various instruction codes are inputted to the respective temporary registers 3 from outside at the same time.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a microcomputer that reads and executes various instruction codes from the outside.

With recent advances in semiconductor technology and application to advanced processing devices such as workstations, microcomputers are required to be faster.

The signal speed inside microcomputers is becoming faster and faster due to advances in semiconductor technology, but the input terminals for data transfer (instruction fetching) with external storage devices have a large area and therefore have large parasitic capacitance, making it difficult to transmit signals at high speed. That's difficult. Therefore, in order to meet future demands for faster microcomputers, it is necessary to solve the speed bottleneck in the input terminal section.

[Prior Art] Conventionally, in a microcomputer, as shown in Fig. 6,
An instruction code with a predetermined number of bits N is input to the instruction register 2 via N input terminals 4, and the instruction code is input to the central processing unit (hereinafter referred to as C
The microcomputer (called PU) 1 executes the instruction code transferred from the instruction register 2. In order to increase the speed of this microcomputer, the number of bits N of the instruction code, that is, the number of input terminals 4, is increased. The word length is increased, and multiple instruction codes are incorporated at a time.

Furthermore, as shown in FIG. 7, a conventional microcomputer has an instruction cache 5 built in between a plurality of input terminals 4 and an instruction register 2 to reduce external access and increase speed. There are some things.

[Problems to be Solved by the Invention] However, in a microcomputer such as the one shown in FIG. 6, in which the word length of the instruction code is made long,
There is a problem in that the instruction code becomes complicated.

Furthermore, in a microcomputer with a built-in instruction cache 5, such as the microcomputer shown in FIG. Since it is slow, there is a problem that the processing speed is slow.

The present invention has been made to solve the above-mentioned problems, and its purpose is to provide a microcomputer that can prevent the complexity of instruction codes and the reduction in processing speed at the time of branch instruction 2 interrupts, etc. It's about doing.

1.Means to solve the problem] FIG. 1 is a diagram explaining the principle of the present invention.

The central processing unit 1 sequentially executes various instruction codes each having a predetermined number of bits, and the instruction register 2 holds the instruction codes and outputs the instruction codes to the central processing unit 1.

The plurality of temporary registers 3 temporarily hold various instruction codes, and transfer each held instruction code to the instruction register 2 one instruction at a time in time series. The input terminal 4 is connected to each temporary register 3 by the same number of bits as the instruction code, and is used to simultaneously input various instruction codes to each temporary register 3 from the outside.

[Operation] Various instruction codes are simultaneously input to each temporary register 3 via the input terminal 4. Thereafter, the instruction codes held in each temporary register 3 are transferred to the instruction register 2 one by one in time series, and the instruction code is executed by the central processing unit 1.

Therefore, even if the processing speed of the central processing unit 1 increases, there is no need to increase the input speed of the input terminal 4 for inputting the instruction code, and there is no need to increase the word length of the instruction code. Code is not complicated.

[Example] An example embodying the present invention will be described below with reference to FIGS. 2 to 4.

As shown in FIG. 2, the CP of the microcomputer 10
A block address temporary register 11 that temporarily holds program addresses is connected to the UI, and a plurality of program address terminals 12 are connected to the register 11. Then, the CPUI accesses a plurality of addresses in the program memory 13 via the program address temporary register 11 and the program address terminal 12. Program memory 13 in this embodiment
stores n-bit instruction code data (hereinafter referred to as program data), and when a program is accessed by the CPU 1, outputs four program data.

The four program data outputted from the program memory 13 are input to four temporary registers 3A to 3D via program data terminals 4, which are provided with n pieces of program data, each having the same number of bits as the number of bits of the program data, for a total of 4n pieces. Retained temporarily.

Each of the temporary registers 3A to 3D is connected to the instruction register 2 via a bus 14A consisting of n wires, and transfers the program data held therein one by one to the instruction register 2 in time series. The instruction register 2 is also connected to the CPUL via a bus 14B made up of n wires, and sequentially transfers various program data transferred from each of the temporary registers 3A to 3D to the CPUI. The CPU 1 is configured to sequentially execute various program data transferred from the instruction register 2.

Next, the instruction register 2 and each temporary register 3A
~3D will be explained based on FIG.

Each of the temporary registers 3A to 3D consists of n bit storage units 15 connected to each program data terminal 4, respectively. Each bit storage unit 15 has a first clocked inverter 1 connected in series to each program data terminal 4.
6. Inverter 17° Second clocked inverter 1
8, and a third clocked inverter 19 which together with the inverter 17 constitutes a latch circuit. Each clocked inverter 16, 1.8.19 has a pass control terminal 1
When a high level control signal is input to 6a, 18a, 19a, the level of the input signal is inverted and output, and when a high level control signal is input to cutoff control terminals 16b, 18b, ], 9b. , which blocks that person's J signal.

The pass control terminal 16a of each first clocked inverter 16 and the cutoff control terminal L9 of each third clocked inverter 19 of each temporary register 3A to 3D
The program fetch signal PF is inputted to b from the CPUI, and the cut-off control terminal 16b of each first clocked inverter 16 and the pass control terminal of each third clocked inverter 19]; A signal obtained by inverting the program fetch signal PF is input via the inverter 20. In addition, each temporary register 3A
The output select signals 5LO-8L3 are inputted from the CPUI to the passage control terminals 18a of each of the second clocked inverters 18 of . A signal obtained by inverting each of the output select signals SLO to S L3 is inputted to each of the output select signals SLO to S L3.

Further, the instruction register 2 includes n bit storage units 25 connected to each wiring of the bus 14A, and each bit storage unit 25 is connected to a fourth clocked inverter 26 . It consists of an inverter 27 and a fifth clocked inverter 28 which together with the inverter 27 constitutes a latch circuit. The pass control terminal 26a of each fourth clocked inverter 26 and the cutoff control terminal 28b of each fifth clocked inverter 28 are connected to the CPU.
The load signal ILD is input from I, and each fourth
A signal obtained by inverting the load signal ILD is inputted to the cutoff control terminal 26b of the clocked inverter 26 and the passage control terminal 28a of each fifth clocked inverter 28 via the inverter 29.

Therefore, in a state where each bit data of instructions A, B, C, I shown in FIG. 4 is input to each program data terminal 4, the program fetch signal PF is
When the fetch signal PF becomes high level, the fetch signal PF passes through the pass control terminal 16a of each first clocked inverter 16 and the cutoff control terminal 1 of each third clocked inverter 19.
9b.

As a result, each third clocked inverter 19 blocks its input signal, and each first clocked inverter 16 inverts its input signal and passes it. As a result, the bit data of each program data terminal 4 is taken into each bit storage section 15 in an inverted state, and the bit data taken into each bit storage section 15 is transferred to the inverter 17.
As a result, the signal is further inverted, that is, returned to the input level of each program data terminal 4, and is output to the third clocked inverter 190 input terminal.

Next, when the program fetch signal PF becomes low level, the program fetch signal PF is passed through the inverter 20.
A signal having an inverted level is input to the cut-off control terminal 16b of each first clocked inverter 16 and the pass control terminal 9a of each third clocked inverter 19. This allows each first clocked inverter 1
6 blocks its input signal, and each third clocked inverter 19 inverts its input signal, that is, the input level of each block data terminal 4, and passes it through. As a result, each bit data is latched in each bit storage section 15, and each bit data of instructions A, B, C, and D is held in temporary registers 3A to 3D as shown in FIG.

Instructions A and B are stored in temporary registers 3A to 3D.

In a state where each bit data of C and D is held, when the output select signal SLO of the CPUI becomes high level as shown in FIG.
Only the clocked inverter 18 inverts and passes its input signal.

As a result, each bit data of the instruction A held in the temporary register 3A is outputted to each bit storage section 25 of the instruction register 2 via the bus 14A.

When the load signal ILD goes high in a state in which each bit data of the instruction A is output to the winter 2 bit storage section 25 of the instruction register 2, the load signal ILD passes through each fourth clocked inverter 26. Control terminal 2
6a and the cutoff control terminal 28b of each fifth clocked inverter 28. This causes each fifth clocked inverter 28 to block its input signal, and each fourth clocked inverter 26 to invert and pass its input signal. As a result, each bit data of instruction A is taken into each bit storage section 25, and each bit data of instruction A is taken into each bit storage section 25.
The bit data fetched into the fifth clocked inverter 27 is further inverted by the inverter 27 and output to the CPUI, and is also output to the input terminal of the fifth clocked inverter 28.

Next, as shown in FIG. 4, when the output select signal SLO of the CPUI becomes low level, a signal obtained by inverting the level of the output select signal SLO is transmitted through the inverter 21 to each second clocked inverter of the temporary register 3A. 18 cutoff control terminals 18b, each second clocked inverter 18 cuts off its input signal,
Each bit data of instruction A is no longer output to each bit storage section 25 of instruction register 2.

Then, when the load signal ILD of the CPUI becomes low level, a signal obtained by inverting the level of the load signal ILD is sent to each fourth clocked inverter 2 via the inverter 29.
6 cutoff control terminal 26b and each fifth clocked inverter 28 pass control terminal 28a. As a result, each fourth clocked inverter 26 blocks its input signal, and each fifth clocked inverter 28 inverts its input signal, that is, the output level of each inverter 27, and passes it. As a result, each bit storage section 25
Each bit data of instruction A is latched, and instruction A is held in the instruction register 2 as shown in FIG.

After that, the instruction A is stored in the temporary registers 3A to 3D.

In a state where each bit data of B, C, and D is held, the output select signal SL of the CPUI is output as shown in FIG.
When only one of I to SL3 becomes high level 34 in sequence, the temporary register 3B is opened in the same way as above.
Each bit data of instructions B-D held in 3D is outputted to each bit storage section 25 of the instruction register 2 via the bus L4A. Then, in a state where each bit data of each instruction B-D is output to each bit storage section 25 of the instruction register 2, when the load signal ILD becomes high level, each bit data of each instruction B-D is output to the instruction register 2. At the same time, when the output select signals SLI to SL3 of the CPUI become low level, each bit data is latched into each bit storage unit 25, and the fourth
As shown in the figure, each bit data of instructions B to D is held in the instruction register 2 and output to the CPUI.

Further, a data address register 30 that temporarily holds data addresses is connected to the CPU 1.
0 is connected to a plurality of data address terminals 31. Further, a data cache 32 is connected to the CPUI,
Data cache 32 is connected to data memory 34 via a plurality of data terminals 33. And CPU1
accesses a predetermined address of the data memory 34 via the data address register 30 and the data address terminal 31, reads data to be processed from the data memory 34 via the data cache 32, and transfers operation result data to the data memory 34. Write.

In this way, in this embodiment, four temporary registers 3A to 3D are provided before the instruction register 2, and n program data terminals 4 are provided for each temporary register 3A to 3D. Four program data can be fetched into the registers 3A to 3D at the same time, and the program data held in each temporary register 3A to 3D can be fetched from the CP via the instruction register 2.
It can be sequentially transferred to the UI. Therefore, without increasing the input speed of the program data terminal 4,
In addition, without increasing the word length of the program data and complicating the program data, the CPU It is possible to prevent a decrease in processing speed.

FIG. 5 is a block circuit diagram showing the electrical configuration of another embodiment, and the microcomputer 10 of this embodiment has a CPU
A program and data address temporary register 35 for temporarily holding program addresses and data addresses is connected to I, and a plurality of program and data address terminals 36 are connected to the register 35. and,
The CPU 1 has a program and data address temporary register 35 and a program and data address terminal 3.
6, the program and data memory 37 is accessed. Furthermore, in the microcomputer 10 of this example, among the 4n program data terminals 4,
A predetermined number of program data terminals 4 are also used as data terminals, and a data cache 32 is connected to the predetermined number of block program data terminals 4.

When accessing the program data of the program and data memory 37, four different program data are input to the four temporary registers 3A to 3D via the 40 program data terminals 4. The microcomputer 10 is miniaturized by reading data to be processed from the program and data memory 37 and writing operation result data to the program and data memory 37 via the program data terminals 4 and data cache 32. I'm trying.

[Effects of the Invention] As described in detail above, the present invention has the excellent effect of preventing the complexity of instruction codes and the reduction in processing speed at the time of a branch instruction 9 interrupt.

[Brief explanation of drawings]

Fig. 1 is a diagram explaining the principle of the present invention, Fig. 2 is a block circuit diagram showing the electrical configuration of an embodiment embodying the invention, and Fig. 3 is an electric circuit showing a temporary register in an embodiment. Figure 4 is a waveform diagram showing the operation of one embodiment, Figure 5 is a block circuit diagram showing the electrical configuration of another embodiment, and Figures 6 and 7 are electrical configurations of conventional microcomputers. It is a block circuit diagram showing. In the figure, the central processing unit 2 is an instruction register (2), and the temporary register 4 (3) is an input terminal. (CPU) ■

Claims (1)

[Claims] A central processing unit (1) that sequentially executes various instruction codes each having a predetermined number of bits, and one instruction register (2) that holds the instruction code to be executed by the central processing unit (1). and a plurality of temporary registers (3) that temporarily hold various instruction codes and sequentially transfer the held instruction codes to the instruction register (2), and a plurality of temporary registers (3) corresponding to each of the temporary registers (3). The same number of bits as the instruction code are provided, and each temporary register (3
) A microcomputer comprising a plurality of input terminals (4) for simultaneously inputting various instruction codes.