JPS6181347U - - Google Patents

Info

Publication number
JPS6181347U
JPS6181347U JP1985108774U JP10877485U JPS6181347U JP S6181347 U JPS6181347 U JP S6181347U JP 1985108774 U JP1985108774 U JP 1985108774U JP 10877485 U JP10877485 U JP 10877485U JP S6181347 U JPS6181347 U JP S6181347U
Authority
JP
Japan
Prior art keywords
multiplier
circuit
cross product
array
signals
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1985108774U
Other languages
English (en)
Other versions
JPS6132437Y2 (ja
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Publication of JPS6181347U publication Critical patent/JPS6181347U/ja
Application granted granted Critical
Publication of JPS6132437Y2 publication Critical patent/JPS6132437Y2/ja
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52—Multiplying; Dividing
    • G06F7/523—Multiplying only
    • G06F7/53—Multiplying only in parallel-parallel fashion, i.e. both operands being entered in parallel
    • G06F7/5324—Multiplying only in parallel-parallel fashion, i.e. both operands being entered in parallel partitioned, i.e. using repetitively a smaller parallel parallel multiplier or using an array of such smaller multipliers

Landscapes

  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Computational Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Complex Calculations (AREA)
  • Multi Processors (AREA)
  • Lock And Its Accessories (AREA)

Description

【図面の簡単な説明】
第１図は、拡張可能な４×８アレイ乗算回路の
入，出力接続端子を示すブロツク図、第２図は、
８ビツトの被乗数と４ビツトの乗数の乗算によつ
て作成される２の補数のクロス積項のテーブル、
第３図は、本考案に従つて第１、第２の制御信号
で修飾された２の補数のクロス積項、第４図は、
第１図に図示した型の４個の乗算回路を備えた８
×１６の拡張アレイ乗算回路のブロツク図、第５
図は、第４図に示した拡張アレイの更に詳細なブ
ロツク図であつて各４×８乗算回路間の相互接続
を示すもの、第６図は、任意の大きさの２つの補
数の乗算アレイについて第１、第２の制御信号の
プログラミングを図示する拡張乗算アレイのブロ
ツク図、第７図は、ゲート手段、加算ブロツク及
びキヤリ・ルツクアヘツド・ブロツクを備えた本
考案の一実施例の４×８乗算回路、第８Ａ，８Ｂ
図は、ゲート手段を更に詳細に図示すると共に全
加算及び半加算ブロツクを図示する論理図、第９
図は、第７図及び第８Ａ，８Ｂ図のキヤリ・ルツ
クアヘツド・ブロツクに対応する論理図である。 １６，１８，２０，２２，４０，４２…乗算回
路、３１，３５…外部ブロツク。

Claims (1)

  1. 【実用新案登録請求の範囲】 (a) 拡張乗算アレイ内の乗算回路の相対位置を
    確定する第１、第２の制御信号を受ける第１、第
    ２の制御端子と、 (b) 第１、第２のデジタルデータ語を受けて複
    数のクロス積信号を作成するゲート回路であつて
    、該ゲート回路は前記第１、第２の制御端子に接
    続されて該第１、第２の制御信号に応答して前記
    クロス積信号の選択されたセツトが該拡張乗算ア
    レイ内の乗算回路の相対位置の函数としてイネー
    ブルにされるゲート回路と、 (c) 該ゲート回路に接続されて前記クロス積信
    号の選択されたセツトを加算して前記第１、第２
    のデジタルデータ語の積のセグメントを作成する
    加算回路を備えたことを特徴とする拡張乗算アレ
    イ内での使用に適し、第１、第２のデジタルデー
    タ語の積のセグメントを作成するための乗算回路
    。
JP1985108774U 1978-04-03 1985-07-15 Expired JPS6132437Y2 (ja)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US05/892,792 US4130878A (en) 1978-04-03 1978-04-03 Expandable 4 × 8 array multiplier

Publications (2)

Publication Number Publication Date
JPS6181347U true JPS6181347U (ja) 1986-05-30
JPS6132437Y2 JPS6132437Y2 (ja) 1986-09-20

Family

ID=25400494

Family Applications (2)

Application Number Title Priority Date Filing Date
JP3767479A Pending JPS54134943A (en) 1978-04-03 1979-03-28 Opennended 4x8 array multiplier circuit
JP1985108774U Expired JPS6132437Y2 (ja) 1978-04-03 1985-07-15

Family Applications Before (1)

Application Number Title Priority Date Filing Date
JP3767479A Pending JPS54134943A (en) 1978-04-03 1979-03-28 Opennended 4x8 array multiplier circuit

Country Status (8)

Country Link
US (1) US4130878A (ja)
JP (2) JPS54134943A (ja)
DE (1) DE2913327C2 (ja)
FR (1) FR2422204A1 (ja)
GB (1) GB2017985B (ja)
HK (1) HK66984A (ja)
MY (1) MY8500496A (ja)
SG (1) SG18584G (ja)

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL7809398A (nl) * 1978-09-15 1980-03-18 Philips Nv Vermenigvuldiginrichting voor binaire getallen in twee-complement notatie.
JPS59149540A (ja) * 1983-02-15 1984-08-27 Toshiba Corp 分割型乗算器
FR2544105B1 (fr) * 1983-04-06 1988-10-14 Thomson Csf Multiplieur du type en cascade utilisant un ensemble d'operateurs elementaires
GB2166272B (en) * 1984-10-27 1988-06-29 Stc Plc Serial multiplier circuit
JPS61156433A (ja) * 1984-12-28 1986-07-16 Toshiba Corp 並列乗算器
US4887233A (en) * 1986-03-31 1989-12-12 American Telephone And Telegraph Company, At&T Bell Laboratories Pipeline arithmetic adder and multiplier
US4768161A (en) * 1986-11-14 1988-08-30 International Business Machines Corporation Digital binary array multipliers using inverting full adders
KR920003908B1 (ko) * 1987-11-19 1992-05-18 미쓰비시뎅끼 가부시끼가이샤 승산기(乘算器)
US5032865A (en) * 1987-12-14 1991-07-16 General Dynamics Corporation Air Defense Systems Div. Calculating the dot product of large dimensional vectors in two's complement representation
US4941121A (en) * 1988-04-01 1990-07-10 Digital Equipment Corporation Apparatus for high performance multiplication
DE3823722A1 (de) * 1988-07-13 1990-01-18 Siemens Ag Multiplizierer
US4926371A (en) * 1988-12-28 1990-05-15 International Business Machines Corporation Two's complement multiplication with a sign magnitude multiplier
EP0813143A3 (en) * 1989-11-13 1998-01-28 Harris Corporation Sign extension in plural-bit recoding multiplier
US5262976A (en) * 1989-11-13 1993-11-16 Harris Corporation Plural-bit recoding multiplier
JP2558912B2 (ja) * 1990-03-08 1996-11-27 松下電器産業株式会社 乗算器回路
DE4317074C1 (de) * 1993-05-21 1994-06-23 Itt Ind Gmbh Deutsche Multiplizierer für reelle und komplexe Zahlen
US5751622A (en) * 1995-10-10 1998-05-12 Chromatic Research, Inc. Structure and method for signed multiplication using large multiplier having two embedded signed multipliers
US5956265A (en) * 1996-06-07 1999-09-21 Lewis; James M. Boolean digital multiplier
US7269616B2 (en) * 2003-03-21 2007-09-11 Stretch, Inc. Transitive processing unit for performing complex operations
US20090077145A1 (en) * 2007-09-14 2009-03-19 Cswitch Corporation Reconfigurable arithmetic unit
US20090292756A1 (en) * 2008-05-23 2009-11-26 Elliot Gibson D Large-factor multiplication in an array of processors

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3670956A (en) * 1968-09-26 1972-06-20 Hughes Aircraft Co Digital binary multiplier employing sum of cross products technique
US3752971A (en) * 1971-10-18 1973-08-14 Hughes Aircraft Co Expandable sum of cross product multiplier/adder module
US3914589A (en) * 1974-05-13 1975-10-21 Hughes Aircraft Co Four-by-four bit multiplier module having three stages of logic cells

Also Published As

Publication number Publication date
FR2422204B1 (ja) 1984-06-15
FR2422204A1 (fr) 1979-11-02
JPS6132437Y2 (ja) 1986-09-20
MY8500496A (en) 1985-12-31
HK66984A (en) 1984-08-31
GB2017985A (en) 1979-10-10
DE2913327A1 (de) 1979-10-04
JPS54134943A (en) 1979-10-19
SG18584G (en) 1985-02-15
US4130878A (en) 1978-12-19
GB2017985B (en) 1982-04-07
DE2913327C2 (de) 1986-04-24

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