JPS6164152A - C-mos circuit - Google Patents
C-mos circuitInfo
- Publication number
- JPS6164152A JPS6164152A JP59186785A JP18678584A JPS6164152A JP S6164152 A JPS6164152 A JP S6164152A JP 59186785 A JP59186785 A JP 59186785A JP 18678584 A JP18678584 A JP 18678584A JP S6164152 A JPS6164152 A JP S6164152A
- Authority
- JP
- Japan
- Prior art keywords
- mos
- mos circuit
- power supply
- input
- type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 claims abstract description 27
- 239000004065 semiconductor Substances 0.000 claims description 5
- 230000015556 catabolic process Effects 0.000 description 5
- 238000010586 diagram Methods 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000002253 acid Substances 0.000 description 1
- 239000011888 foil Substances 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
- H01L27/0921—Means for preventing a bipolar, e.g. thyristor, action between the different transistor regions, e.g. Latchup prevention
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Electronic Switches (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、Ｐ型基板に形成されたＣ−ＭＯ５回路に関し
、過大入力時に生じるラッチアップを防止しようとする
ものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a C-MO5 circuit formed on a P-type substrate, and is intended to prevent latch-up that occurs when an excessive input is applied.
Ｃ−ＭＯ５回路はＰチャネルＭＯＳＩ−ランジスタとＮ
チャネルＭＯＳ）ランジスタを直列に電源Ｖ ｃｃ、
Ｖ ｓｓ間に接続し、これらのトランジスタのゲート
に共通に入力を加え、これらのトランジスタの直列接続
点を出力端とする。Ｃ−ＭＯＳ回路を形成する半導体基
板はＰ型、Ｎ型いずれでもよいが、Ｐ型の場合を第３図
に示す。この図で１０はＰ型半導体基板、１２は基板１
０に形成したＮ型のウェル、１４．１６はＰ型基板１０
に形成したＮ 型拡散層、２０．２２はＮ型のウェル１
２に形成したＰ＋型拡散層、１８．２４はゲート電極で
ある。２０，２２．２４はＰチャネルＭＯＳトランジス
タＱ１を形成し、２０．２２はそのドレイン、ソース、
２４がゲートである。１４，１６，１８はＮチャネルＭ
ＯＳトランジスタを形成し、１４．１６がソース、ドレ
イン、１８がゲートである。トランジスタＱ１のソース
２２は、ウェル１２と共に電源Ｖｃｃへ接続され、トラ
ンジスタＱｌ、Ｑ２のドレイン１６．２０は互いに接続
されて出力端ＯＵＴとなり、トランジスタＱ２のソース
１４は電源Ｖｓｓへ接続される。一般にＶｃｃは５Ｖ、
Ｖｓｓは０■であり、基４反１０はグランドへ接続され
る。しかし、高速化や寄生素子効果の抑制を狙って基Ｆ
ｊ、１０へは−３，５〜−４，ＯＶの負のバソクゲート
ハイアス電圧を与えるものがある。The C-MO5 circuit consists of a P-channel MOSI-transistor and an N
channel MOS) transistor in series with power supply V cc,
Vss, a common input is applied to the gates of these transistors, and the series connection point of these transistors is used as an output terminal. The semiconductor substrate forming the C-MOS circuit may be of either P type or N type, and FIG. 3 shows the case of P type. In this figure, 10 is a P-type semiconductor substrate, 12 is a substrate 1
0 is an N-type well formed, 14.16 is a P-type substrate 10.
20.22 is the N type well 1 formed in the N type diffusion layer.
The P+ type diffusion layer formed at 2 and 18.24 are gate electrodes. 20, 22.24 form a P-channel MOS transistor Q1, and 20.22 is its drain, source,
24 is a gate. 14, 16, 18 are N channel M
An OS transistor is formed, and 14 and 16 are the source and drain, and 18 is the gate. The source 22 of the transistor Q1 is connected to the power supply Vcc together with the well 12, the drains 16 and 20 of the transistors Q1 and Q2 are connected to each other to form an output terminal OUT, and the source 14 of the transistor Q2 is connected to the power supply Vss. Generally Vcc is 5V,
Vss is 0■, and base 4 and 10 are connected to ground. However, with the aim of increasing speed and suppressing parasitic element effects,
There is one that applies a negative bathok gate high-ass voltage of -3.5 to -4.OV to j and 10.
Ｐ型基板に負電圧を与えるＣ−ＭＯＳ回路では、次の問
題がある。即ちＰ型基板のＣ−ＭＯＳ回路ではＮ型ウェ
ル１２とＰ型基板１０とＮ＋＋ソース領域１４でＮＰＮ
！−ランジスタ（Ｑａとする）を構成し、またＰ＋型
ソース領域２２とＮ型ウェル１２とＰ型基板１０でＰＮ
Ｐ ）ランリスク（Ｑｂとする）を構成し、これらを全
体では第４図に示すようにサイリスクを構成する。この
サイリスクは２層１０とＮ層１４との間が導通伏感にな
れば全体が導通し、層２２，１２，１０．１４を通って
電源ＶｃｃからＶｓｓへ電流が流れる。この電流は抵抗
などの電流制限素子がなければ短絡電流となり、場合に
よっては素子を破壊する。A C-MOS circuit that applies a negative voltage to a P-type substrate has the following problem. That is, in a C-MOS circuit with a P-type substrate, the N-type well 12, the P-type substrate 10, and the N++ source region 14 are NPN.
! - A transistor (designated as Qa) is formed, and the P+ type source region 22, the N type well 12, and the P type substrate 10 form a PN transistor.
P) constitutes a run risk (referred to as Qb), and these collectively constitute a Sai risk as shown in Fig. 4. When this SiRisk becomes conductive between the second layer 10 and the N layer 14, the whole becomes conductive, and current flows from the power source Vcc to Vss through the layers 22, 12, 10.14. This current becomes a short-circuit current if there is no current limiting element such as a resistor, and may destroy the element in some cases.
しかし通常はこのようなことは起らない。即ち基板１０
は負電位にバイアスされ、ソース領域１４はＶｓｓ（グ
ランド）へ接続されているなら、層１４．１０間のＰＮ
接合は逆バイアスされており、電流は流れない。該電流
はトランジスタＱａのヘース電流となるものであるから
、結局Ｑａはオフである。However, this usually does not happen. That is, the substrate 10
is biased to a negative potential and source region 14 is connected to Vss (ground), the PN between layer 14.10
The junction is reverse biased and no current flows. Since this current becomes the hess current of the transistor Qa, Qa is turned off after all.
しかし入力ＩＮに過大な電圧が加わると、層１４．１０
間のＰＮ接合がオンになることがある。However, if too much voltage is applied to the input IN, layer 14.10
The PN junction between them may turn on.
即ちこの種のＣ−ＭＯＳ回路ではトランジスタＱ１、Ｑ
２のゲート保護のために第５図に示すように、ゲート、
ソース間を短絡したＭＯＳ、トランジスタＱ３が入力端
子ＩＮ、電源Ｖｓｓ間に接続される。第５図で２６．２
８はＮ＋型領領域、トランジスタＱ３のソース、ドレイ
ン領域を形成する。That is, in this type of C-MOS circuit, transistors Q1 and Q
As shown in FIG. 5, the gate,
A MOS transistor Q3 whose sources are short-circuited is connected between the input terminal IN and the power supply Vss. 26.2 in Figure 5
8 forms an N+ type region and the source and drain regions of the transistor Q3.
３０はゲート電極でソース領域２６と共に電源Ｖｓｓへ
接続され、そしてドレイン領域２８は入力端子ＩＮへ接
続される。入力端ＩＮにノイズなどにより正の過大電圧
例えば＋２４Ｖ程度が印加されるとドレイン領域２８と
基板１０との間のＰＮ接合がブレークダウンし、過大電
圧はバルクへ落されて基板１０の電位が上昇し、Ｐ型基
板１０とＮ＋＋層２６との間のＰＮ接合が順バイアスさ
れるという問題が生じる。即ち、基板１０は負電位にバ
イアスされているが、この負電位はチャージポンプ型の
基板バイアス発生器によって与えられており、これは基
板を強力に負電圧に保持する能力はなくて、上記ブレー
クダウンで基板に多量の電荷が注入されると基板電位を
変動させてしまう。前述のように２６．１０間が順バイ
アスされて電流がａこれると、サイリスク （１４，１
０，１２，２２）はオンになり、Ｃ−ＭＯＳ回路がラッ
チアップする。A gate electrode 30 is connected together with the source region 26 to the power supply Vss, and the drain region 28 is connected to the input terminal IN. When a positive excessive voltage, for example, about +24 V, is applied to the input terminal IN due to noise or the like, the PN junction between the drain region 28 and the substrate 10 breaks down, the excessive voltage is dropped to the bulk, and the potential of the substrate 10 increases. However, a problem arises in that the PN junction between the P-type substrate 10 and the N++ layer 26 is forward biased. That is, the substrate 10 is biased to a negative potential, but this negative potential is provided by a charge pump type substrate bias generator, which does not have the ability to strongly hold the substrate at a negative voltage, and does not cause the above-mentioned break. If a large amount of charge is injected into the substrate when the device is down, the substrate potential will fluctuate. As mentioned above, when the current is forward biased between 26.10 and the current is a, the si risk (14,1
0, 12, 22) are turned on, and the C-MOS circuit latches up.
本発明はか＼る点を改善し、簡単な手段でＣ−ＭＯＳ回
路のラッチアップを防止しようとするものである。The present invention aims to improve these points and prevent latch-up of C-MOS circuits by simple means.
本発明は、バソクゲートハイアスの与えられる半導体基
板に形成されたＣ−ＭＯＳ回路において、端子ピンに接
続される該Ｃ−ＭＯＳ回路の入／出力端と電源間にゼナ
ーダイオードを接続して、該入出力端に過大電圧が印加
されるときＣ−ＭＯＳ回路に発生するラッチアップを阻
止するようにしてなることを特徴とするものである。次
に実施例を参照しながら構成作用を説明する。The present invention relates to a C-MOS circuit formed on a semiconductor substrate provided with a bathock gate bias, in which a Zener diode is connected between the input/output terminal of the C-MOS circuit connected to a terminal pin and the power supply. , is characterized in that latch-up that occurs in the C-MOS circuit when an excessive voltage is applied to the input/output terminal is prevented. Next, the structure and operation will be explained with reference to embodiments.
第１図は本発明の実施例を示し、（ａ＋はＣ−ＭＯＳ
ＬＳＩの入力段に通用した例、（ｂｌは同出力段に通
用した例を示す。ＱＩ Ｑ２はＣ−ＭＯＳインバータ
を構成するＰチャネル、Ｎチャネル各ＭＯＳＩ−ランリ
スク、Ｑ３はダ・イオード接続されたＭＯＳ）ランリス
クである。第１図（２１１に示すようにツェナーダイオ
ードＤｌ、Ｄ２を入力端ＩＮと電流ＶＳＳとの間に接続
すれば、入力端ＩＮに過大正電圧が印加してもラソチア
・ノブは生じない。即ちこの場合は第５図の層２８．１
０間のＰＮ接合がブレークダウンする前にゼナーダイオ
ードＤ１゜Ｄ２がブレークダウンし、過大正電圧を電源
Ｖｓｓ（グランド）へ落としてしまうので、該層２８゜
１０間のＰＮ接合のブレークダウンは発生せず、従って
基板１０の電位上昇、層１４，１０間のＰＮ接合の順バ
イアス、トランジスタＱａのオン従ってＣ−ＭＯＳイン
バータＱｌ、Ｑ２のラッチアップは発生しない。FIG. 1 shows an embodiment of the present invention, (a+ is C-MOS
An example that is applicable to the input stage of an LSI, (bl is an example that is applicable to the output stage of the same.QI Q2 is a P-channel, N-channel MOSI-run risk that constitutes a C-MOS inverter, and Q3 is a diode-connected (MOS) run risk. If Zener diodes Dl and D2 are connected between the input terminal IN and the current VSS as shown in FIG. 1 (211), the Lassocia knob will not occur even if an excessively positive voltage is applied to the input terminal IN. In this case, layer 28.1 in Figure 5
Before the PN junction between layers 28 and 10 breaks down, Zener diode D1゜D2 breaks down and drops the excessive positive voltage to the power supply Vss (ground), so the breakdown of the PN junction between layers 28 and 10 is Therefore, no rise in the potential of the substrate 10, no forward bias of the PN junction between the layers 14 and 10, no turning on of the transistor Qa, and no latch-up of the C-MOS inverters Q1 and Q2 occur.
第１図山）のような出力段回路でも、出力端ＯＵＴにノ
イズなどにより過大正電圧が印加されると、Ｃ−ＭＯＳ
インバータＱｌ、Ｑ２にラッチアップが発生する。即ち
この場合もＰ型基板上のトランジスタＱｌ、Ｑ２は第３
図から推測されるようにサイリスクを構成しており、出
力端ＯＵＴに過大正電圧が印加すると層１６．１０間の
ＰＮ接合がブレークダウンし、基板１０の電位を押し上
げ、層１４．１０間のＰＮ接合を順バイアスし、サイリ
スク（１４，１０，１２，２２）をオンにする。Even in an output stage circuit like the one shown in Fig. 1, if excessive positive voltage is applied to the output terminal OUT due to noise etc., the C-MOS
Latch-up occurs in inverters Ql and Q2. That is, in this case as well, the transistors Ql and Q2 on the P-type substrate are
As inferred from the figure, it constitutes a silicon risk, and when an excessively positive voltage is applied to the output terminal OUT, the PN junction between the layers 16 and 10 breaks down, pushing up the potential of the substrate 10 and increasing the voltage between the layers 14 and 10. Forward bias the PN junction and turn on the silicon risks (14, 10, 12, 22).
これを防くには出力端ＯＵＴと電源Ｖｓｓとの間にツェ
ナーダイオードＤｉ、Ｄ２を接続し、出力端ＯＵＴに過
大正電圧が加われば該ゼナーダイオードがブレークダウ
ンして該過大正電圧を電源Ｖｓｓへ落すようにするのが
よい。To prevent this, Zener diodes Di and D2 are connected between the output terminal OUT and the power supply Vss. It is better to let it fall.
ツェナーダイオ−）”Ｄｉ、Ｄ２の直列接続個数及びツ
ェナーダイオード単体のブレークダウン電圧などは、上
記の層１６．１０間又は層２８，１０間のブレークダウ
ンが生じる前に該ゼナーダイオードがブレークダウンし
、そして正常な入出力信号電圧ではブレークダウンしな
いような値に選定する。ツェナーダイオードのブレーク
ダウン電圧は通常９■程度である。なお第１図（ａｌ、
（ｂ）の入力端ＩＮ及び出力端ＯＵＴはＬＳＩパッケ
ージの端子ピンになるものであり、作業者の手が触れた
等により過大電圧が加わり易いものである。ＶｃＣ。The number of series-connected zener diodes (Di, D2) and the breakdown voltage of a single zener diode are such that the zener diode breaks down before the breakdown occurs between layers 16 and 10 or between layers 28 and 10. Then, select a value that will not cause breakdown under normal input/output signal voltages.The breakdown voltage of a Zener diode is usually about 9μ.
The input terminal IN and output terminal OUT in (b) serve as terminal pins of the LSI package, and are easily subject to excessive voltage when touched by an operator's hand. VcC.
Ｖｓｓも端子ピンを通して外部より供給される電源であ
る。Vss is also a power supply supplied from the outside through a terminal pin.
第２図はゼナーダイオードＤＩ、Ｄ２のＰ型箔Ｆｉ１０
上の構造を示す。Ｐ型基板１０にＮ型ウェル３６を形成
し、酸ウェルにＰ＋型層３４．Ｎ”型層４０を形成し、
Ｐ型層３４にはＮ＋型層３２をまたＮ 型層４０にはＰ
型層３８を形成し、５３２．３４でゼナーダイオード
Ｄ１をそして層３８．４０でゼナーダイオードＤ２を構
成する。Figure 2 shows Zener diode DI, D2 P-type foil Fi10
The structure above is shown. An N-type well 36 is formed in the P-type substrate 10, and a P+-type layer 34 is formed in the acid well. forming an N” type layer 40;
The P type layer 34 has an N+ type layer 32, and the N type layer 40 has a P type layer 32.
A mold layer 38 is formed, forming a zener diode D1 at 532.34 and a zener diode D2 at layer 38.40.
Ｎウェル３６により分離されているので、ゼナーダイオ
ードＤｉ、Ｄ２がブレークダウンしても、チャージポン
プ型基板バイアス発生器により負電位を与えられている
基Ｆｊ、１０の電位に変動を生じることはない。なおゼ
ナーダイオードＤ２側のＮウェルは省略してもよい。Since they are separated by the N well 36, even if the zener diodes Di and D2 break down, the potential of the groups Fj and 10, which are given a negative potential by the charge pump type substrate bias generator, will not change. do not have. Note that the N-well on the Zener diode D2 side may be omitted.
以上説明したように本発明ではゼナーダイオードを接続
するという簡単な手段でＰ基板搭載Ｃ−ＭＯＳインバー
タの過大正入力電圧時のラッチアップを防止でき、甚だ
有効である。As explained above, the present invention is extremely effective in preventing latch-up of the P-substrate-mounted C-MOS inverter at the time of excessive positive input voltage by the simple means of connecting Zener diodes.
第１図は本発明の実施例を示す回路図、第２図はゼナー
ダイオードの構造を示す説明図、第３図〜第５図はラッ
チアップの説明図である。
図面で、１０はＰ型半導体基板、Ｑｌ、Ｑ２はＣ−ＭＯ
Ｓインバータを構成するＭｏｓ＋−ランリスク、ＩＮ、
ＯＵＴは人、出力端子ピン、Ｖｃｃ。
Ｖｓｓは電源、Ｄｉ、Ｄ２はゼナーダイオード、Ｑ３は
ダイオード接続されたＭｏＳトランジスタである。FIG. 1 is a circuit diagram showing an embodiment of the present invention, FIG. 2 is an explanatory diagram showing the structure of a Zener diode, and FIGS. 3 to 5 are explanatory diagrams of latch-up. In the drawing, 10 is a P-type semiconductor substrate, Ql, Q2 are C-MO
Mos + - run risk, IN, which constitutes the S inverter
OUT is human, output terminal pin, Vcc. Vss is a power supply, Di and D2 are Zener diodes, and Q3 is a diode-connected MoS transistor.
Claims (3)
形成されたＣ−ＭＯＳ回路において、端子ピンに接続さ
れる該Ｃ−ＭＯＳ回路の入／出力端と電源間にゼナーダ
イオードを接続して、該入出力端に過大電圧が印加され
るときＣ−ＭＯＳ回路に発生するラッチアップを阻止す
るようにしてなることを特徴とするＣ−ＭＯＳ回路。(1) In a C-MOS circuit formed on a semiconductor substrate to which a back gate bias is applied, a Zener diode is connected between the input/output terminal of the C-MOS circuit connected to the terminal pin and the power supply. A C-MOS circuit characterized in that it is configured to prevent latch-up occurring in the C-MOS circuit when an excessive voltage is applied to an input/output terminal.
入力端とグランド側電源との間にダイオード接続された
ＭＯＳトランジスタが接続され、ゼナーダイオードは該
ＭＯＳトランジスタに並列に接続されたことを特徴とす
る特許請求の範囲第１項記載のＣ−ＭＯＳ回路。(2) The C-MOS circuit is an input stage C-MOS circuit,
The C-MOS according to claim 1, characterized in that a diode-connected MOS transistor is connected between the input terminal and the ground side power supply, and the Zener diode is connected in parallel to the MOS transistor. circuit.
出力端とグランド側電源との間にゼナーダイオードが接
続されてなることを特徴とする特許請求の範囲第２項記
載のＣ−ＭＯＳ回路。(3) The C-MOS circuit is an output stage C-MOS circuit,
3. The C-MOS circuit according to claim 2, further comprising a Zener diode connected between the output terminal and a ground side power supply.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59186785A JPS6164152A (en) | 1984-09-06 | 1984-09-06 | C-mos circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59186785A JPS6164152A (en) | 1984-09-06 | 1984-09-06 | C-mos circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6164152A true JPS6164152A (en) | 1986-04-02 |
Family
ID=16194548
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59186785A Pending JPS6164152A (en) | 1984-09-06 | 1984-09-06 | C-mos circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6164152A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5276350A (en) * | 1991-02-07 | 1994-01-04 | National Semiconductor Corporation | Low reverse junction breakdown voltage zener diode for electrostatic discharge protection of integrated circuits |
| JP2004512685A (en) * | 2000-10-16 | 2004-04-22 | コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ | Integrated circuit with overvoltage protection and method of manufacturing the same |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5211880A (en) * | 1975-07-18 | 1977-01-29 | Toshiba Corp | Semiconductor integrated circuit device |
| JPS5771179A (en) * | 1980-10-22 | 1982-05-01 | Hitachi Ltd | Input protective circuit device |
-
1984
- 1984-09-06 JP JP59186785A patent/JPS6164152A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5211880A (en) * | 1975-07-18 | 1977-01-29 | Toshiba Corp | Semiconductor integrated circuit device |
| JPS5771179A (en) * | 1980-10-22 | 1982-05-01 | Hitachi Ltd | Input protective circuit device |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5276350A (en) * | 1991-02-07 | 1994-01-04 | National Semiconductor Corporation | Low reverse junction breakdown voltage zener diode for electrostatic discharge protection of integrated circuits |
| JP2004512685A (en) * | 2000-10-16 | 2004-04-22 | コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ | Integrated circuit with overvoltage protection and method of manufacturing the same |
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