JPS63301558A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To improve a device of this design in latch-up resistance property by a method wherein a source and a drain electrode of a MOS transistor are connected with a first node to which a first power supply potential is applied and a drain electrode of a MOS transistor is connected with a second node to which a second power supply potential is applied. CONSTITUTION:A first node 11 and a second node 12 supplied with a first and a second power supply potential respectively are provided. And, a MOS transistor 26 is provided, where a source electrode 22 and a drain electrode 23 are connected with the said first node 11 and the drain electrode 23 is connected with the said second node 12. When voltage between the gate electrode 24, connected with the first node, of the MOS transistor 26 and the drain electrode 23 connected with the second node exceeds the threshold voltage of this transistor, the resistor is rendered to be on and then the current path is established between the first and the second node, and a surge applied onto one node is absorbed by the other node. By these processes, a latch-up resistant property can be improved.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to a complementary MO3 semiconductor integrated circuit device, and in particular to a semiconductor with improved latch-up resistance against surge contamination from a power supply terminal. The present invention relates to integrated circuit devices.

(Prior art) In a complementary MO8 semiconductor integrated circuit device (0MO8-IC), surges entering the signal output terminal (overvoltage or overvoltage whose value changes suddenly with respect to the signal voltage or current during normal operation) It is well known that the so-called latch-up phenomenon occurs when the internal parasitic thyristor is turned on and a large current continues to flow between the power supplies.Furthermore, not only the signal output terminal It is known that a launch-up phenomenon also occurs with respect to signal input terminals due to the effects of providing input protection diodes and the like.

Conventionally, in order to prevent latch-up phenomena related to signal input/output terminals from occurring, measures such as strengthening the substrate bias near the signal input/output terminals were taken to prevent the mixed surge from spreading to internal elements. These surges are absorbed by the power terminal.

However, when a surge is directly applied to the power supply terminal, the bipolar transistor itself that constitutes the parasitic thyristor tends to turn on. Further, since the surge is applied to the power supply which is originally an escape route for the surge when the surge is applied, it becomes difficult for the external surge to be absorbed and the parasitic thyristor is easily turned on. Therefore, the latch-up resistance against surges introduced from the power supply terminal is poorer than that of other terminals. However, in the past, no surge countermeasures have been taken for this power supply, so there is a problem in that a latch-up phenomenon is likely to occur due to surges entering from the power supply terminal.

(Problems to be Solved by the Invention) As described above, in the conventional method, no measures have been taken against external surges entering from the power supply terminal, and therefore, there is a drawback that the latch-up resistance of the power supply terminal is poor.

The present invention has been made in consideration of the above-mentioned circumstances, and its purpose is to provide a semiconductor integrated circuit device that can improve latch-up resistance against external surges that enter from the power supply terminals. .

[Structure of the Invention] (Means for Solving the Problems) A semiconductor integrated circuit device of the present invention connects a source electrode and a gate electrode of a MOS transistor to a first node to which a first power supply potential is applied, The drain electrode of the MOS transistor is connected to a second node to which a second power supply potential is applied.

(Function) In the semiconductor integrated circuit device of the present invention, first, the first and second
Under normal conditions, when no surge is applied to the node,
The MOS transistor is in an off state. Therefore, in this case, the MOS transistor has no effect.

On the other hand, when a high voltage surge is applied to the first and second nodes, the potential between both nodes fluctuates and its value becomes much larger than during normal operation.

At this time, the following effects work.

First, when the voltage between the gate electrode of the MOS transistor connected to the first node and the drain electrode connected to the second node exceeds the threshold voltage ra of this transistor, this transistor turns on. . As a result, a current path is generated between the first and second nodes, and a surge applied to one node is absorbed by the other node.

Furthermore, when the voltage between the source and drain electrodes of the MoS transistor increases and exceeds the punch-through voltage, this transistor causes a punch-through phenomenon.
A short circuit occurs between the source and drain electrodes. As a result, a current path is generated between the first and second nodes, and a surge applied to one node is absorbed by the other node.

Furthermore, the source or drain voltage increases, and the M
The source and drain regions of the oS transistor are the emitter,
When a base current flows through a PNP type or NPN type parasitic bipolar transistor serving as a collector region, this parasitic bipolar transistor is turned on, and the collector current generates a current path between the first and second nodes, and one side A surge applied to one node is absorbed by the other node. Note that when a large current surge is applied, the collector current is mainly generated by this parasitic bipolar transistor.

(Example) Hereinafter, the present invention will be described in detail with reference to the drawings.

FIG. 1 is a circuit diagram showing the configuration of a first embodiment of the present invention.

In the figure, 11 is a high potential VDD potential, for example +5V
12 is an external power supply connection terminal of the IC to which a low potential GND potential (OV) is applied. Inside the IC, the terminal 11 for Voo has a P-channel enhancement type MOS.
The source electrode and gate electrode of transistor 13 are connected. The drain electrode of this transistor 13 is connected to the GND terminal 12. Furthermore, the back gate electrode, so-called substrate, of the transistor 13 is connected to the terminal 11.

FIG. 2 is a cross-sectional view showing an element structure when the circuit shown in FIG. 1 is implemented as an integrated circuit. In the figure, 21 is an N-type substrate, 22 and 23 are formed within this N-type substrate 21, and P+
There are source and drain regions consisting of type regions, 24 a gate electrode, and 25 an N+ region for substrate bias provided to supply a VOO potential to the substrate 21. As shown,
In the substrate 21, the source and drain regions 22 and 23 are used as collector and emitter, and the substrate 21 is used as a base for the PNPI-
The transistor 26 is generated parasitically, and furthermore, this P
A resistor 27 is parasitically connected between the base of the NP transistor 26 and the N+ region 25 due to the resistance component of the substrate 21 itself. In addition, the above parasitic PNP
The positions of the emitter and collector of the transistor 26 may be reversed depending on the potential relationship at that time.

In such a configuration, a surge is applied to the terminals 11 and 12 in the following four cases.

■ When a negative surge voltage is applied to terminal 11 of VDD ■ When a positive surge voltage is applied to terminal 12 of GND ■ When a positive surge voltage is applied to terminal 11 of Voo ■ GND When a surge voltage of negative polarity is applied to the terminal 12 of (1), the operation in case (2) will be explained first. That is, when a negative surge voltage is applied to the terminal 11 to which the VDD potential of +5V is applied and the VDD potential decreases, the potential of the gate N-pole 24 of the transistor 13 also decreases as the Voo potential decreases. Then, this gate potential becomes the threshold voltage of the transistor 13 (P channel Mo
For S transistors, if the voltage exceeds (usually about -1V), the second
A channel layer is formed between the source and drain l[22 and 23 in the figure, and the transistor 13 is turned on. As a result, a channel current i cha as shown in FIG. 2 flows.

Further, as the Voo potential decreases, the potential of the source region 22 of the transistor 13 also decreases. At this time, due to the presence of the resistor 27, the potential of the substrate 21 is in the negative region ii! ! The potential of 22 does not change suddenly. Then, when the source potential with respect to the potential of the substrate 21 exceeds the breakdown voltage Vs of the PN junction, which is usually about 20V to 30V, the substrate 21
A breakdown current begins to flow from 1 to the source region 22. As a result, the potential of the substrate 21 becomes unstable and attempts to approach the lowered source potential. Then, as the substrate potential approaches the source potential, the substrate 2
The potential of 1 is the forward voltage (VF
), a PN junction current begins to flow from the drain region 23 toward the substrate 21. This current is a parasitic PNP
This becomes the base current of the transistor 26, and when the transistor 26 is turned on, the collector current i as shown in FIG.
cot flows.

Furthermore, as the VDD potential decreases, the potential difference between the source region 22 and drain region 23 of the transistor 13 exceeds the punch-through voltage (about 10 V to 20 V, depending largely on the channel length of the MO8I transistor). , a short circuit occurs between the source and train regions, and a punch-through current i pan as shown in FIG.
flows.

Next, the operation in case (2) above will be explained. That is, GND
When a positive surge voltage is applied to the terminal 12 of the transistor 12 and the GND potential rises, if the potential of the drain region 23 exceeds the threshold voltage of the P-channel MO8I transistor 13 with respect to the potential of the gate electrode 24, the transistor 13 It turns on, and a channel current i cha as shown in FIG. 2 flows.

Moreover, the GND potential rises, and the PN
When the forward voltage of the junction is exceeded, a PN junction current begins to flow from the drain region 23 toward the substrate 21. This current becomes the base current of the parasitic PNP transistor 26, which turns on and a collector current 1 col as shown in FIG. 2 flows.

In case (2) above, that is, when a positive surge voltage is applied to the VDO terminal 11 and the VDO potential rises, the potential of the source region 22 rises. When the source potential exceeds the forward voltage of the PN junction with respect to the potential of the substrate 21, current begins to flow from the source region 22 to the substrate 21. This current becomes the base current of the parasitic PNP transistor 26, and this transistor 26 is turned on, and as shown in FIG. 3, a collector current 1 col in the opposite direction to that in FIG. 2 flows.

In the case of (2) above, that is, when a negative surge voltage is applied to the GND terminal 12 and the GND potential drops, the potential of the drain region [23] drops. When the breakdown voltage of the PN junction is exceeded with respect to the potential of the substrate 21,
A breakdown current begins to flow from the substrate 21 toward the drain region 23 . As a result, the potential of the substrate 21 also decreases and approaches the drain potential. Then, as the substrate potential approaches the train potential, the substrate 21
When the potential of P exceeds the forward voltage of the PN junction with respect to the source region 22, P
N junction current begins to flow. This becomes the base current of the parasitic PNP transistor 26, and after this, the transistor 2
6 is turned on, and a collector current of 1 col flows in the direction shown in FIG.

Furthermore, in the case of (2), when the potential difference between the source region 22 and drain region 23 of the transistor 13 exceeds the punch-through voltage as the GND potential decreases, a short circuit occurs between the source and drain regions 22 and 23, and both regions There is a third
Punch-through current i_pan flows in the direction shown in the figure.

In this way, in the above embodiment circuit, the terminal 11 or 12
When a positive or negative surge voltage is applied to the source and drain regions 22 and 23, various currents 1cha and 1col as described above are generated between the source and drain regions 22 and 23.

i pan flows and these currents cause terminal 11.1
A surge voltage applied to one of the two is absorbed by the other.

FIG. 4 is a sectional view showing an element structure when the above-described embodiment circuit is incorporated together with a CMOS inverter circuit used inside a semiconductor circuit device. In the figure, 30 is a P-well region formed in an N-type substrate, 31 and 32 are source and drain regions of an N-channel MOS transistor formed in this P-well region 30 and forming a CMOS inverter, and 33 is this transistor. , 34 is a bias P'' region for supplying a GND potential to the P well region 1430, 35 and 36 are sources of P channel MOS transistors formed in the N type substrate 21 and forming a CMOS inverter; The drain region 37 is the gate electrode of this transistor.

Here, by forming a CMOS inverter in the N type substrate 21, a parasitic N
The parasitic thyristor is formed by the PN transistor 38 and the parasitic PNP transistor 39 having the P+ type region 36 as an emitter, the N type substrate 21 as a base, and the P well region 30 as a collector.

When a surge voltage is applied to one of the terminals 11 and 12, a current as shown by the arrow in the figure flows through the protective transistor 13, and a trigger current that turns on the parasitic thyristor due to the surge application, that is, forms a parasitic thyristor. PNP transistor 39 and NPN transistor 3
It works to prevent the emitter current flowing through the pull region 1g36. The latch-up characteristics are improved.

FIG. 5 is a circuit diagram showing the configuration of a second embodiment of the invention.

In the figure, 11 and 12 are the high potential Voo potential, GN
These are external power supply connection terminals to which the D potential is applied.

Inside the IC, the drain electrode of an N-channel enhancement type MOS transistor 14 is connected to the terminal 11. A source electrode and a gate electrode of this transistor 14 are connected to the terminal 12. Roughly speaking, the back gate electrode, so-called substrate, of the transistor 14 is connected to the terminal 12.

FIG. 6 is a sectional view showing an element structure when the circuit shown in FIG. 5 is realized by an integrated circuit using a P-well region. In the figure, 41 is an N-type substrate, 42 is a P-well region formed in this substrate 41, and 43 and 44 are N+-type regions formed in this P-well region 42. Source, drain region, 4
5 is the gate electrode of this transistor, 46 is P1 for bias for setting the P well region 42 to GND potential.
A region 47 is an N+ region for biasing to set the N type substrate 41 to VDD potential. As shown in the figure, within the P well region 42 are N+ type source and drain regions 43.
．． An NPNI-transistor 48 having collector and emitter 44 and P-well region 42 as a base is generated parasitically, and furthermore, between region 46 and the base of the parasitic bipolar transistor 48, the P-well region 42 itself has A resistor 49 is parasitically connected by the resistive component.

Note that the positions of the emitter and collector of the parasitic NPN transistor 48 may be reversed depending on the potential relationship at that time.

Even in a circuit having such a configuration, a surge is applied to the terminals 11 and 12 in the cases (1) and (2) described above.

First, in the case of ■, that is, when a negative surge voltage is applied to the terminal 11 of VOO and the VDD potential decreases, the potential of the drain potential region 44 of the transistor 14 decreases as the Voo potential decreases. . Then, the drain potential is lower than the gate potential by the threshold voltage valve (
In an N-channel MOS transistor, when the voltage exceeds +1V (normally about +1V), the source and drain regions 43 and 44 in FIG.
A channel layer is formed in between, and the transistor 14 is turned on. As a result, the channel current as shown in Figure 6:
cha is flowing.

Further, when the potential of the drain region 44 of the transistor 14 decreases and the drain potential exceeds the forward voltage of the PN junction with respect to the potential of the P-well region 42, the P-type well region 42
A PN junction current begins to flow from there toward the drain region 44. This current becomes the base current of the parasitic bipolar transistor 48, and this transistor 48 is turned on and the sixth
A collector current of 1 col as shown in the figure flows.

In case (2), that is, when a positive surge voltage is applied to the GND terminal 12 and the GND potential rises, the potential of the gate electrode 45 rises. When the gate potential exceeds the threshold voltage of the N-channel MoS transistor with respect to the potential of the drain region 44, the transistor 14 is turned on, and the channel current i cha flows in the direction shown in FIG.
flows.

Furthermore, when the GND potential rises and the potential of the source region 43 rises and exceeds the breakdown voltage of the PN junction with respect to the potential of the P-well region 42, a breakdown current flows from the source region 43 toward the P-well region 42. begins to flow. As this current flows, P well f! 4 area 42
The potential of increases. Then, when the potential of the P well fr4 region exceeds the forward voltage of the PN junction with respect to the potential VDD of the drain region 44, the P well region 42 to the drain region 4
4, the PN junction current begins to flow. This current is a parasitic NPN
This becomes the base current of the transistor 48, which turns on the transistor 48, and a collector current 1 col flows in the direction shown in FIG.

Furthermore, when the potential of the source region 43 increases and the potential difference between the source region 43 and the fourth drain region 44 exceeds the punch-through voltage, a short circuit occurs between the source and the train, and between the two regions 43 and 44. A bunt-through current ipan as shown in FIG. 6 flows.

In case (2) above, that is, when a positive surge voltage is applied to the terminal 11 and the VDD potential rises, the potential of the drain region 44 rises. When the train potential exceeds the breakdown voltage of the PN junction with respect to the potential of the P-well region 42, the drain region 44
Breakdown current begins to flow. As this current flows, the potential of the P well region 42 increases. When the potential of this P well region 42 exceeds the forward voltage of the PN junction with respect to the potential GND of the source region 43, a PN junction current begins to flow from the P well region 42 to the source region 43. This current becomes the base current of the parasitic NPN transistor 48, and this transistor 48 is turned on.
As shown in the figure, a collector current 1 col flows in the opposite direction to that in the case of FIG. 6 above.

Roughly speaking, when the drain potential increases and the potential difference between the source region 43 and the drain region 44 exceeds the punch-through voltage, a short circuit occurs between the source and drain regions, and there is a gap between the two regions as shown in FIG. Punch-through current i in the direction
Pan is flowing.

In case (2), a negative surge voltage is applied to the GND terminal 12, and when the GND potential drops, the potential of the source region 43 drops. And P well territory tii1
When the source potential exceeds the forward voltage of the PN junction with respect to the potential of 42, a forward current of the PN junction begins to flow from the P well region 42 toward the source region 43. This becomes the base current of the parasitic NPN transistor 48, and after this,
The transistor 48 is turned on and a collector current 1 col flows in the direction shown in FIG.

In this way, also in the case of this embodiment circuit, when a positive or negative surge voltage is applied to the terminal 11 or 12, various currents i aha as described above are generated between the source and drain regions 43 and 44. .

i col and i pan flow, and the surge voltage applied to one of the terminals 11.12 is absorbed by the other by these currents.

FIG. 8 is a sectional view showing an element structure when the above-described embodiment circuit is incorporated together with a CMOS inverter circuit used in a semiconductor circuit device. In the figure, 51 and 52 are formed in the P-well region 1d42 and are the source and drain regions of the N-channel MOS transistor forming the CMOS inverter, 53 is the gate electrode of this transistor, and 54
and 55 is a source and train region on the P-channel MOS transistor side forming the CMOS inverter, which is formed in the N-type substrate 41, 56 is a gate electrode of this transistor, and 57 is a bias supplying the Voo potential to the N-type substrate 41. There is an N+ region for

Here, by forming a CMOS inverter in the N type substrate 41, a strange N
The parasitic thyristor is parasitically generated between the PN transistor 58 and the parasitic PNP transistor 59 which has the P+ type region 54 as its emitter, the N type substrate 41 as its base, and the P well region 42 as its collector.

When a surge voltage is applied to one of the terminals 11 and 12, a current as shown by the arrow in the figure flows through the protective transistor 14, and a trigger current that turns on the parasitic thyristor due to the surge application, that is, forms the parasitic thyristor. This serves to prevent the emitter current flowing through regions 54 and 51 in PNP transistor 59 and NPN transistor 58 from increasing. As a result, the parasitic thyristor is prevented from turning on, and the latch-up resistance against surges introduced from the power supply terminal is improved.

FIG. 9 is a circuit diagram showing the configuration of a third embodiment of the present invention. This embodiment circuit includes both the P-channel MO8 transistor 13 of the first embodiment circuit and the N-channel MOS transistor 14 of the second embodiment circuit. 10 and 11 show an element structure when the circuit shown in FIG. 9 is implemented as an integrated circuit using a P-well region. In addition, Fig. 10 shows the case where the surge input is the above-mentioned ■, ■, and Fig. 11 shows the case where the surge input is the above-mentioned ■.
, ■ cases are shown, respectively. In the figure, 21 is an N type substrate, 22 and 23 are P channel MOS transistors 1 formed in this N type substrate 21 and consisting of a P1 type region.
3, the source and drain regions 1ii!, 24 the gate electrode, and 25 the N+ region 26 provided for supplying the Voo potential to the substrate 21, the source and drain regions 1ii! Parasitic PN with collector and emitter at 22°23 and base at substrate 21
A P transistor, 27 is an anomalous resistance due to the resistance component of the substrate 21 itself, 42 is a P well region formed in the substrate 21, and 43 and 44 are P well regions 4.
N channel MOS consisting of N+ type region formed in 2
The source and drain regions of the transistor 14, 45 the gate electrode of this transistor, 46 the P+ region for setting the P well region 42 at the GNDIi level, 48 the N+ type source and drain regions [43 and 44 the collector and emitter] , a parasitic NPN transistor based on the P well region 42, and 49 a parasitic resistance due to a resistance component of the P well region 1ilt42 itself.

In a circuit with such a configuration, the ability for surges to be absorbed by the power supply is different from that in the first and second embodiment circuits because the current path between the terminals 11 and 12 is two, one on the N channel side and the other on the P channel side. It is fully enhanced by increasing the number of points. Therefore, the surge can be absorbed by the power supply in a shorter time, and the latch-up resistance can be greatly improved.

FIG. 12 collectively shows the currents generated in the transistors 13 and 14 when a surge is applied to the terminals N and 12 in the embodiment circuit of FIG. 9. That is,
In FIG. 12, when a negative surge is applied to the VOO potential terminal, the P-channel MOS transistor 13
A channel current, a collector current, and a punch-through current are generated in the N-channel MO8 transistor 14, and a channel current and a collector current are generated in the N-channel MO8 transistor 14. When a positive surge is applied to the VDD potential terminal, the P-channel MOS
A collector current is generated in transistor 13, and a collector current and punch-through current are generated in N-channel MOS transistor 14. Further, when a positive surge is applied to a terminal at the GND potential, a channel current and a collector current are generated in the P-channel MOS transistor 13, and a channel current, a collector current, and a punch-through current are generated in the N-channel MOS transistor 14. GND
When a negative surge is applied to the potential terminal, a collector current and a punch-through current are generated in the P-channel MOS transistor 13, and the N-channel MOS transistor 14
A collector current is generated.

As is clear from FIG. 12, for example, when a negative surge is applied to the GND terminal 12, in the embodiment circuit shown in FIG. Only collector current is generated. However, in the case of this embodiment circuit, a collector current and a punch-through current are generated in the P-channel MOS transistor 13, and a current on the P-channel side is added, so that the surge is quickly absorbed by the power supply.

Therefore, in the case of this embodiment circuit, N-channel MoS
The latch-up resistance is greatly improved compared to the case where only the transistor 14 or the P-channel MOS transistor 13 is provided.

13 and 14 respectively show the external power connection terminal of the 0MO8-I C of the present invention, which is provided with both the P-channel MO8 transistor 13 and the N-channel MOS transistor 14 as shown in FIG. 9 above. On the other hand, it is a circuit diagram showing the configuration of a test circuit for testing whether or not a latch-up phenomenon occurs when a high voltage surge is applied. FIG. 13 shows a test circuit that applies a surge to the VDD potential, and the terminal 11 of 0MO8-IC60 is supplied with the Voo potential, and the terminal 12 is supplied with the GN[) potential. In this circuit, initially, by closing the switch 61, a capacitor 63 having a voltage of, for example, 200 pF is charged with a voltage of 1t)ii62. Next, by opening switch 61 and closing switch 64, a surge is applied to terminal 11 by applying and discharging the charge of capacitor 63 to terminal 11.

As a result, if a latch-up phenomenon occurs, the voltage of the heavy pressure source 62 at that time can be regarded as a surge voltage at which the latch-up phenomenon occurs.

FIG. 14 shows a test circuit that applies a surge to the GND potential. By closing the switch 64, the charged charge of the capacitor 63 is applied to the terminal 12, and thereby the latch-up generation voltage at the terminal 12 is measured. Can be done.

Using such a test circuit, we tested a conventional IC in which a protective transistor such as that of the present invention is not inserted between the power supply terminals 11 and 12. In the test circuit shown in FIG. When the voltage was below 50 V (positive polarity surge) and -50 V (negative polarity surge), latch-up occurred in the test circuit shown in FIG. 14 when the voltage was below 50 V and -50 V, respectively. On the other hand, the I of this invention
When testing C, it was found that latch-up occurred in the test circuit shown in Fig. 13 when the charging voltage of the capacitor 63 reached 5oov and -500V, and in the test circuit shown in Fig. 14 when the charging voltage of the capacitor 63 reached 5oov and -500V, respectively. It did not occur. As a result, it can be seen that the circuit of the present invention has significantly improved latch-up resistance against surge voltages that enter the external power supply connection terminal.

It goes without saying that the present invention is not limited to the above-mentioned embodiments, and can be implemented in various other ICs. For example, in each of the above embodiments, the present invention can be applied to an IC with two power supplies.
However, there are also 0MO8-ICs with 3 power sources, 4'7ii sources, or more, and these ICs also have a P channel or By inserting one or both of the N-channel MOS transistors, it is possible to improve the latch-up resistance against surges entering the external power supply connection terminal.

FIG. 15 is a circuit diagram showing the configuration of a fourth embodiment of the present invention. This is implemented in an IC that uses a power supply, and includes an external power supply connection terminal 71 to which a high potential VDD potential is applied and an external power supply connection terminal 1 to which a quasi-low potential Vss2 potential is applied.
A P-channel MOS transistor 81 and an N-channel MO8 transistor 82 are connected between the external power supply connection terminal 71 and the external power supply connection terminal 73 to which the low potential V881 potential is applied.
and an N-channel MOS transistor 84, and a P-channel MO8t-transistor 85 and an N-channel MO8l-transistor 86 are inserted between terminals 72 and 73, respectively. The gate electrode of each transistor is biased to a predetermined power supply potential so that it will not turn on when a normal power supply potential is applied between the terminals. In the case of this embodiment circuit, either a P-channel transistor or an N-channel transistor may be provided between each pair of terminals, but it is preferable to provide both in order to increase the current path due to surges.

FIG. 16 is a circuit diagram showing the configuration of a fifth embodiment of the present invention. This is implemented in an IC that uses four potential power supplies, and there is a P-channel MO3) between the external power supply connection terminal 91 to which the Voo1 potential is applied and the external power supply connection terminal 92 to which the Voo2if potential is applied. −Rangister
101 and an N-channel MOS transistor 102,
A P-channel MOS is connected between the external power supply connection terminal 92 and the external power supply connection terminal 93 to which the Vss2 potential is applied.
Transistor 103 and N-channel MO8 transistor
104 is connected to the external power supply connection terminal 93 and the low potential Vs.
A P-channel MOS transistor 105 and an N-channel M
An OS transistor 106 is connected between terminals 91 and 93, a P channel MOS transistor 107 and an N channel MoS transistor 108 are connected between terminals 91 and 94, and a P channel MoS transistor 109 and an N channel MOS transistor 110 are connected between terminals 91 and 94. But terminals 92 and 9
4, a P-channel MoS transistor 111 and an N-channel MOS transistor 112 are inserted, respectively. Also in this case, the gate electrode of each transistor is biased to a predetermined power supply potential so that it does not turn on when a normal power supply potential is applied to each terminal. Also, in the case of this example circuit,
Although either a P-channel or an N-channel transistor may be provided between each pair of terminals, it is effective to provide both.

FIG. 17 is a plan view showing the arrangement state when the MOS transistor 14 in the embodiment circuit of FIG. 5 is actually formed in a semiconductor integrated circuit device (semiconductor chip).

In the figure, 200 is a semiconductor chip, and around this semiconductor chip 200, a plurality of external connection terminals 201 and an external power supply connection terminal 12 for a low potential GND potential are provided. The transistor 14 is arranged between the external power supply connection terminal 12 and one external connection terminal 201 so as to be adjacent to the terminal 12. The source region, gate electrode, and back gate of this transistor 14 are connected to the GND phase-saving phase power supply connecting terminal 12.
The VDD potential supplied from a high potential external power supply connection terminal (not shown) is applied to the drain region.

By arranging the MOS transistor 14 adjacent to the external power supply connection terminal 12 for GND potential, when a surge is input from the outside to the external N source connection terminal 12, the transistor 14 is quickly turned on. Therefore, the surge can be effectively released to the high potential VDD potential. In addition, since input/output transistors that are provided near other signal input/output external terminals are not provided near the external power terminal, empty space tends to occur around the terminal, especially when connected to the external power terminal. between other terminals or outside F.
By arranging this transistor 14 around the A power supply terminal, extra area for forming this transistor is unnecessary. As a result, the chip size does not increase, and the cost does not increase due to the provision of the transistor 14.

FIG. 18 is a plan view showing another arrangement state in which the MOS transistor 14 in the embodiment circuit of FIG. 5 is actually formed within a semiconductor chip.

In this case, the MOS transistor 14 is arranged below the external 'R source connection terminal 12 for GND potential. Since the area of the external power supply connection terminal is usually about 10,000 μm 2 , a transistor with the same area can be formed below this terminal.

In this case as well, the source region, gate electrode, and back gate of the transistor 14 are all connected to the terminal 12, and the VDD potential is applied to the drain region.

FIG. 19 is a diagram showing the cross-sectional structure of the portion shown in FIG. 18 above. A P-well region 212 is formed on the N-type substrate 211, and a pair of N+-type regions 213214, which become the source and drain regions of the MOS transistor 14, are further formed on the surface of the P-well region Ia212. . Note that 215 is a P well region [P+ type guard ring region provided around 212, and 216 is a MO
The gate electrode 217 of the S transistor 14 is a metal electrode made of Aλ, for example, which is used as the external power connection terminal 12 for GND, and this metal electrode 217 is connected to the N+ type region 13, the gate 7!1 pole 216, and the guard ring. They are each connected to a region 215. Furthermore, the other N+
A metal electrode 218 made of AR, for example, is connected to the mold region 214, and a VDD potential is applied to this metal electrode 218.

In this case as well, if a surge from the outside occurs at the external power connection terminal 12,
, the transistor 14 quickly turns on and can effectively release the surge to the high potential Voo. Further, since the MOS transistor 14 is arranged and formed under the terminal 12, an extra area for forming the transistor 14 is unnecessary. As a result, the chip size does not increase, and the cost does not increase due to the provision of the transistor 14.

FIG. 20 shows the M of the P channel in the embodiment of FIG.
7 is a plan view showing another arrangement state when the OS transistor 13 is formed in an actual semiconductor chip. FIG. In this case, the MOS transistor 13 is arranged and formed at the corner of the semiconductor chip 200. In the figure, 201 is an external connection terminal, and 202 is a G
The wiring for the NDI potential, 203, is the wiring for the Voo potential, and the source region, gate electrode, and back gate of the transistor 13 are all at the above-mentioned V. . It is connected to the wiring FJ 203 for potential, and the drain region is connected to the wiring 20 for GND potential.
Connected to 2.

In general, in semiconductor chips, there are four areas: the periphery of the chip and the inside of the chip.
Because No. 5 transmission and reception is performed, the wiring for transmitting and receiving signals at the corner of the chip tends to be dense on the inside and sparse on the outside. Therefore, forming the MOS transistor 13 at the corner of the chip is extremely effective from the viewpoint of effectively utilizing the free area, and further reduces the cost due to the increase in chip size due to the provision of the transistor. It has the advantage of not causing any increase.

That is, in this case, the latch-up resistance can be freely improved simply by extending the power supply wiring to the transistor 13. Note that FIG. 21 shows the arrangement of the transistors 13 in FIG. 20 in more detail.

FIG. 22 shows P″ft7ft in the embodiment shown in FIG.
FIG. 3 is a plan view showing an arrangement state in which both 7-channel MOS transistors 13 and 14 are formed in an actual semiconductor chip. In the figure, 200 is a semiconductor chip, and around this semiconductor chip 200 there are a plurality of external connection terminals 201, an external power supply connection terminal 11 for a high potential VDO potential, and an external power supply connection terminal for a low potential GND potential. 1
2 is provided. In this case, the P-channel MOS transistor 13 and the N-channel MOS transistor 14 are arranged adjacent to the terminal 201 on two mutually adjacent sides of the semiconductor chip 200, and have respective source regions, gate electrodes, back gates, and GN the drain region
Wiring 202 or ■ for Dit position. Wiring 2 for o1 position
03.

By arranging and forming both transistors on two different sides of the semiconductor chip in this manner, it is possible to provide a sufficient distance between the two transistors. Therefore, by providing both transistors 13 and 14, it is possible to reduce the current amplification factor hfe of the PNP type and NPN type bipolar transistors in the newly formed parasitic silice structure. Therefore, the parasitic silis structure formed by both transistors themselves becomes difficult to turn on, and the latch-up resistance is improved because both transistors function to release the surge at the time of surge input to another power source, which is the original purpose.

FIG. 23 is a plan view showing another arrangement state in which both the P-channel and N-channel MoS transistors 13 and 14 in the embodiment of FIG. 9 are formed in an actual semiconductor chip. In this case, a P-channel MOS transistor 13 and an N-channel MOS transistor 14 are connected to terminals 201 on two opposing sides of the semiconductor chip 200, respectively.
It is arranged and formed adjacent to. By arranging both transistors 13 and 14 on opposite sides of the semiconductor chip in this way, it is possible to further increase the distance between the two transistors.

[Effects of the Invention] As described above, according to the present invention, it is possible to provide a semiconductor integrated circuit device that can improve latch-up resistance against external surges entering from a power supply terminal.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing the configuration of a first embodiment of the present invention;
2 and 3 are sectional views for explaining the operation of the first embodiment circuit, respectively, FIG. 4 is a sectional view showing the embodiment circuit together with a CMOS inverter circuit, and FIG. 5 is a sectional view of the circuit according to the present invention. A circuit diagram showing the configuration of the second embodiment, FIGS. 6 and 7 are cross-sectional views for explaining the operation of the second embodiment circuit, and FIG. 8 shows the circuit of the second embodiment. CM
9 is a circuit diagram showing the configuration of the third embodiment of the present invention, and FIGS. 10 and 11 are sectional views of the circuit of the third embodiment, respectively.
Figure 2 is a diagram for explaining the circuit of the third embodiment.
3 and 14 are circuit diagrams of test circuits used to test the characteristics of the third embodiment circuit, respectively, and FIG. 15 is a circuit diagram showing the configuration of a fourth embodiment of the present invention.
16 is a circuit diagram showing the configuration of a fifth embodiment of the present invention, FIG. 17 is a plan view showing the arrangement of transistors in the embodiment circuit of FIG. 5, and FIG. 18 is an embodiment of the embodiment of FIG. 5. A plan view showing another arrangement state of transistors in the circuit,
19 is a cross-sectional view of the circuit shown in FIG. 18, FIG. 20 is a plan view showing the arrangement of transistors in the embodiment circuit of FIG. 1, and FIG. 21 shows the arrangement of transistors in FIG. 20 in more detail. FIG. 22 is a plan view showing an arrangement of transistors in the embodiment circuit of FIG. 9, and FIG. 23 is a plan view showing another arrangement of transistors in the embodiment circuit of FIG. . 11, 12... External power supply connection terminal, 13.14...
MOS transistor, 21...N type substrate, 22.23
...source, drain region, 24...gate electrode,
26... Parasitic PNP transistor, 27... Parasitic resistance, 41... N type substrate, 42... P well region, 4
3.44... Source and drain regions consisting of N+ type regions, 45... Gate electrode, 48... Parasitic NPN transistor, 49... Parasitic resistance, 71.72.73°9
1, 92.93.94...external terminal, 81.83.8
5. 101゜103, 105. 107. 109
．． 111...P channel MOI-transistor, 82
．． 84.86. 102. 104°106, 108
．． 110. 112... N channel MOS transistor, 200... semiconductor chip, 201... external connection terminal, 202... wiring for GND potential, 203...
・Vo. Wiring for electrical potential. Applicant's representative Patent attorney Takehiko Suzue Figure 1 2] Figure 2 GND Vo. Figure 3 Figure 6 Figure 7 bu Figure 13 Figure 5 (J Figure 14 Figure 17

Claims (9)

[Claims] (1) A first node to which a first power supply potential is applied, a second node to which a second power supply potential is applied, a source electrode and a gate electrode are connected to the first node; 1. A semiconductor integrated circuit device comprising: a MOS transistor having a drain electrode connected to a second node. (2) The semiconductor integrated circuit device according to claim 1, wherein the first power supply potential is a high potential, the second power supply potential is a low potential, and the MOS transistor is a P-channel MOS transistor. . (3) The semiconductor integrated circuit device according to claim 1, wherein the first power supply potential is a low potential, the second power supply potential is a high potential, and the MOS transistor is an N-channel MOS transistor. . (4) The semiconductor integrated circuit device according to claim 1, wherein the MOS transistor is arranged adjacent to an external power supply connection terminal. (5) The semiconductor integrated circuit device according to claim 11, wherein the MOS transistor is arranged and formed under an external power supply connection terminal. (6) The semiconductor integrated circuit device according to claim 1, wherein the MOS transistor is arranged and formed in a corner portion of the semiconductor integrated circuit device. (7) a first node to which a high power supply potential is applied;
a second node to which a low power supply potential is applied; a P-channel MOS transistor having a source electrode and a gate electrode connected to the first node and a drain electrode connected to the second node; 1. A semiconductor integrated circuit device comprising: an N-channel MOS transistor having a drain electrode connected to a first node, and a source electrode and a gate electrode connected to the second node. (8) The semiconductor integrated circuit device according to claim 7, wherein the P-channel and N-channel MOS transistors are arranged and formed on different sides. (9) The semiconductor integrated circuit device according to claim 7, wherein each of the P-channel and N-channel MOS transistors is arranged adjacent to an external power supply connection terminal.