TW448604B - Power-on sequence induced latch-up protection device - Google Patents

Abstract

A power-on sequence induced latch-up protection device is used in a power supply system including a first power and a second power, and the voltage of the first power is larger than the voltage of the second power. The device includes: a control unit having an input terminal electrically connected to the first power; and a variable capacitor having a control terminal and two capacitor terminals. One capacitor terminal is electrically connected to the second power, and the other capacitor terminal is electrically connected to the grounding voltage. The control terminal is electrically connected to the output terminal of the control unit. The variable capacitor changes the capacitance based on the input signal of the control terminal, thereby prevention the latch-up effect induced by the power-on sequence and the coupling effect to the other devices. The control unit and the variable capacitor are formed on the same semiconductor substrate.

Description

4 48 6 04 V. Description of the Invention (l) —— [Field of Invention] The present invention relates to a protection device for a blocking effect caused by a power supply sequence, and more particularly to a power supply sequence having the following two advantages?丨 Locking effect protection device: low capacitive coupling effect, can be integrated with other semiconductor components on the semiconductor substrate. [Explanation of related technology] In CMOS (coraplementary M0S) semiconductor devices, the latch-up effect has been plagued many circuit layout designers, because it causes the CMOS device to temporarily or even permanently fail, affecting the reliability of the device. ). And in the application of multiple power design CMOS, the power supply sequence (p0wer-0ri sequence) is also the reason that it may cause two kinds of latch-up effects. The principle of inducing latch-up and the improvement methods of conventional techniques will be described below. '^ Figure 1 is a structural diagram of the N-well of CMOS t and the semiconductor layer thereon * and the substrate 11 is a P-type semiconductor substrate.' Reference symbol 12 represents n (N-well), and reference symbol 13 represents the source of PMOS. Its voltage is connected to the second voltage source VDD2, and the N well 12 is connected to ν through the n + region of the reference symbol 14. In this structure, VDD1 must be greater than, or the source ㈠ and… area ^^. There will be a forward bias of the ρη junction. However, when the above structure is operated, the power supply sequence will cause some problems in the factory. For example, in the normal mode, if VDD2 is supplied first and then ’is supplied first, the voltage in the η + region η is provided.

448 6 04 V. Description of the invention (2) When the voltage of the source electrode 13 is 3, the ρ η junction between the source electrode 13 and the η + region 14 is always maintained at the reverse bias voltage. Therefore, at this time, the operation of the CMOS is in normal operation. However, if VDD2 is supplied first and then VDD1 is supplied, the voltage of source 13 is supplied first. Therefore, when the voltage of n + region 14 is provided, the period between source 13 and n + region 14 will be within a period of time. Forming a forward bias of ρ η, for example, if VDD1 is 3.3 V and VDD2 is 2.5 V, the voltage VDD of η + region 1 4 must take some time, about several microseconds to reach 3. 3 V, as shown in Figure 2. During the period when the VDD1 voltage is lower than the VDD2 voltage by 2.5 V minus the forward bias of the pn junction (in general, about 2, 0 V), that is, the period of t ST 1 in FIG. 2 Here, the ρ η junction between the source electrode 13 and the n + region 14 is a forward biased mode. As described above, during the period of t S T 1, the ρ η junction between the source electrode 13 and the η + region 14 is forward biased, so there will be a forward current flowing through the junction of the PV Ν well. , And this current may trigger the ρ η ρ η gate fluid (thyristor) formed by parasitic transistors ρηρ and ηρη in CMOS, which is called the latch-up effect, which causes the component to fail. Therefore, in order to avoid the above effects, there are two ways in conventional technology: the first is to add a resistor between the VDM voltage and the corresponding pin of the IC to reduce the current flowing into the C M 0 S element, To achieve the purpose of preventing latch-up effects. The second is to add a capacitor between the VDD1 voltage pin and the ground wire. This capacitor will share a part of the charge, so that the current flowing into the component is not enough to trigger the latch-up effect. However, the above-mentioned two types of protective devices for the blocking effect caused by the conventional power supply sequence are implemented on the printed circuit board by adding a resistor or a capacitor element, and are not integrated in the semiconductor element, so they do not meet the requirements.

448604

V. Explanation of the invention (3) Practical application Q Simultaneous T The above two methods also have the other * The disadvantage is that during normal operation > the addition of a resistor or capacitor will cause a coupling phenomenon in the circuit within 1C > and thus make the circuit operation unstable 0 [Summary of the Invention In view of this, the system of a of the present invention provides a protection device caused by a latch-up effect caused by a power supply sequence, wherein the device has the advantages of low capacitance dissipation, can be integrated with other semiconductor components on a semiconductor substrate, etc. The protection device of the lock-in effect caused by the power supply sequence of the invention is used for a power supply system including a first power supply and a second power supply, and the first power supply voltage is greater than the second power supply voltage. The device includes an input end of the control part electrically connected to the power supply. The first power supply; and, --- a variable capacitor Contains-a control terminal and two capacitor terminals-the capacitor terminal is electrically connected to the second power source, the capacitor terminal is electrically connected to a ground voltage, and the control terminal is electrically connected to the output terminal of the control section; the variable capacitor follows the control The input value of the input terminal is used to change the capacitance value to avoid the latch-up effect caused by the power supply sequence and the coupling effect on other components. * The control unit and the variable capacitor are formed on the same semiconductor substrate. Schematic diagram of the N-well in CMOS and the semiconductor structure on it r Figure 2 is a diagram of the relationship between voltage and time when the power is turned on; Figure 3 is a schematic circuit diagram of the protection device of the latch-up effect caused by the power supply sequence of the present invention J

448 6 04 V. Description of the invention (4) Figure 4 is a schematic diagram of the semiconductor structure of the NMOS transistor 33 and the capacitor group 34 shown in Figure 3; and Figure 5 is a protection against the blocking effect caused by the power supply sequence of another embodiment of the present invention Schematic diagram of the device. [Description of symbols] 11 P-type semiconductor base 12 N well 13 PM0S source 14 n + region 31 diode group 32 inverter 321 PM0S transistor 322 NM0S transistor 33 NM0S transistor 34 capacitor group 341 first capacitor 342 Second capacitor 41 P-type semiconductor base 42 η well 43 NM0S transistor 44 Gate dielectric layer 45 Gate electrode

Page 7 448604 V. Description of the invention (5) [Detailed description of the preferred embodiment] The structure of the protection device of the latching effect and the working principle of the power supply sequence of the present invention will be described in detail below with reference to the accompanying drawings. In the following, the first power supply voltage VDD1 is set to 3.3 V, and the second power supply voltage V is set to 2.5 V, which is described by Λ 利. FIG. 3 is a schematic circuit diagram of the protection device of the latch-up effect caused by the power supply sequence according to the present invention, which includes “a diode group 31, including four serially connected diodes”, in which the first one of the diode group 31 The ρ pole of a diode is connected to Vddi, an inverter 32 'is composed of a CMOS, where the source of the pmos transistor 3 2 1 is connected to VDD2', the source of the NM0S transistor 322 is grounded, pMQ§ and NM0S The common node of the two gates, that is, the input terminal of the inverter, is connected to the last diode n of the diode group 31; an NMOS transistor 33, and the gate is connected to the inverter 32 The output terminal 'is a common node of the drains of the PM 0s transistor 321 and the NMOS transistor 322, and the source 33 of the OFF transistor 33 is grounded; and a capacitor group 34' includes a first capacitor 341 and The second capacitor 342, where the capacitance of the first capacitor 341 is much larger than the second capacitor 3 ohms, > the first capacitor 341 is connected to V & D2 at one end, and connected to the first terminal of the second capacitor 342 at the other end, and the second The second terminal of the capacitor 3 4 2 is grounded, and the common node of the first capacitor 341 and the second capacitor 342 is connected to the NMOS transistor 33 Drain. The working principle of the circuit of FIG. 3 will be described below. In general, when 3.3V of VDD1 is started first, the structure of Figure 3 will not work because VDD2 has not been provided yet. After that, when 2.5V of VDD2 is connected, the diode group 31 will provide a voltage drop of 2.0V, so the wheel-in terminal voltage of the inverter 32 is about 1.3V, and the M0S transistor 322 is turned on at this time. 'anti

5. Description of the Invention (6) The output terminal of the phaser 32 is a ground voltage of 0V, so the NM OS transistor 33 is not conductive, and VDD2 is grounded through the first capacitor 341 and the second capacitor 342. From the above, it can be known that the circuit of FIG. 3 does not affect the operation of VDDi and VDD2 under normal circumstances. When the power supply sequence is changed, when 2.5V of VDD2 is turned on first, VDD2 is grounded through the first capacitor 3 4 1 and the second capacitor 3 4 2. Then, when VDD1 is connected, when VDD1 has not reached 2.0V, that is, during the period of t ST 1 in FIG. 2, the voltage of VDDi is not enough to turn on diode group 3 1, and inverter 32 The input of can be regarded as 0V, so the output of inverter 32 will be 2.5V of VUD2. After that, the 2.5V at the output of the inverter 32 will turn on the NMOS transistor 33. Therefore, the path of the second capacitor 34 will be bypassed by the NMOS transistor 33 and will not function. At this time, VDD2 will be grounded through the first capacitor 341 with a large capacitance value, and the first capacitor 341 will share a part of the electric charge, so that the current flowing into the element is not enough to trigger the latch-up effect. When the voltage of VDD1 rises to more than 2.5V, the voltage of VDD1 is turned on to diode group 31 at this time, and the input terminal voltage of inverter 32 exceeds 0.5V. At this time, NMOS transistor 322 will be turned on, so the inverter The output terminal of 32 is a ground voltage, the NMOS transistor 3 3 is turned off (cut-off), and VDD2 is grounded through the first capacitor 341 and the second capacitor 342 connected to each other. From the above description, it can be known that when VDD1 is just started and the voltage is not greater than the VDD2 voltage, VDD2 will be grounded through the first capacitor 3 41 with a large capacitance value. In other words, it can share more charge and make VDD2 flow into The current is small enough to cause a latch-up effect. When VDD1 is activated for a period of time, when VDD1 voltage is greater than VDD2, that is, after time T1, VDD2 is grounded through the first capacitor 341 and the second capacitor 342 connected in series, and the first capacitor 341 and

448604 V. Description of the invention (7) The series capacitance of the second capacitor 342 is much smaller than the first capacitor 341, so the coupling effect of the capacitor on the circuit can effectively reduce β. Figure 4 is the NM0S transistor 33 and the capacitor in Figure 3. The structural diagram of group 34 includes: a P-type semiconductor substrate 41; an n-well 42 formed on the p-type semiconductor substrate 41; an NMOS transistor structure 43 formed on the p-type semiconductor substrate 41 It is connected to the ground voltage 'gate is electrically connected to the output terminal of inverter 3 2' and the drain diffusion layer crosses the ρη junction formed by the p-type semiconductor substrate 41 and the n-well 42; a gate dielectric layer 44, Is formed on the n-well 42; and a gate electrode 45 'is formed on the gate dielectric layer 44 and is electrically connected to the second power source. It can be seen in the structure of FIG. 4 that the gate electrode 45, the gate dielectric layer 44 and the n-well 42 form a gate capacitor, which is the first capacitor 341 in FIG. In addition, a junction between the n-well 42 and the p-type semiconductor substrate 41 will form an empty region 'which can be regarded as another capacitor during the inversion operation, which is the second capacitor 342 in FIG. 3. When the NMOS transistor 43 is activated, a current channel is formed between the drain and the source. At this time, the empty capacitor of the η well 42 and the p-type semiconductor substrate 41 will lose its effect. When the NMOS transistor 43 is turned off, the whole The capacitance will be the empty capacitance formed by the gate capacitor in series with the η-well 42 and the p-type semiconductor substrate 41, but the value of the empty capacitance formed by the η-well 42 and the p-type semiconductor substrate 41 is smaller than the gate capacitance, so, and The coupling effect of other circuits will be effectively reduced. Those skilled in the art will know that the present invention is not limited to the use of NMOS, but can also use PMOS to achieve the same purpose, as shown in the circuit diagram of FIG. 5.

Page 10 448 604 V. Description of the invention (8) In addition, those skilled in the art will also know that the present invention is not limited to using the CMOS structure to implement the inverter 32, and other similar inverter circuit structures can also achieve the purpose of the invention. . In addition, those skilled in the art know that the diode group 31 is not limited to the use of diodes. Other circuit structures that can achieve the purpose of voltage reduction can also achieve the purpose of the present invention. Therefore, the above is only for the convenience of describing a preferred embodiment of the present invention, and the scope of the present invention is not limited to the preferred embodiment. Any change made according to the present invention shall be a patent for the present invention. Range.

Claims (1)

Ί 4 48 6 〇4. Scope of patent application 1, a protection device of the latch-up effect caused by the power supply sequence 'is used for a power supply system including a first power supply and a second power supply' and the first power supply voltage is greater than the The second power voltage, the device includes: a control unit, the wheel-in terminal is electrically connected to the first power source; and a variable capacitor including a control terminal and two capacitor terminals, a capacitor I terminal is electrically connected to the second Power supply, the other capacitor terminal is electrically connected to the ground voltage, and the control terminal is electrically connected to the output terminal of the control section. The variable capacitor | converter changes the capacitance value according to the input signal of the control terminal to avoid power supply. The latching effect and coupling effect on other components caused by i should be caused in sequence. | 丨 Wherein the control unit and the variable capacitor are formed on the same semiconductor substrate "I! j 丨 2, which is caused by the power supply sequence of the first patent application scope. Protection device for blocking effect, wherein: the control unit is an inverter D j Page 12 448 b 6. Scope of patent application and the common node of the second capacitor. 4. The protection device for the latch-up effect caused by the power supply sequence according to item 2 of the scope of the patent application, wherein the structure of the variable capacitor includes: a P-type semiconductor substrate: an n-well formed on the p-type semiconductor substrate An NMOS is formed on the p-type semiconductor substrate, the source is electrically connected to the ground voltage, the gate is electrically connected to the output terminal of the inverter, and the drain diffusion layer spans the p-type semiconductor substrate and the n-well A ρη junction is formed; a gate dielectric layer is formed on the η well, and a gate electrode is formed on the gate dielectric layer and is electrically connected to the second power source. 5. The protection device for the blocking effect caused by the power supply sequence according to item 1 of the scope of the patent application, wherein: the electrical connection between the input of the control unit and the first power supply is through one or more connected diodes Connection, wherein the P pole of the first diode of the one or more diodes connected in series is connected to the first power source, and the n pole of the last diode is connected to the input terminal of the control unit. 6. A protection device for a lock-in effect caused by a power supply sequence is used for a power supply system including a first power supply and a second power supply, and the first power supply voltage is greater than the second power supply voltage, and the device includes: Page 13 448 6 04 VI. Patent application scope A capacitor group includes a first capacitor and a second capacitor. The first terminal of the first capacitor is electrically connected to the second power source, and the second terminal is connected to the second power source. A first terminal of the capacitor, and a second terminal of the second capacitor electrically connected to a ground voltage; and a PMOS transistor, a source electrically connected to the second power source, a gate electrically connected to the first power source, and a drain electrode Connected to a common node of the first capacitor and the second capacitor.