JPS6158853B2 - - Google Patents

Info

Publication number
JPS6158853B2
JPS6158853B2 JP54136052A JP13605279A JPS6158853B2 JP S6158853 B2 JPS6158853 B2 JP S6158853B2 JP 54136052 A JP54136052 A JP 54136052A JP 13605279 A JP13605279 A JP 13605279A JP S6158853 B2 JPS6158853 B2 JP S6158853B2
Authority
JP
Japan
Prior art keywords
gate
register
signal
latch
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP54136052A
Other languages
English (en)
Japanese (ja)
Other versions
JPS5559569A (en
Inventor
Kurea Baagurando Neiru
Aanorudo Ruuitsuku Deebitsudo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of JPS5559569A publication Critical patent/JPS5559569A/ja
Publication of JPS6158853B2 publication Critical patent/JPS6158853B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4234—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
    • G06F13/4243—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus with synchronous protocol

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Executing Machine-Instructions (AREA)
  • Memory System (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
JP13605279A 1978-10-23 1979-10-23 Interface unit Granted JPS5559569A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US05/954,067 US4258417A (en) 1978-10-23 1978-10-23 System for interfacing between main store memory and a central processor

Publications (2)

Publication Number Publication Date
JPS5559569A JPS5559569A (en) 1980-05-06
JPS6158853B2 true JPS6158853B2 (OSRAM) 1986-12-13

Family

ID=25494887

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13605279A Granted JPS5559569A (en) 1978-10-23 1979-10-23 Interface unit

Country Status (4)

Country Link
US (1) US4258417A (OSRAM)
EP (1) EP0010197B1 (OSRAM)
JP (1) JPS5559569A (OSRAM)
DE (1) DE2965798D1 (OSRAM)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02155452A (ja) * 1988-12-05 1990-06-14 Matsushita Electric Ind Co Ltd モータ
JPH02211045A (ja) * 1989-02-08 1990-08-22 Matsushita Electric Ind Co Ltd 光ディスク用スピンドルモータの動圧軸受ユニット
JPH0564528U (ja) * 1992-02-06 1993-08-27 コパル電子株式会社 動圧空気軸受

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4467417A (en) * 1981-09-16 1984-08-21 Honeywell Information Systems Inc. Flexible logic transfer and instruction decoding system
EP0082903B1 (fr) * 1981-12-29 1987-05-13 International Business Machines Corporation Unité de commande pouvant être connectée à deux mémoires de vitesses différentes
US4513371A (en) * 1982-07-29 1985-04-23 Ncr Corporation Computer interface apparatus using split-cycle lookahead addressing for faster access to paged memory
US4831520A (en) * 1987-02-24 1989-05-16 Digital Equipment Corporation Bus interface circuit for digital data processor
JPH02105239A (ja) * 1988-10-13 1990-04-17 Mitsubishi Electric Corp マイクロコンピュータ
US5041962A (en) * 1989-04-14 1991-08-20 Dell Usa Corporation Computer system with means for regulating effective processing rates
US5210858A (en) * 1989-10-17 1993-05-11 Jensen Jan E B Clock division chip for computer system which interfaces a slower cache memory controller to be used with a faster processor
US6041379A (en) * 1996-10-04 2000-03-21 Northrop Grumman Corporation Processor interface for a distributed memory addressing system
US5886658A (en) * 1997-05-15 1999-03-23 Crystal Semiconductor Corporation Serial port interface system and method for an analog-to-digital converter
US6925520B2 (en) * 2001-05-31 2005-08-02 Sun Microsystems, Inc. Self-optimizing crossbar switch

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3398405A (en) * 1965-06-07 1968-08-20 Burroughs Corp Digital computer with memory lock operation
US3611315A (en) * 1968-10-09 1971-10-05 Hitachi Ltd Memory control system for controlling a buffer memory
US3643221A (en) * 1970-04-16 1972-02-15 Ibm Channel buffer for data processing system
US3909791A (en) * 1972-06-28 1975-09-30 Ibm Selectively settable frequency divider
US3795901A (en) * 1972-12-29 1974-03-05 Ibm Data processing memory system with bidirectional data bus
US4014006A (en) * 1973-08-10 1977-03-22 Data General Corporation Data processing system having a unique cpu and memory tuning relationship and data path configuration
US3938097A (en) * 1974-04-01 1976-02-10 Xerox Corporation Memory and buffer arrangement for digital computers
US3967247A (en) * 1974-11-11 1976-06-29 Sperry Rand Corporation Storage interface unit
NL165859C (nl) * 1975-04-25 1981-05-15 Philips Nv Station voor informatie-overdracht.
JPS5263038A (en) * 1975-10-01 1977-05-25 Hitachi Ltd Data processing device
US4075692A (en) * 1976-01-02 1978-02-21 Data General Corporation Data path configuration for a data processing system
US4063081A (en) * 1976-06-08 1977-12-13 Honeywell Computer apparatus
US4091455A (en) * 1976-12-20 1978-05-23 Honeywell Information Systems Inc. Input/output maintenance access apparatus

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02155452A (ja) * 1988-12-05 1990-06-14 Matsushita Electric Ind Co Ltd モータ
JPH02211045A (ja) * 1989-02-08 1990-08-22 Matsushita Electric Ind Co Ltd 光ディスク用スピンドルモータの動圧軸受ユニット
JPH0564528U (ja) * 1992-02-06 1993-08-27 コパル電子株式会社 動圧空気軸受

Also Published As

Publication number Publication date
EP0010197A1 (en) 1980-04-30
JPS5559569A (en) 1980-05-06
EP0010197B1 (en) 1983-06-29
DE2965798D1 (en) 1983-08-04
US4258417A (en) 1981-03-24

Similar Documents

Publication Publication Date Title
US4298927A (en) Computer instruction prefetch circuit
US5640528A (en) Method and apparatus for translating addresses using mask and replacement value registers
US4361868A (en) Device for increasing the length of a logic computer address
US4638423A (en) Emulating computer
JP2539199B2 (ja) デジタルプロセッサ制御装置
JPS59501684A (ja) 目的命令ストリ−ムへ殆んど実時間で插入するためのソ−スおよび目的命令ストリ−ムの外部における加速式命令写像
JPS586173B2 (ja) チャネル制御方式
JPS6158853B2 (OSRAM)
US5029073A (en) Method for fast establishing a co-processor to memory linkage by main processor
US5119484A (en) Selections between alternate control word and current instruction generated control word for alu in respond to alu output and current instruction
JPH0135367B2 (OSRAM)
US5649142A (en) Method and apparatus for translating addresses using mask and replacement value registers and for accessing a service routine in response to a page fault
EP0010196B1 (en) Control circuit and process for digital storage devices
JPH0332818B2 (OSRAM)
KR920007253B1 (ko) 마이크로 프로그램 제어 장치
EP0240606B1 (en) Pipe-line processing system and microprocessor using the system
US5742842A (en) Data processing apparatus for executing a vector operation under control of a master processor
US5404471A (en) Method and apparatus for switching address generation modes in CPU having plural address generation modes
JPH027097B2 (OSRAM)
US5363490A (en) Apparatus for and method of conditionally aborting an instruction within a pipelined architecture
JP2680828B2 (ja) ディジタル装置
US5864690A (en) Apparatus and method for register specific fill-in of register generic micro instructions within an instruction queue
US4262330A (en) I-phase controls for a computer
JPS58115565A (ja) デ−タ処理装置
US4218741A (en) Paging mechanism