JPS6156812B2 - - Google Patents

Info

Publication number
JPS6156812B2
JPS6156812B2 JP57052093A JP5209382A JPS6156812B2 JP S6156812 B2 JPS6156812 B2 JP S6156812B2 JP 57052093 A JP57052093 A JP 57052093A JP 5209382 A JP5209382 A JP 5209382A JP S6156812 B2 JPS6156812 B2 JP S6156812B2
Authority
JP
Japan
Prior art keywords
output
dma
program counter
selector
input condition
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP57052093A
Other languages
English (en)
Japanese (ja)
Other versions
JPS58169248A (ja
Inventor
Yutaka Moryama
Akira Myasaka
Tatsuki Hayashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP57052093A priority Critical patent/JPS58169248A/ja
Publication of JPS58169248A publication Critical patent/JPS58169248A/ja
Publication of JPS6156812B2 publication Critical patent/JPS6156812B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30094—Condition code generation, e.g. Carry, Zero flag

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Executing Machine-Instructions (AREA)
  • Bus Control (AREA)
JP57052093A 1982-03-30 1982-03-30 入力条件セレクタ付プログラムカウンタ制御方式 Granted JPS58169248A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57052093A JPS58169248A (ja) 1982-03-30 1982-03-30 入力条件セレクタ付プログラムカウンタ制御方式

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57052093A JPS58169248A (ja) 1982-03-30 1982-03-30 入力条件セレクタ付プログラムカウンタ制御方式

Publications (2)

Publication Number Publication Date
JPS58169248A JPS58169248A (ja) 1983-10-05
JPS6156812B2 true JPS6156812B2 (cs) 1986-12-04

Family

ID=12905215

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57052093A Granted JPS58169248A (ja) 1982-03-30 1982-03-30 入力条件セレクタ付プログラムカウンタ制御方式

Country Status (1)

Country Link
JP (1) JPS58169248A (cs)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0690700B2 (ja) * 1984-05-31 1994-11-14 富士通株式会社 半導体集積回路
JPS6191752A (ja) * 1984-10-11 1986-05-09 Nec Corp マイクロコンピユ−タ
JPH0789346B2 (ja) * 1985-07-05 1995-09-27 日本電気株式会社 Ｄｍａコントローラ

Also Published As

Publication number Publication date
JPS58169248A (ja) 1983-10-05

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