JPS6153740B2 - - Google Patents

Info

Publication number
JPS6153740B2
JPS6153740B2 JP56143638A JP14363881A JPS6153740B2 JP S6153740 B2 JPS6153740 B2 JP S6153740B2 JP 56143638 A JP56143638 A JP 56143638A JP 14363881 A JP14363881 A JP 14363881A JP S6153740 B2 JPS6153740 B2 JP S6153740B2
Authority
JP
Japan
Prior art keywords
terminal
logic circuit
signal current
output
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP56143638A
Other languages
English (en)
Japanese (ja)
Other versions
JPS5846437A (ja
Inventor
Koji Takaragawa
Junsaku Nitsuta
Akira Ishida
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP56143638A priority Critical patent/JPS5846437A/ja
Publication of JPS5846437A publication Critical patent/JPS5846437A/ja
Publication of JPS6153740B2 publication Critical patent/JPS6153740B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/381—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using cryogenic components, e.g. Josephson gates

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Computing Systems (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Superconductor Devices And Manufacturing Methods Thereof (AREA)
  • Logic Circuits (AREA)
JP56143638A 1981-09-11 1981-09-11 超伝導論理回路 Granted JPS5846437A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56143638A JPS5846437A (ja) 1981-09-11 1981-09-11 超伝導論理回路

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56143638A JPS5846437A (ja) 1981-09-11 1981-09-11 超伝導論理回路

Publications (2)

Publication Number Publication Date
JPS5846437A JPS5846437A (ja) 1983-03-17
JPS6153740B2 true JPS6153740B2 (cs) 1986-11-19

Family

ID=15343417

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56143638A Granted JPS5846437A (ja) 1981-09-11 1981-09-11 超伝導論理回路

Country Status (1)

Country Link
JP (1) JPS5846437A (cs)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4825771B2 (ja) * 2007-10-22 2011-11-30 信越ポリマー株式会社 ウェーハ収納容器およびウェーハのハンドリング方法

Also Published As

Publication number Publication date
JPS5846437A (ja) 1983-03-17

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