JPS6153740B2 - - Google Patents
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- Publication number
- JPS6153740B2 JPS6153740B2 JP56143638A JP14363881A JPS6153740B2 JP S6153740 B2 JPS6153740 B2 JP S6153740B2 JP 56143638 A JP56143638 A JP 56143638A JP 14363881 A JP14363881 A JP 14363881A JP S6153740 B2 JPS6153740 B2 JP S6153740B2
- Authority
- JP
- Japan
- Prior art keywords
- terminal
- logic circuit
- signal current
- output
- input
- Prior art date
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- Expired
Links
- 238000010586 diagram Methods 0.000 description 4
- 230000009897 systematic effect Effects 0.000 description 3
- 230000003111 delayed effect Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 1
- 230000001747 exhibiting effect Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/381—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using cryogenic components, e.g. Josephson gates
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Computational Mathematics (AREA)
- Computing Systems (AREA)
- Mathematical Analysis (AREA)
- Mathematical Optimization (AREA)
- Pure & Applied Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- Superconductor Devices And Manufacturing Methods Thereof (AREA)
- Logic Circuits (AREA)
Description
【発明の詳細な説明】
本発明は、２つの論理信号入力をＡ及びＢ、桁
上げ信号をＣoとするとき、ＡとＢとの排他的論
理和出力（ＡＢ）とＣoとの排他的論理和出力
（ＡＢ）Ｃoが加算出力信号Ｘとして得られ、
且つＡとＢとの論理積出力Ａ・Ｂと（ＡＢ）・
Ｃoとの論理出力（Ａ・Ｂ）＋（ＡＢ）・Ｃoが桁
上げ信号出力Ｃo+1として得られる超電導論理回
路に関する。Detailed Description of the Invention The present invention provides an exclusive OR output (AB) of A and B and an exclusive OR of C o when two logic signal inputs are A and B and a carry signal is C o . The logical sum output (AB) C o is obtained as the addition output signal X,
And the logical product output of A and B, A・B and (AB)・
The present invention relates to a superconducting logic circuit in which a logic output ( A.B )+(AB) .C.sub.o with C.sub.o is obtained as a carry signal output C.sub.o +1 .
従来、このような機能を呈する超伝導論理回路
が種々提案されているが、高速動作が得られなか
つたり、大なる電力を消費したり、安定な動作が
得られなかつたり、全体が大型、複雑であつたり
し、何れも満足し得るものではなかつた。 Various superconducting logic circuits have been proposed that exhibit such functions, but they do not operate at high speed, consume a large amount of power, do not operate stably, or are large and complex as a whole. All of them were unsatisfactory.
よつて、本発明は、そのような欠点のない新規
な、上述した機能を呈する超伝導論理回路を提案
せんとするもので、以下、詳述するところから明
らかとなるであろう。 Therefore, the present invention aims to propose a novel superconducting logic circuit free from such drawbacks and exhibiting the above-mentioned functions, which will become clear from the detailed description below.
第１図は、本発明による超伝導論理回路の一例
を、全体として符号Ｑで示し、それぞれ第１、第
２、第３及び第４の端子ａ１，ａ２，ａ３及びａ
４を有する第１、第２、第３及び第４の論理回路
Ｕ１，Ｕ２，Ｕ３及びＵ４を有する。 FIG. 1 shows an example of a superconducting logic circuit according to the invention, generally designated Q, with first, second, third and fourth terminals a1, a2, a3 and a
4, first, second, third and fourth logic circuits U1, U2, U3 and U4.
この場合、論理回路Ｕ１及びＵ３は、(a)端子ａ
１及びａ２の双方に信号電流が２値表示で「１」
（正論理）で入力されたとき、端子ａ３に信号電
流を２値表示で「１」で出力し、端子ａ４に信号
電流を２値表示で「０」で出力し、(b)端子ａ１及
びａ２の何れかを一方に信号電流が２値表示で
「１」で入力され、他方に信号電流が２値表示で
「０」で入力されたとき、端子ａ３に信号電流を
２値表示で「０」で出力し、端子ａ４に信号を２
値表示で「１」で出力し、(c)端子ａ１がａ２の双
方に信号電流が２値表示で「０」で入力されたと
き、第３及び第４の端子の双方に信号電流を
「０」で出力する機構を有する。 In this case, logic circuits U1 and U3 are connected to (a) terminal a
The signal current for both 1 and a2 is "1" in binary display.
(positive logic), the signal current is output as "1" in binary display to terminal a3, the signal current is output as "0" in binary display to terminal a4, and (b) terminal a1 and When a signal current is input as "1" in binary display to either a2 and a signal current as "0" in binary display is input to the other terminal, the signal current is input as "0" in binary display to terminal a3. 0" and send a signal to terminal a4 as 2.
(c) When the signal current is input to both terminals a1 and a2 as "0" in the binary display, the signal current is output to both the third and fourth terminals as "1". It has a mechanism to output "0".
論理回路Ｕ１及びＵ３のこのような構成の実施
例は、第２図Ａ及び第２図Ｂに示す構成を有す
る。 An example of such a configuration of logic circuits U1 and U3 has the configuration shown in FIGS. 2A and 2B.
第２Ａ図及び第２Ｂ図に示す構成は、特願昭56
―17682号に第１図及び第４図を伴なつて詳細に
説明されているので、簡単のため、その詳細説明
は、特願昭56―17682号に所載のものを援用す
る。なお、第２図Ａ及び第２図Ｂにおいて、Ｒ
１，Ｒ２，ＲBP、RSは抵抗、Ｊ１及びＪ２はジ
ヨセフソン接合を示す。 The structure shown in Fig. 2A and Fig. 2B is
Since it is explained in detail in Japanese Patent Application No. 17682 with figures 1 and 4, for the sake of brevity, the detailed explanation given in Japanese Patent Application No. 17682 will be referred to. In addition, in FIG. 2A and FIG. 2B, R
1, R2, R BP , RS are resistances, and J1 and J2 are Josephson junctions.
また、第２及び第４の論理回路Ｕ２及びＵ４
は、(a)端子ａ１及びａ２の双方に信号電流が２値
表示で「１」で入力されたとき、端子ａ３に信号
電流を２値表示で「１」で出力し、(b)端子ａ１に
信号電流が２値表示で「１」で入力され、端子ａ
２に信号電流が「０」で入力されたとき、端子ａ
３に信号電流を２値表示で「０」で出力する構成
を有する。 Moreover, the second and fourth logic circuits U2 and U4
(a) When the signal current is input as "1" in binary display to both terminals a1 and a2, the signal current is output as "1" in binary display to terminal a3, (b) The signal current is input as "1" in binary display, and the terminal a
When the signal current is input to 2 as “0”, the terminal a
3, the signal current is output as "0" in binary display.
論理回路Ｕ２及びＵ４のこのような構成の実施
例は、第３図Ａ〜第３図Ｄに示す構成を有する。
第３図Ａ〜第３図Ｃに示す構成は、特願昭56―
17678号に第１図、第２図及び第４図を伴なつて
詳細に説明されているので、簡単のため、その詳
細説明は特願昭56―17678号に所載のものを援用
する。また、このような構成の他の実施例は、第
３図Ｄに示す構成を有する。第３図Ｄに示す構成
は、特願昭55―78082号に第４図を伴なつて詳細
に説明されているので、簡単のため、その詳細説
明は特願昭55―78082号に所載のものを援用す
る。なお、第３図Ａ〜第３図Ｄにおいて、Ｒ１〜
Ｒ４は抵抗、Ｊ１〜Ｊ３はジヨセフソン接合、Ｌ
はインダクタをそれぞれ示す。 An example of such a configuration of logic circuits U2 and U4 has the configuration shown in FIGS. 3A to 3D.
The configurations shown in Figures 3A to 3C are
Since it is explained in detail in Japanese Patent Application No. 17678 with figures 1, 2, and 4, for the sake of brevity, the detailed explanation given in Japanese Patent Application No. 17678 will be used. Another embodiment of such a configuration has the configuration shown in FIG. 3D. The configuration shown in Figure 3D is explained in detail in Japanese Patent Application No. 55-78082 with Figure 4, so for the sake of simplicity, the detailed explanation is included in Japanese Patent Application No. 55-78082. Please refer to the following. In addition, in FIGS. 3A to 3D, R1 to
R4 is a resistor, J1 to J3 are Josephson junctions, L
indicate inductors, respectively.
しかして、論理回路Ｕ１は、その端子ａ１及び
ａ２がそれぞれ被加算信号Ａ及びＢの供給される
入力端子１１に、端子ａ３が負荷抵抗１８を介し
て桁上げ信号出力端子１６に、端子ａ４が論理回
路Ｕ２の端子ａ２に接続されている。 Thus, the logic circuit U1 has its terminals a1 and a2 connected to the input terminal 11 to which the augend signals A and B are respectively supplied, its terminal a3 connected to the carry signal output terminal 16 via the load resistor 18, and its terminal a4 connected to the carry signal output terminal 16. It is connected to terminal a2 of logic circuit U2.
また、論理回路Ｕ２は、その端子ａ１が、端子
１１及び１２に供給される信号Ａ及びＢが供給さ
れる時点から所定の時間だけ遅延している時点か
らタイミングバイアス信号Ｔ１の供給される入力
端子１３に、端子ａ３が負荷抵抗１９を介して論
理回路Ｕ３の端子ａ１に、端子ａ４が接地に接続
されている。 In addition, the logic circuit U2 is an input terminal to which the timing bias signal T1 is supplied from a time when the terminal a1 thereof is delayed by a predetermined time from the time when the signals A and B supplied to the terminals 11 and 12 are supplied. 13, terminal a3 is connected to terminal a1 of logic circuit U3 via load resistor 19, and terminal a4 is connected to ground.
さらに、論理回路Ｕ３は、その端子ａ２が桁上
げ信号Ｃoの供給される入力端子１５に、端子ａ
３が負荷抵抗２０を介して桁上げ信号出力端子１
６に、端子ａ４が論理回路Ｕ４の端子ａ２に接続
されている。 Further, the logic circuit U3 has its terminal a2 connected to the input terminal 15 to which the carry signal Co is supplied.
3 is the carry signal output terminal 1 via the load resistor 20
6, terminal a4 is connected to terminal a2 of logic circuit U4.
また、論理回路Ｕ４は、その端子ａ１が上述し
たタイミングバイアス信号Ｔ１が端子１３に供給
される時点から所定の時間だけ遅延せる時点から
タイミングバイアス信号Ｔ２の供給される入力端
子１４に、端子ａ３が負荷抵抗２１を介して加算
出力端子１７に、端子ａ４が接地に接続されてい
る。 In addition, the logic circuit U4 has a terminal a3 connected to the input terminal 14 to which the timing bias signal T2 is supplied from a point in time when the terminal a1 is delayed by a predetermined time from the point in time when the above-mentioned timing bias signal T1 is supplied to the terminal 13. A terminal a4 is connected to ground through a load resistor 21 to the addition output terminal 17.
以上が、本発明による超伝導論理回路の一例構
成である。 The above is an example of the configuration of a superconducting logic circuit according to the present invention.
このような構成によれば、論理回路Ｕ１〜Ｕ４
が、上述した構成を有するので、詳細説明は省略
するが、論理回路Ｕ１の端子ａ３及びａ４に、そ
れぞれＡ・Ｂ及び（ＡＢ）の論理出力が得ら
れ、また、論理回路Ｕ２の端子ａ３に（ＡＢ）
の出力が得られ、さらに、論理回路Ｕ３の端子ａ
３に、（ＡＢ）・Ｃoの出力が得られ、論理回路
Ｕ３の端子ａ４に、（ＡＢ）Ｃoの出力が得ら
れる。 According to such a configuration, the logic circuits U1 to U4
has the above-mentioned configuration, so a detailed explanation will be omitted, but the logic outputs A, B and (AB) are obtained at the terminals a3 and a4 of the logic circuit U1, respectively, and the logic outputs of A, B and (AB) are obtained at the terminal a3 of the logic circuit U2, respectively. (AB)
is obtained, and furthermore, the terminal a of the logic circuit U3
3, the output of (AB)·C o is obtained, and the output of (AB)C o is obtained at the terminal a4 of the logic circuit U3.
よつて、出力端子１６に、Ａ・Ｂ＋（ＡＢ）・
Ｃoで表される桁上げ信号Ｃo+1が得られ、また、
出力端子１７に、（ＡＢ）Ｃoで表される加算
出力Ｘが得られる。 Therefore, A・B+(AB)・
A carry signal C o+1 , denoted by C o , is obtained, and
An addition output X represented by (AB)C o is obtained at the output terminal 17 .
上述したように、第１図に示す本発明による超
伝導論理回路によれば、所期の出力を得ることが
でき、そして、冒頭で前述した欠点を有しない。 As mentioned above, the superconducting logic circuit according to the invention shown in FIG. 1 makes it possible to obtain the desired output and does not have the drawbacks mentioned at the beginning.
なお、上述においては、本発明の一例を示した
に留まり、第４図に示すように、第１図で上述し
た構成において、その論理回路Ｕ２の端子ａ３を
論理回路Ｕ３の端子ａ１に、論理回路Ｕ３の端子
ａ２を桁上げ信号入力端子１５に接続するのに代
え、論理回路Ｕ２の端子ａ３を論理回路Ｕ３の端
子ａ２に、論理回路Ｕ３の端子ａ１を桁上げ信号
入力端子１５に接続したことを除いて、第１図の
場合と同様の構成とすることもでき、そして、こ
のような構成にしても、第１図の場合と同様の作
用効果が得られることは明らかであろう。 Note that the above description merely shows an example of the present invention; as shown in FIG. 4, in the configuration described above in FIG. 1, the terminal a3 of the logic circuit U2 is connected to the terminal a1 of the logic circuit U3; Instead of connecting terminal a2 of circuit U3 to carry signal input terminal 15, terminal a3 of logic circuit U2 was connected to terminal a2 of logic circuit U3, and terminal a1 of logic circuit U3 was connected to carry signal input terminal 15. Except for this, it is also possible to adopt a configuration similar to that in the case of FIG. 1, and it is clear that even with such a configuration, the same effects as in the case of FIG. 1 can be obtained.
また、第５図に示すように、第１図及び第４図
で上述した構成の超伝導論理回路の複数Ｑ１，Ｑ
２………を継続接続して、複数ビツトの超伝導論
理回路を構成することもできることは明らかであ
ろう。 Further, as shown in FIG. 5, a plurality of superconducting logic circuits Q1, Q
It is clear that a multi-bit superconducting logic circuit can also be constructed by continuously connecting . . . 2.
第１図は、本発明による超伝導論理回路の一例
を示す系統的接続図である。第２図及び第３図
は、第１図に示す超伝導論理回路に用いる論理回
路の実施例を示す接続図である。第４図は、本発
明による超伝導論理回路の他の例を示す系統的接
続図である。第５図は、本発明による超伝導論理
回路の応用例を示す系統的接続図である。
Ｑ，Ｑ１〜Ｑ４…超伝導論理回路、１１，１２
…被加算信号入力端子、１３，１４…タイミング
バイアス信号入力端子、１５…桁上げ信号入力端
子、１６…桁上げ信号出力端子、１７…加算出力
信号端子、Ｕ１，Ｕ２，Ｕ３，Ｕ４…論理回路、
ａ１，ａ２，ａ３，ａ４…論理回路Ｕ１〜Ｕ４の
端子。
FIG. 1 is a systematic connection diagram showing an example of a superconducting logic circuit according to the present invention. FIGS. 2 and 3 are connection diagrams showing embodiments of logic circuits used in the superconducting logic circuit shown in FIG. 1. FIG. 4 is a systematic connection diagram showing another example of a superconducting logic circuit according to the present invention. FIG. 5 is a systematic connection diagram showing an application example of the superconducting logic circuit according to the present invention. Q, Q1-Q4...Superconducting logic circuit, 11, 12
...Augend signal input terminal, 13, 14...Timing bias signal input terminal, 15...Carry signal input terminal, 16...Carry signal output terminal, 17...Addition output signal terminal, U1, U2, U3, U4...Logic circuit ,
a1, a2, a3, a4...Terminals of logic circuits U1 to U4.
Claims (1)
有する第１、第２、第３及び第４の論理回路を有
し、 第１及び第３の論理回路は、(a)その第１及び第
２の端子の双方に信号電流が２値表示で「１」で
入力されたとき、第３の端子に信号電流を２値表
示で「１」で出力し、第４の端子に信号電流を２
値表示で「０」で出力し、(b)第１及び第２の端子
の何れか一方に信号電流が２値表示で「１」で入
力され、他方に信号電流が２値表示で「０」で入
力されたとき、第３の端子に信号電流を２値表示
で「０」で出力し、第４の端子に信号電流を２値
表示で「１」で出力し、(c)第１及び第２の端子の
双方に信号電流が２値表示で「０」で入力された
とき、第３及び第４の端子の双方に信号電流を２
値表示で「０」で出力する構成を有し、 上記第２及び第４の論理回路は、(a)その第１及
び第２の端子の双方に、信号電流が２値表示で
「１」で入力されたとき、第３の端子に信号電流
を２値表示で「１」で出力し、(b)第１の端子に信
号電流が２値表示で「１」で入力され、第２の端
子に信号電流が２値表示に「０」で入力されたと
き、第３の端子に信号電流を２値表示で「０」で
出力する構成を有し、 上記第１の論理回路は、その第１及び第２の端
子がそれぞれ第１及び第２の被加算信号入力端子
に、第３の端子が第１の負荷抵抗を介して桁上げ
信号出力端子に、第４の端子が上記第２の論理回
路の第２の端子に接続され、 上記第２の論理回路は、その第１の端子が第１
のタイミングバイアス入力端子に、第３の端子が
第２の負荷抵抗を介して上記第３の論理回路の第
１または第２の端子に、第４の端子が接地に接続
され、 上記第３の論理回路は、上記第２の論理回路の
第３の端子が上記第２の負荷抵抗を介して当該第
３の論理回路の第１の端子に接続されているか第
２の端子に接続されているかに応じて、第２の端
子または第１の端子が桁上げ信号入力端子に、第
３の端子が第３の負荷抵抗を介して桁上げ信号出
力端子に、第４の端子が上記第４の論理回路の第
２の端子に接続され、 上記第４の論理回路は、その第１の端子が第２
のタイミングバイアス入力端子に、第３の端子が
第４の負荷抵抗を介して加算出力信号端子に、第
４の端子が接地に接続されていることを特徴とす
る超伝導論理回路。[Scope of Claims] 1. First, second, third and fourth logic circuits having first, second, third and fourth terminals, respectively, the first and third logic circuits having first, second, third and fourth terminals, respectively; , (a) when a signal current is input as "1" in binary representation to both the first and second terminals, outputs a signal current as "1" in binary representation to the third terminal; 2 signal current to the 4th terminal
(b) The signal current is input to either the first or second terminal as "1" in binary display, and the signal current is input as "0" in binary display to the other terminal. ”, the signal current is output as “0” in binary display to the third terminal, the signal current is output as “1” in binary display to the fourth terminal, and (c) the signal current is output as “1” in binary display. When the signal current is input to both the third and fourth terminals as “0” in binary display, the signal current is input to both the third and fourth terminals as “0”.
The second and fourth logic circuits have a configuration that outputs "0" in the value display, and (a) the signal current is output as "1" in the binary display at both the first and second terminals thereof. (b) When the signal current is input to the first terminal as "1" in binary display, the signal current is output as "1" in binary display, and The first logic circuit is configured to output a signal current as "0" in binary display to the third terminal when the signal current is input as "0" in binary display to the terminal. The first and second terminals are respectively connected to the first and second augend signal input terminals, the third terminal is connected to the carry signal output terminal via the first load resistor, and the fourth terminal is connected to the second is connected to a second terminal of the logic circuit, and the second logic circuit has its first terminal connected to the first terminal.
A third terminal is connected to the first or second terminal of the third logic circuit via a second load resistor, and a fourth terminal is connected to the ground. In the logic circuit, whether the third terminal of the second logic circuit is connected to the first terminal or the second terminal of the third logic circuit via the second load resistor. The second terminal or the first terminal becomes the carry signal input terminal, the third terminal becomes the carry signal output terminal via the third load resistor, and the fourth terminal The fourth logic circuit is connected to a second terminal of the logic circuit, and the fourth logic circuit has a first terminal connected to a second terminal of the fourth logic circuit.
A superconducting logic circuit characterized in that a third terminal is connected to a timing bias input terminal of the circuit, a third terminal is connected to an addition output signal terminal via a fourth load resistor, and a fourth terminal is connected to ground.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56143638A JPS5846437A (en) | 1981-09-11 | 1981-09-11 | Superconductive logical circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56143638A JPS5846437A (en) | 1981-09-11 | 1981-09-11 | Superconductive logical circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5846437A JPS5846437A (en) | 1983-03-17 |
| JPS6153740B2 true JPS6153740B2 (en) | 1986-11-19 |
Family
ID=15343417
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56143638A Granted JPS5846437A (en) | 1981-09-11 | 1981-09-11 | Superconductive logical circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5846437A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4825771B2 (en) * | 2007-10-22 | 2011-11-30 | 信越ポリマー株式会社 | Wafer storage container and wafer handling method |
-
1981
- 1981-09-11 JP JP56143638A patent/JPS5846437A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5846437A (en) | 1983-03-17 |
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