JPH0359608B2 - - Google Patents

Description

[Detailed Description of the Invention] (1) Technical Field of the Invention The present invention relates to a selection circuit using a superconducting element such as a Josephson element, and particularly to a logic circuit configured with a superconducting element with a bias in the direction opposite to the true output signal. The present invention relates to a superconducting selection circuit that outputs an inverted output by passing a current.

(2) Background of the Technology In general, selection circuits that present signals to individual output terminals for each code in response to coded inputs, such as address selection in a computer storage device, use true values and inverted values as inputs. Even in a selection circuit using a superconducting element, an inverter circuit is required to configure an inverted output from the true output of the code generation circuit in the preceding stage of a circuit constituting a logic circuit such as an AND circuit. However, constructing an inverter circuit using superconducting elements such as Josephson elements requires an extremely complicated circuit, and has the disadvantage that a simple inverter circuit cannot be constructed.

(3) Prior art _and problems Figure ₁ shows a conventional dendritic selection circuit (tree decoder). The branched third and fourth and fifth and sixth superconducting elements J ₃ , J ₄ and J ₅ , J ₆ are connected, respectively, and the output terminals 1,
A system in which a predetermined output is selected from 2, 3, and 4 has been proposed. A control line 5 is provided in the first to sixth superconducting elements J ₁ to J ₆ , and a code generating circuit (not shown) provides a true output and an inverted output to the control line, for example, A ₁ , ₁ , A ₂ , ₂ , A ₃ , ₃ are selected to be added, a bias current I is applied to the superconducting elements J ₁ to J ₆ , and the code signal is applied to the first and fifth superconducting elements J ₁ and J ₅ . A ₁ = 1, A ₃ on control line 5
By adding =1, the first and fifth superconducting elements J ₁ ,
J ₅ is cut off, and current i is passed only through branch B ₁ , which includes the second and sixth superconducting elements J ₂ and J ₆ .
Superconducting element J ₁ containing A ₁ , ₁ , A ₂ , ₂ , A ₃ , ₃
It becomes possible to select only signal end 4 from among J6 to _J6 .

In addition to such a dendritic selection circuit, a loop selection circuit (loop decoder) as shown in FIG. 2 is also used as a conventional superconducting selection circuit.

The above loop selection circuit has a first branch in which a plurality of third and fourth superconducting elements are connected in series to both ends of each of the first and second superconducting elements J ₁ and J ₂ .
B ₁ is connected to a second branch B ₂ in which the fifth and sixth superconducting elements are connected in series, and the control line 5 is associated with the first to sixth superconducting elements J ₁ to J ₆ . The control line connects, for example, the first and second superconducting elements J ₁ and J ₂
The third and sixth superconducting elements are connected so that the true and inverted outputs A ₁ , ₁ are applied from the sign generating circuit to
True output by connecting control line 5 to J ₃ and J ₄ in a loop
Allow A ₂ to be added. The control line 5 is connected to the fourth and fifth superconducting elements J ₄ and J ₅ in the same loop so that the inverted output ₂ can be applied from the code generation circuit.

Furthermore, output lines 1, 2, 3, and 4 are taken out from each of the third to sixth superconducting elements _J3 to _J6 . According to the above configuration, since the inductance of the branch B ₃ including the first and second superconducting elements J ₁ and J ₂ is smaller than that of the first and second branches B ₁ and B ₂ , the bias current I _B flows mostly through the third branch _B3 . Now, if code signals A ₁ = 1, A ₂ = 1 are applied to the control line 5 from the code circuit, output terminal 1 will receive signals A ₁ and A _2. If ₁ = ₂ = 1, output terminal 2 will receive signals of ₁ and A 2. ₂ is similarly connected to output end 3.
A ₁ · ₂ and ₁ ·A ₂ are obtained at the output end 4.

Such a superconducting selection circuit requires true outputs A ₁ , A ₂ , A _{3 .} . . and inverted outputs A ₁ , ₂ , _{3 .} . . from the code generation circuit on the control line. However, Josephson elements and the like have the disadvantage that an extremely complicated inverter circuit is required to obtain the inverted outputs ₁ , ₂ , _3, . . . from the true outputs A ₁ , _{A 2} , _{A 3} . In order to eliminate this drawback, a superconducting element decoder circuit that does not use an inverted output for the code signal applied to the control line may be used, as shown in Japanese Patent Laid-Open No. 56-29740.

To briefly explain the configuration of _this circuit, as shown in _{FIG .} By selecting the signal current so that the signal current is in the forward direction for the conductive element J ₁ and in the reverse direction for the second superconducting element J ₂ , the first superconducting element J ₁ is set to "0" and the second superconducting element J 2 is set to "0". Conductive element J ₂ is for taking out the “1” signal and has output terminal 1.
is "0", but the inverted output of "1" can be taken out from the output terminal 2.

The superconducting elements J ₁ and J ₂ as described above have Josephson junctions J that are relatively long in the direction in which the bias current I _B flows as shown in FIG. ₁ is used, which switches to a voltage state only when it flows in the same direction as the bias current _IB .

However, the superconducting element having this configuration has the disadvantage that the configuration is extremely complicated in order to pattern the upper layer of the Josephson junction J in the forward and reverse directions using only the control line 5.

(4) Purpose of the Invention In view of the above-mentioned conventional drawbacks, the present invention provides a superconducting selection circuit in which a bias line for passing a bias current in the opposite direction to the current flowing through the control line 5 is separately provided and coupled to a superconducting element that is not inverted. The purpose is to provide

(5) Structure of the Invention According to the present invention, this object is to control the plurality of superconductors of the selection means formed by arranging branches in which a plurality of superconducting elements are connected in series on an output line in multiple stages to constitute a logic circuit. A superconducting selection circuit characterized in that only a true output signal is applied to a conductive element from a code generation circuit, and a bias line for flowing a bias current in the opposite direction to the true output signal is coupled to the plurality of superconducting elements to be inverted. This is achieved by providing.

(6) Embodiment of the invention An embodiment of the invention will be described below with reference to the drawings.

FIG. 5 shows an embodiment of the superconducting selection circuit of the present invention, in which a superconducting element consisting of a plurality of series-connected first and second Josephson elements, etc.
J ₁ , J ₂ , third and fourth superconducting elements J ₃ , J ₄ also connected in series, similar fifth and sixth and seventh and eighth superconducting elements J ₅ , J ₆ , J ₇ and _J8 are arranged in parallel in multiple stages, and the output terminals 1 to 4 of each are grounded, and the input signals of X ₀ to _{X 3} are applied to the input terminal, and resistors R ₁ and R ₂ are connected between the input terminal and the ground. , R ₃ and R ₄ , and the control line 5a is connected to the first, third, fifth and seventh superconducting elements.
J ₁ , J ₃ , J ₅ , J ₇ , and the control line 5b is also connected to the second, fourth, sixth and eighth superconducting elements J ₂ , J ₄ ,
J ₆ and J ₈ , and the true outputs A ₀ and A ₁ from the code generation circuit 7 can be applied to the control lines 5a and 5b.

Furthermore, in the present invention, the bias lines 6a and 6b are coupled to the superconducting elements J ₁ to J ₈ from which it is desired to obtain an inverted output, and the bias lines 6a and 6b are not coupled to the superconducting elements from which it is desired to obtain a true output. pattern.

A constant bias current is supplied to the bias line from a bias supply source 8 so that a bias current I _B flows in the direction opposite to that of the control line.

In the _embodiment shown _in FIG. ₅ , bias lines _6a , 6
This is the case when b is connected, and this state is "1"
and bias wires 6a and 6b are superconducting elements J ₄ ,
The uncombined states such as J ₅ , J ₇ , and J ₈ are set to “0”.
The operation of the above configuration will be described by using the symbols ``1'' to indicate that current flows through the control lines 5a and 5b, and ``0'' to indicate that no current flows.

In FIG. 5, the true output A ₀ of the code generation circuit 7
=1, A ₁ =0, and the input signal at the input terminal is X ₀ =X ₁ =
As the current of X ₂ =X ₃ =1 flows, the bias line 6
A bias current I _B , which is opposite to the current flowing through the control lines 5a and 5b, flows through a and 6b, and if this bias current has the same level as the current flowing through the control lines 5a and 5b, then the control line and the bias line are coupled together. Only the superconducting element connected to the control line will be in the "0" state, and the one connected only to the control line will be in the "1" state.

Therefore, in the example shown in FIG.
is X ₀ , A ₀ , A ₁ , and output terminal 2 is X ₁ , A ₀ , _1.
However, output terminal 3 has X ₂・₀・A ₁ , and output terminal 4 has
Of the logical products configured so that X ₃・₀・₁ is selected, the true output of control line 5 A ₀ = 1, A ₁ = 0
, the third one has a combination of “1” and “0”.
and the fourth superconducting element J ₃ are selected. Similarly, when A ₀ = 1 and A ₁ = 1, only the first and second superconducting elements J ₁ and J ₂ are selected, and when A ₀ = 0 and A ₁ = 1, J ₅ and J ₆ are selected, but A ₀ =0 and A ₁ =0, J ₇ and J ₈ are selected.

In other words, the true outputs A ₀ and A ₁ are “1” or “0”.
When selected, only one of the branches B ₁ to B ₄ with the selected combination is selected and current flows through the output line, and in the other branches, one other superconducting element becomes a voltage state, so that the input The signal is connected to the resistor R ₁ ~
It is grounded through _R4, and only a small current flows through the output terminals 1 to 4.

FIG. 6 shows an application example of the superconducting element selection circuit of the present invention as a multiplexer, and 9 has the same configuration as the one surrounded by the dotted line in FIG. Because of the configuration, the output will have X ₀・
A ₀・A ₁ +X ₁・A ₀・₁ +X ₂・₀・A ₁ +X ₃・
_0.1 will be output _.

As another configuration for obtaining the above-mentioned logical sum, in order to obtain a higher margin, control lines may be provided at the output terminals 1 to 4, and the logical sum may be formed using superconducting elements.

Figure 7 shows input signals X ₀ , X ₁ , X ₂ , and X ₃ all set to 1.
This constitutes a decoder circuit, and after applying the true outputs A ₀ and A ₁ to the control line to the superconducting element, the true outputs A ₀ and A ₁ can be obtained by applying a bias current in the reverse direction to the bias line. "1", "0" specified by
A ₀・A 1 , A _0・1 , A 0・A 1 , A ₀・₁ ,
One of _{0.A 1} and _0.1 will be selected _.

Furthermore, it is clear that more diverse selection functions can be added by changing the way the bias lines cross or adding other types of signal current to the bias current.

(7) Effects of the Invention As explained above in detail, the selection circuit for superconducting elements of the present invention has a selection circuit in which a logic circuit includes an inverter circuit for producing an inverted output from the true output of a code generation circuit. Since this can be done simultaneously within the means, the circuit becomes simple and has the effect of providing a selection circuit with a variety of functions.

[Brief explanation of drawings]

Figure 1 is a connection diagram of a conventional superconducting selection circuit, Figure 2
The figure is a connection diagram of another conventional superconducting selection circuit, Figure 3 is a connection diagram of a part of another conventional superconducting selection circuit, and Figure 4 is a diagram of the superconducting element used in Figure 3. 5 is a schematic cross-sectional view for explaining the configuration, FIG. 5 is a connection diagram of the superconducting selection circuit of the present invention, FIG. 6 is a systematic connection diagram when the superconducting selection circuit of the present invention is used as a multiplexer, and FIG. FIG. 7 is a systematic connection diagram when the superconducting selection circuit of the present invention is used as a decoder. 1, 2, 3, 4... Output end, 5, 5a, 5b...
...Control line, 6a, 6b...Bias line, 7...Sign generation circuit, 8...Bias supply source, 9...Selection circuit, _J1 to _J8 ...Superconducting element, _A0 to _A3 ... True output, ₀ to ₃ ...Inverted output, I _B ...Bias current.

Claims (1)

[Scope of Claims] 1. A true output signal is sent from a code generation circuit to the plurality of superconducting elements of the selection means, which constitutes a logic circuit by arranging branches in which a plurality of superconducting elements are connected in series on an output line in multiple stages. A superconducting selection circuit characterized in that the plurality of superconducting elements to be inverted are connected to a bias line that flows a bias current in a direction opposite to that of a true output signal. 2. The superconducting selection circuit according to claim 1, wherein the output ends of the output lines are combined into one to form a multiplexer. 3. The superconducting selection circuit according to claim 1, wherein the input ends of the output lines are combined into one to form a decoder. 4. The superconducting selection circuit according to claim 1, characterized in that the bias current flowing through the bias line is superimposed with another signal current.