JPS6151548U - - Google Patents

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Publication number
JPS6151548U
JPS6151548U JP13625784U JP13625784U JPS6151548U JP S6151548 U JPS6151548 U JP S6151548U JP 13625784 U JP13625784 U JP 13625784U JP 13625784 U JP13625784 U JP 13625784U JP S6151548 U JPS6151548 U JP S6151548U
Authority
JP
Japan
Prior art keywords
address
lsi
bus
personalization
write signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13625784U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP13625784U priority Critical patent/JPS6151548U/ja
Publication of JPS6151548U publication Critical patent/JPS6151548U/ja
Pending legal-status Critical Current

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  • Bus Control (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本考案の実施例を示すブロツク図、第
２図は各ＬＳＩ回路に設けられる個性化回路の構
成例を示す回路図である。 FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a circuit diagram showing an example of the configuration of an individualization circuit provided in each LSI circuit.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 個性化用のアドレスを転送する母線を有する処
理装置と、前記アドレスによつてそれぞれ個性化
される複数のＬＳＩ回路とで構成され、各ＬＳＩ
回路が、前記母線に接続された個性化レジスタと
、前記処理装置からの書込み信号に応答して、前
記母線上のアドレスを前記個性化レジスタへロー
ドさせ、然る後前記書込み信号によるアドレスの
ロードを禁止する書込み制御手段とを含むことを
特徴とする、ＬＳＩ回路を個性化するためのシス
テム。 Consisting of a processing device having a bus line for transferring addresses for individualization, and a plurality of LSI circuits each individualized by the address, each LSI
A personalization register connected to the bus, and a circuit responsive to a write signal from the processing unit to cause an address on the bus to be loaded into the personalization register, and then loading the address by the write signal. 1. A system for individualizing an LSI circuit, comprising: a write control means for inhibiting writing.
JP13625784U 1984-09-10 1984-09-10 Pending JPS6151548U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13625784U JPS6151548U (en) 1984-09-10 1984-09-10

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13625784U JPS6151548U (en) 1984-09-10 1984-09-10

Publications (1)

Publication Number Publication Date
JPS6151548U true JPS6151548U (en) 1986-04-07

Family

ID=30694721

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13625784U Pending JPS6151548U (en) 1984-09-10 1984-09-10

Country Status (1)

Country Link
JP (1) JPS6151548U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20200071420A (en) 2018-12-11 2020-06-19 (주)포인트엔지니어링 Probe card and method for manufacturing the same

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54132142A (en) * 1978-04-05 1979-10-13 Mitsubishi Electric Corp Input/output device identifying system for electronic computer system
JPS5938829A (en) * 1982-08-28 1984-03-02 Sony Corp Automatic setting device of slave machine number

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54132142A (en) * 1978-04-05 1979-10-13 Mitsubishi Electric Corp Input/output device identifying system for electronic computer system
JPS5938829A (en) * 1982-08-28 1984-03-02 Sony Corp Automatic setting device of slave machine number

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20200071420A (en) 2018-12-11 2020-06-19 (주)포인트엔지니어링 Probe card and method for manufacturing the same

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