JPS6144837U - 半導体用パツケ−ジ - Google Patents

半導体用パツケ−ジ

Info

Publication number
JPS6144837U
JPS6144837U JP1984130215U JP13021584U JPS6144837U JP S6144837 U JPS6144837 U JP S6144837U JP 1984130215 U JP1984130215 U JP 1984130215U JP 13021584 U JP13021584 U JP 13021584U JP S6144837 U JPS6144837 U JP S6144837U
Authority
JP
Japan
Prior art keywords
cavity
semiconductor package
solder
metal
bonding pad
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1984130215U
Other languages
English (en)
Other versions
JPH0342681Y2 (ja
Inventor
康 川上
正博 秋山
幸太郎 田中
Original Assignee
沖電気工業株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 沖電気工業株式会社 filed Critical 沖電気工業株式会社
Priority to JP1984130215U priority Critical patent/JPS6144837U/ja
Publication of JPS6144837U publication Critical patent/JPS6144837U/ja
Application granted granted Critical
Publication of JPH0342681Y2 publication Critical patent/JPH0342681Y2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item

Landscapes

  • Wire Bonding (AREA)
  • Die Bonding (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【図面の簡単な説明】
第１図はこの考案の半導体用パッケージの一実筒．例の
構成を略線的に示す平面図、第２図Ａ−Ｄはこの考案の
半導体用パッケージの実施例の要部をそれぞれ示す略線
的断面図、第３図Ａ及びＢは従来の半導体用パッケージ
の説明に供する平面図及び断面図である。 １・・・セラミック基板、２・・・半導体チップ、３・
・・キャビテイ、４，５・・・ボンデイングパッド、６
・・・第一金属の膜、７・・・第二金属の膜、８・・・
フレーム、９・・・半田、１０・・・金ワイヤ、１１・
・・半田流出防止部、１２・・・（隆起部としての）焼
結アルミナ、１３・・・棒状材、１４・・・溝。

Claims (1)

  1. 【実用新案登録請求の範囲】 １ 一枚のセラミック基板上に半導体チップを半田付け
    して搭載するためのキャビテイと、複数個のワイヤボン
    デイング用のボンデイングパツドとを具え、該ボンデイ
    ングパツドのうちの少なくとも一個以上を前記キャビテ
    イとつなげて形成して成る半導体用パッケージにおいて
    、該キャビテイとボンデイングパツドとの境界部に半田
    流出防止部を具えていることを特徴とする半導体用パッ
    ケージ。 ２ 前記半田流出防止部を半田に対してぬれ性の悪い金
    属で形成したことを特徴とする実用新案登録請求の範囲
    第１項記載の半導体用パッケージ。 ３ 前記半田流出防止部を絶縁性隆起部で形成したこと
    を特徴とする実用新案登録請求の範囲第１項記載の半導
    体用パッケージ。 ４ 前記半田流出防止部を、前記キャビテイの半導体チ
    ップが搭載される面側の金属及びボンデイングパッドの
    表面側の金属と同一の金属で、隆起部として形成したこ
    とを特徴とする実用新案登録請求の範囲第１項記載記載
    の半導体用パッケージ。
JP1984130215U 1984-08-28 1984-08-28 半導体用パツケ−ジ Granted JPS6144837U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1984130215U JPS6144837U (ja) 1984-08-28 1984-08-28 半導体用パツケ−ジ

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1984130215U JPS6144837U (ja) 1984-08-28 1984-08-28 半導体用パツケ−ジ

Publications (2)

Publication Number Publication Date
JPS6144837U true JPS6144837U (ja) 1986-03-25
JPH0342681Y2 JPH0342681Y2 (ja) 1991-09-06

Family

ID=30688831

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1984130215U Granted JPS6144837U (ja) 1984-08-28 1984-08-28 半導体用パツケ−ジ

Country Status (1)

Country Link
JP (1) JPS6144837U (ja)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52149971A (en) * 1976-06-09 1977-12-13 Oki Electric Ind Co Ltd Semiconductor integrated circuit device
JPS55145047U (ja) * 1979-04-02 1980-10-17
JPS5812333A (ja) * 1981-07-15 1983-01-24 Toshiba Corp 半導体装置
JPS58138056A (ja) * 1982-02-12 1983-08-16 Mitsubishi Electric Corp 半導体装置

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52149971A (en) * 1976-06-09 1977-12-13 Oki Electric Ind Co Ltd Semiconductor integrated circuit device
JPS55145047U (ja) * 1979-04-02 1980-10-17
JPS5812333A (ja) * 1981-07-15 1983-01-24 Toshiba Corp 半導体装置
JPS58138056A (ja) * 1982-02-12 1983-08-16 Mitsubishi Electric Corp 半導体装置

Also Published As

Publication number Publication date
JPH0342681Y2 (ja) 1991-09-06

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