JPS6143448A - Aerial wiring - Google Patents

Abstract

PURPOSE:To form an aerial wiring pertinent to LSI production by a method wherein the wiring is supported by a metallic body in electrodes while by insulating film in specified positions. CONSTITUTION:A drain electrode 211 of GaAs MESFET21 and a gate electrode 221 of GaAs MESFET22 are connected to each other by a wiring 24 supported by posts 211, 221 and supporters 25, 26 made of e.g. SiO2 provided halfway. This wiring 24 is firstly provided with FETs 21, 22 and then successively coated with Si3N4. At this time, the drain electrode 211 of FET21 and the gate electrode 221 of FET22 are respectively formed into throughholes by dry-etching process. Finally the wirin made of TiAu is formed while specified positions 29, 30 are covered with photoresist patterns and then SiO2 is removed by etching process to form an aerial wiring.

Description

Detailed Description of the Invention (Usage for ordinary work! Jf) The present invention is particularly useful for wiring, especially space wiring having a structure in which most of the wiring is spatially separated from the substrate, so that the parasitic capacitance is extremely small. Regarding.

(Prior art and its problems) In the past one or two years, there has been an extremely large demand for computers to become ultra-large and ultra-high-speed, and to support this demand ultra-high-speed computers have been required.
The development of LSI is proceeding with great force in various places. For example, in order to speed up the S-like Ipolar LSI, a self-alignment method (
By making full use of advanced manufacturing technologies such as the cell 7-align method, the speed of bipolar transistors, which are the main element thereof, is being increased. In addition, a more innovative technology is the gallium arsenide field effect transistor (G
aAsMESFET) as the main element
Research on 5LSI is also progressing.

In such an ultrahigh-speed LSI, the factors that determine the operating speed include the characteristics of the main element (transistor) itself (If!I, cutoff frequency/T), and the parasitic capacitance of the wiring. This will be explained as follows regarding a circuit using GaAs MESFET. That is, GaAs
Assuming that the mutual conductance of the MESFET is fl, l, the input capacitance is C□, and the wiring capacitance t'c, t, the transmission delay time tpd is roughly expressed as Kfi as follows: CjlA, +
ct tpa藝□ (1) ffl Now, if the wiring length is long <C, >>C, j, (Equation 11 is tpd, oCCL/ ,, n(2) υ, tpd worsens in proportion to C1 In the case of GaAs LSI, the wiring is on a semi-insulating substrate.

Alternatively, an insulating film formed on the substrate, such as Sin,
Formed on the film, its opposite surface (relative to the back surface of the substrate)
The capacity reaches 50 to 1007F per wiring.

In a normal LSI, the wiring length per fan-out may be 2 to 3 degrees, and with a correspondingly large parasitic capacitance, the tpd is less than 100p8ee.
It was not easy to obtain f.

For the above-mentioned reasons, reduction of wiring capacitance, that is, low-capacitance wiring, is essential for realizing ultra-high-speed LSIs, but such wiring has not always been proposed in the past. As one type of low capacitance wiring, there is a space wiring that is rarely used in the fabrication of GaA8MES-FETs.

Figure 1 shows an example of this.Ashi, sauce 11. This is an example in which gates 12 and drains 13 are made alternately, and for example, sources 11 are connected to each other by a space wiring 14. Drain 13,
The gates 12 are connected separately to form one GaAs MES'FET k as a whole. This type of spatial wiring is effective when the electrodes are close to each other, but it is not suitable for applications where the distance between the electrodes is more than tin, as in normal LSIs, depending on the frequency. There is a problem.

(Object of the Invention) The object of the present invention was made in view of the above-mentioned problems in the prior art, and it is an object of the present invention to provide a space wiring suitable for Lsxg construction.

(Structure of the Invention) According to the present invention, the electrodes to be connected are supported by a metal film and at desired distances by an insulating film. The space wiring is characterized in that it is formed in a sagging 'i'c pole, is spatially separated from the wiring, and the insulating film.

(Example) Next, the spatial wiring according to the present invention will be explained in detail using the second figure. Figure 2 (a) shows two GaAs MESFETs 21
．． 22'i, FIG. 22(b) is a top view of the integrated circuit when the electric circuit is realized on the substrate 23, and FIG. FIG. The wiring shown as an example is GaAs MESFET21
The wiring 24 connects the drain electrode 211 of the GaAs MESFET 22 and the gate electrode 221 of the GaAs MESFET 22;
4 is supported by utility poles 211, 221 and supports made of, for example, Si02 provided midway: l'l, 26. In addition, in the implementation row, GaAsMESF'E
T21.22, the surface of the GaAs substrate 23, and the first layer wiring 28 are protected by an insulating film such as 5i3N427. Creating such space wiring is not difficult.

First, GaAs MESFETs 21 and 22 were fabricated using the usual method.
F was manufactured, followed by S with a thickness of approximately 3000A and 111m.
i3N4.

S toy is sequentially applied. Next, in order to obtain electrical continuity between the second layer wiring and the electrode, place the TL electrode 2 of the GaAs MESFET 21 at a desired location (in this example, the TL electrode 2 of the GaAs MESFET 21)
11. Gate electrode 221 of GaAs MESFET 22
) through-holes are formed by complete dry etching.
Next, by a normal method, a thickness of 1 μm made of TiAu, for example, is
A wiring 24 having a width of m9 and a width of 2 μm is formed. Next, in order to make the wiring a space wiring, a predetermined location 29.30'i on the wiring is
In the spatial wiring obtained using the photoresin pattern, the capacitance is small because there is air with a relative electrical coefficient of 1 between the wiring and the board. The intersection between the first layer wiring 28 and the first layer wiring 28 is also extremely small compared to the case where they are separated by a vague separation. According to the inventor, Soyu, if the distance between the wiring and the board is 1 μnL, the wiring ground response force is the same as the conventional M5 membrane 27.
Approximately 1/2 of the cost when wiring is formed directly on top. The cross section was reduced to about 14.

What about the space wiring according to the present invention? +4 construction, manufacturing method.

Although the effects have been explained in detail, the first effect in this example is
It goes without saying that the protective films S+ and N427 in the layers are not necessarily arbitrary and can be omitted. Needless to say.

? Electrode, 12... Gate electrode, 13... Drain electrode, 21.22-GaAsMESFET, 211-...
Drain electrode, 212...Gate electrode, 23...Substrate, 24.Space wiring, 25, 26-...Support (SiO
, ), 27 ・-8i, N4 film, 28 ・・first layer wiring,
29.30...Photoresist pattern.

Industrial Technology gF, Ryokawada) $ WR1 diagram er? (21 f −□23 -゛27F1-

Claims (1)

[Claims] In wiring for interconnecting a plurality of electrodes formed on a substrate, the wiring is supported by a metal body in the electrode portion and by an insulating film at discrete desired locations. A spatial wiring characterized in that it is spatially separated from the substrate or the electrodes, wiring, and insulating film formed on the substrate.