JPS6143448A - Aerial wiring - Google Patents
Aerial wiringInfo
- Publication number
- JPS6143448A JPS6143448A JP16487384A JP16487384A JPS6143448A JP S6143448 A JPS6143448 A JP S6143448A JP 16487384 A JP16487384 A JP 16487384A JP 16487384 A JP16487384 A JP 16487384A JP S6143448 A JPS6143448 A JP S6143448A
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- gaas
- supported
- gate electrode
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
(並業上の利用分!Jf )
本発明は配線とくに、その大部分が基板から空間的に隔
てられた構造を有するために、寄生静電容量が極めて小
さい空間配線に関する。Detailed Description of the Invention (Usage for ordinary work! Jf) The present invention is particularly useful for wiring, especially space wiring having a structure in which most of the wiring is spatially separated from the substrate, so that the parasitic capacitance is extremely small. Regarding.
(従来技術とその問題点)
この1,2年コンピュータの超大型化、超高速化の要請
は極めて大きいものがあり、それを支えるための超高!
LSIの開発が各所で杓力的に進められている。例えば
SしくイポーラLSIの高速化のためには自己整仕法(
セル7アライン法ンを始めとする高度の製造技術を駆使
することにより、その主要素子であるバイポーラ・トラ
ンジスタの高速化が進められている。またより画期的な
技術としてガリウム砒素電界効果トランジスタ(以下G
aAsMESFETと称す)を主要素子とするCaA
5LSIの研究も進められている。(Prior art and its problems) In the past one or two years, there has been an extremely large demand for computers to become ultra-large and ultra-high-speed, and to support this demand ultra-high-speed computers have been required.
The development of LSI is proceeding with great force in various places. For example, in order to speed up the S-like Ipolar LSI, a self-alignment method (
By making full use of advanced manufacturing technologies such as the cell 7-align method, the speed of bipolar transistors, which are the main element thereof, is being increased. In addition, a more innovative technology is the gallium arsenide field effect transistor (G
aAsMESFET) as the main element
Research on 5LSI is also progressing.
このような超高速LSIにおいて、その動作速度を決定
する要因としては主要素子(トランジスタ)自身の特性
(If!Iえば遮断周波数/T)の他に配線の寄生容量
がある。このことをGaAsMESFETを用いた回路
について説明すると次のようになる。すなわちGaAs
MESFETの相互フンダクタンスを、fl、l、入力
容量をC□、配線容量t′c、tとすると、伝達遅延時
間tpdは概略次式のようKfiわせる:CjlA、+
ct
tpa藝□ (1)
ffl
いま配線長が長<C,>>C,j とすると(11式は
tpd、oCCL/
、、n(2)
となυ、tpdはC1に比例して悪化することがわかる
。GaAs LS Iの場合、配線は半絶縁性基板上。In such an ultrahigh-speed LSI, the factors that determine the operating speed include the characteristics of the main element (transistor) itself (If!I, cutoff frequency/T), and the parasitic capacitance of the wiring. This will be explained as follows regarding a circuit using GaAs MESFET. That is, GaAs
Assuming that the mutual conductance of the MESFET is fl, l, the input capacitance is C□, and the wiring capacitance t'c, t, the transmission delay time tpd is roughly expressed as Kfi as follows: CjlA, +
ct tpa藝□ (1) ffl Now, if the wiring length is long <C, >>C, j, (Equation 11 is tpd, oCCL/ ,, n(2) υ, tpd worsens in proportion to C1 In the case of GaAs LSI, the wiring is on a semi-insulating substrate.
あるいは該基板上に形成された絶縁膜、例えばSin、
膜上に形成されておシ、その対地(基板裏面に対する)
容量は配線1市当り50〜1007Fにも達している。Alternatively, an insulating film formed on the substrate, such as Sin,
Formed on the film, its opposite surface (relative to the back surface of the substrate)
The capacity reaches 50 to 1007F per wiring.
通常のLSIにおいては1 fan−out当りの配線
長は2〜3關になることもあシ、それに相当した大きな
寄生容量のもとて例えば100p8ee以下のtpd
f得ることは容易でなかった。In a normal LSI, the wiring length per fan-out may be 2 to 3 degrees, and with a correspondingly large parasitic capacitance, the tpd is less than 100p8ee.
It was not easy to obtain f.
以上の様な理由から配線容量の低減すなわち低容量配線
は超高速LSI実現の上で不可欠であるが、従来そのよ
うな配線は必ずしも提案されていなかった。たソ低容量
配線の1つとしてGaA8MES −FETの製作にま
れに用いられる空間配線が在る。For the above-mentioned reasons, reduction of wiring capacitance, that is, low-capacitance wiring, is essential for realizing ultra-high-speed LSIs, but such wiring has not always been proposed in the past. As one type of low capacitance wiring, there is a space wiring that is rarely used in the fabrication of GaA8MES-FETs.
第1図はその例でアシ、ソース11.ゲート12゜ドレ
イン13を交互に製作し、例えばソース11どうしを空
間配線14で連結した例である。ドレイン13どうし、
およびゲート12どうしは別途連結され全体として1個
のGaAsMES’FET k形成している。このよう
な空間配線は電極どうしが近接している場合には有効で
あるが、通常のLSIのように、場合によっては電極間
がtin以上も陥れている場合に適用するのは、その頻
度に於て問題がある。Figure 1 shows an example of this.Ashi, sauce 11. This is an example in which gates 12 and drains 13 are made alternately, and for example, sources 11 are connected to each other by a space wiring 14. Drain 13,
The gates 12 are connected separately to form one GaAs MES'FET k as a whole. This type of spatial wiring is effective when the electrodes are close to each other, but it is not suitable for applications where the distance between the electrodes is more than tin, as in normal LSIs, depending on the frequency. There is a problem.
(発明の目的)
本発明の目的は従来技術における以上の問題点に鑑みて
なされたものでl、Lsxg造に適した空間配線を提供
することにある。(Object of the Invention) The object of the present invention was made in view of the above-mentioned problems in the prior art, and it is an object of the present invention to provide a space wiring suitable for Lsxg construction.
(発明の構成)
本発明によれば、連結すべき電極部に於て金属膜により
、また離数的なる所望の箇所において絶縁膜によシ支見
られている他は、基板、あるいは基板上に形成されだる
’i’c極、配線、絶縁膜から空間的に隔てられている
ことを特徴とする空間配線かえられる。(Structure of the Invention) According to the present invention, the electrodes to be connected are supported by a metal film and at desired distances by an insulating film. The space wiring is characterized in that it is formed in a sagging 'i'c pole, is spatially separated from the wiring, and the insulating film.
(実施例)
次に第2図音用いて本発明による空間配線全詳細に説明
する。第2図(a)は2個のGaAsMESFET21
.22’i用いてなる電気回路、同図(b)は該電気回
路を基板23上に実現した時の集積回路の上面図、同図
(c)は(b)図におけるA−A’断面を示す図である
。実施例として示す配線はGaAs MESFET21
のドレイン電極211とGaAsMESFET22のゲ
ート電極221を連結する配線24であり、゛該配線2
4は電柱211,221および途中に設けられた例えば
S i02よりなる支持体:l’l、26によシ支えら
れている。なお実施列においてはGaAsMESF’E
T21.22およびGaAs基板23表面および第1層
配線28は絶縁膜例えば5i3N427により保護され
ている。このような空間配線の製作は困難でなく。(Example) Next, the spatial wiring according to the present invention will be explained in detail using the second figure. Figure 2 (a) shows two GaAs MESFETs 21
.. 22'i, FIG. 22(b) is a top view of the integrated circuit when the electric circuit is realized on the substrate 23, and FIG. FIG. The wiring shown as an example is GaAs MESFET21
The wiring 24 connects the drain electrode 211 of the GaAs MESFET 22 and the gate electrode 221 of the GaAs MESFET 22;
4 is supported by utility poles 211, 221 and supports made of, for example, Si02 provided midway: l'l, 26. In addition, in the implementation row, GaAsMESF'E
T21.22, the surface of the GaAs substrate 23, and the first layer wiring 28 are protected by an insulating film such as 5i3N427. Creating such space wiring is not difficult.
まず通常の方法によりGaAsMESFET21,22
f製作し、つづいて厚み約3000A 、111mのS
i3N4 。First, GaAs MESFETs 21 and 22 were fabricated using the usual method.
F was manufactured, followed by S with a thickness of approximately 3000A and 111m.
i3N4.
S toyを順次被着せしめる。次に第2層配線と電極
との電気的導通を得るために所望の場所(本実施例にお
いてはGaAsMESFET 21のトンインTL極2
11、GaAsMESFET 22のゲート電極221
)にスルーホール全ドライエツチングにより形成する、
次に通常の方法により例えばTiAuよりなる厚み1μ
m9幅2μmの配線24を形成する。次に該配線を空間
配線とするために、配線上の所定の場所29.30’i
ホトレジヌトパターンで穫ったのこの上うな空間配線に
おいては配線と基板との11」に比お電率が1の空気が
介在しているためその容量は小きく、また該配線24と
第1層配線28との間の交差8紙もS+O,$07−縁
)漠で分離されている場合に比べて極めて小さい。発明
者の央幽によると、配線と基板の間の間隔を1μnLと
すると、配線の対地答力士は従来のようにM5縁膜27
上に直接配線を形成した場合の約1/2.交叉容址は約
14に低減した。S toy is sequentially applied. Next, in order to obtain electrical continuity between the second layer wiring and the electrode, place the TL electrode 2 of the GaAs MESFET 21 at a desired location (in this example, the TL electrode 2 of the GaAs MESFET 21)
11. Gate electrode 221 of GaAs MESFET 22
) through-holes are formed by complete dry etching.
Next, by a normal method, a thickness of 1 μm made of TiAu, for example, is
A wiring 24 having a width of m9 and a width of 2 μm is formed. Next, in order to make the wiring a space wiring, a predetermined location 29.30'i on the wiring is
In the spatial wiring obtained using the photoresin pattern, the capacitance is small because there is air with a relative electrical coefficient of 1 between the wiring and the board. The intersection between the first layer wiring 28 and the first layer wiring 28 is also extremely small compared to the case where they are separated by a vague separation. According to the inventor, Soyu, if the distance between the wiring and the board is 1 μnL, the wiring ground response force is the same as the conventional M5 membrane 27.
Approximately 1/2 of the cost when wiring is formed directly on top. The cross section was reduced to about 14.
以上本発明による空間配線の?+4造、製造方法。What about the space wiring according to the present invention? +4 construction, manufacturing method.
効果について詳しく説明したが、本実施例における第1
層目の保護膜s+、N427は必ずしも奉賀的でなく省
略することができることはbうまでtない8また本発明
は上記実km例におけるごときGaAs LS Iに限
ることな(SiLSrにも十分適用されることは言うま
でもない。Although the effects have been explained in detail, the first effect in this example is
It goes without saying that the protective films S+ and N427 in the layers are not necessarily arbitrary and can be omitted. Needless to say.
?電極、12・・・ゲート電極、13・・・ドレイン電
極、21.22−GaAsMESFET、211−・・
ドレイン電極、212・・ゲート電極、23・・・基板
、24・空間配線、25 、26−・・支持体(SiO
,)、27 ・−8i、N4膜、28・・第1層配線、
29.30・・・ホトレジストパターン。? Electrode, 12... Gate electrode, 13... Drain electrode, 21.22-GaAsMESFET, 211-...
Drain electrode, 212...Gate electrode, 23...Substrate, 24.Space wiring, 25, 26-...Support (SiO
, ), 27 ・-8i, N4 film, 28 ・・first layer wiring,
29.30...Photoresist pattern.
工業技術gF、良川田用)$ WR1図 爾 ?(21 f −□23 −゛27F1−Industrial Technology gF, Ryokawada) $ WR1 diagram er? (21 f −□23 -゛27F1-
Claims (1)
の配線に於て、該配線が前記電極部に於て金属体により
、また離散的なる所望の箇所において絶縁膜により支え
られている他は、前記基板あるいは基板上に形成された
る電極、配線、絶縁膜から空間的に隔てられていること
を特徴とする空間配線。In wiring for interconnecting a plurality of electrodes formed on a substrate, the wiring is supported by a metal body in the electrode portion and by an insulating film at discrete desired locations. A spatial wiring characterized in that it is spatially separated from the substrate or the electrodes, wiring, and insulating film formed on the substrate.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP16487384A JPS6143448A (en) | 1984-08-08 | 1984-08-08 | Aerial wiring |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP16487384A JPS6143448A (en) | 1984-08-08 | 1984-08-08 | Aerial wiring |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6143448A true JPS6143448A (en) | 1986-03-03 |
Family
ID=15801545
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP16487384A Pending JPS6143448A (en) | 1984-08-08 | 1984-08-08 | Aerial wiring |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6143448A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61133645A (en) * | 1984-12-04 | 1986-06-20 | Toshiba Corp | Semiconductor device and manufacture thereof |
JPH01264243A (en) * | 1988-04-14 | 1989-10-20 | Nec Corp | Semiconductor device and its manufacture |
US6806181B2 (en) | 2001-03-30 | 2004-10-19 | Fujitsu Quantum Devices Limited | Method of fabricating an air bridge |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5568700A (en) * | 1978-11-14 | 1980-05-23 | Philips Nv | Wiring device and method of manufacturing same |
-
1984
- 1984-08-08 JP JP16487384A patent/JPS6143448A/en active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5568700A (en) * | 1978-11-14 | 1980-05-23 | Philips Nv | Wiring device and method of manufacturing same |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61133645A (en) * | 1984-12-04 | 1986-06-20 | Toshiba Corp | Semiconductor device and manufacture thereof |
JPH01264243A (en) * | 1988-04-14 | 1989-10-20 | Nec Corp | Semiconductor device and its manufacture |
US6806181B2 (en) | 2001-03-30 | 2004-10-19 | Fujitsu Quantum Devices Limited | Method of fabricating an air bridge |
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