JP3000124B2 - Method for manufacturing insulated gate field effect transistor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for fabricating an insulated gate field effect transistor (IGFET) generally referred to as a MOS type or MIS type.

[0002]

2. Description of the Related Art A drain region and a source region are formed on a surface of a semiconductor layer so as to be separated from each other.
As represented by a MOS type having a gate provided on a channel region between sources via a gate insulating film,
Insulated gate field-effect transistors (hereinafter sometimes simply referred to as "elements" for simplicity) that control the amount of current selectively flowing in a channel region in response to a signal voltage applied to a gate have various structures. It has become one of the basic active elements in the field of semiconductor integrated circuits, including those that have been modified.

However, in order to increase the integration density, the dimensions of individual elements have become extremely fine, while as the area of the integrated circuit chip itself has increased, so-called gate wiring delay with respect to the gate of each element has increased. The problem has come to light. For example, in a typical element in the related art, polycrystalline silicon has been frequently used for gates and gate wirings because of its easiness of manufacture and handling, and good compatibility with silicon-based semiconductor substrates.

However, the specific resistance of polycrystalline silicon is 500 μm.
There is about Ωcm. Therefore, even if the existence of the gate input resistance of each element is not considered, the signal propagation to the gate according to the time constant which is the product of the stray capacitance and the resistance component that increases in proportion to the wiring length of the polycrystalline silicon. The delay also becomes a serious problem in an integrated circuit in which each element becomes extremely fine as described above, while the chip area tends to increase.

A paper by BAKOGLU et al. (IEEE Tran. Electron De
According to Vices, ED-32, No. 5, 1985, p. 903-909), such a wiring delay can increase in proportion to the product of the square of the scale factor S and the square of the scale factor Sc of the chip size. These wiring delays are now no longer considered to be a serious problem, as it is conceivable that the integration density will increase even further in the future, while the chip size will definitely increase significantly in the future. There must be.

Therefore, conventionally, as a gate and a gate wiring of such an insulated gate field effect transistor,
Attempts have been made to use metal silicides whose specific resistance is one digit lower than polycrystalline silicon or refractory metals that are two orders of magnitude lower than polycrystalline silicon.

[0007]

However, the degree is still insufficient. As is well known, the density of an integrated circuit is generally required to be increased in accordance with the quadruple rule, and the chip size is required to be increased. In fact, it is expected that the integration density and chip size will increase dramatically in the very near future.

However, there has been no material proposed as a practically usable material in addition to the materials described above. This does not mean, for example, that simply having a small specific resistance is sufficient.Even if it is used as a gate of an insulated gate type field effect transistor, it has no adverse effect on the manufacturing process of the device and on the electrical characteristics, or conversely. This is because the material must not be adversely affected.

The present invention has been made in view of such circumstances, and is a material capable of greatly reducing a signal propagation delay under the operation of an element, that is, a material having a very small specific resistance under the operation of the element. Another object of the present invention is to provide an insulated gate field effect transistor in which a gate and a gate wiring are made of a material which does not cause a problem in an element manufacturing process and electric characteristics and is not adversely affected by itself.

Further, as a result of achieving the above object, the present invention can coexist with a Josephson integrated circuit that operates in a so-called cryogenic environment, and in particular, is outside the cryogenic environment with the Josephson integrated circuit. No integrated circuit device that can function as an interface with an external circuit (such as a semiconductor layer integrated circuit) is provided.

[0011]

SUMMARY OF THE INVENTION In order to achieve the above object, the present invention provides a gate and a gate wiring of an insulated gate type field effect transistor based on common sense which has been limited to the specific resistance at room temperature as in the past. I escaped. That is, on the premise that the insulated gate field effect transistor itself is operated in a cryogenic environment, the resistance is extremely reduced by substantially transitioning to a superconducting state in the cryogenic environment,
It is proposed to use a niobium carbonitride film or a niobium nitride film as a constituent material of a gate and a gate wiring as a material which can be substantially zero. These materials are resistant to the high heat applied in the heat treatment required when fabricating an insulated gate field effect transistor, and have substantially no adverse effect on other layers, and, consequently, the completed insulated gate field effect transistor. It is a material that does not hinder other various electrical characteristics other than improving the gate wiring delay of the effect transistor.

Further, the present invention provides a method of manufacturing an insulated gate field effect transistor based on the above-described basic idea, comprising: forming a silicon oxide film 12 on a p-type silicon substrate 11; Forming a niobium carbonitride film 14 or a niobium nitride film 14 thereon; forming an opening for defining a drain region and a source region in the silicon oxide film 12 and the niobium carbonitride film 14 or the niobium nitride film 14; Introducing impurities to form the drain region 16D and the source region 16S; and forming the formed drain region 16D and the source region 16S into 800
Annealing for a predetermined time in a temperature range of from 900 ° C. to 900 ° C .; and etching the niobium carbonitride film 14 or the niobium nitride film 14 according to a predetermined pattern to form a part of the niobium carbonitride film 14 or the niobium nitride film 14. And a portion located between the drain region 16D and the source region 16S and a predetermined pattern portion continuous with this portion are left as a gate 14G and a gate continuous portion 14G 'continuous with the gate, respectively, and are thus left. Using the oxide film portion 12 located between the gate 14G and the semiconductor substrate 11 as a gate insulating film 12G; a silicon oxide film 12, a drain region 16D, and a source region 16S.
Forming a series of interlayer insulating films 18 on the respective surfaces of the gate 12G and the gate continuity portion 14G '; and forming a drain region 16D and a source region 16S on the interlayer insulating film 18;
Opening contact forming openings 16H, 16H, 14GH for each of the gate continuity portions 14G 'and the surface of the interlayer insulating film 18 and the contact forming openings 16H, 16
Forming a series of wiring niobium carbonitride films 20 or niobium nitride films 20 in H and 14GH; and etching the wiring formation niobium carbonitride films 20 or niobium nitride films 20 into a predetermined pattern to form respective drain regions. 16
D and wiring layers 16L, 16L for source region 16S, and gate
Forming a wiring layer 14L for 14G; and a method for fabricating an insulated gate field effect transistor comprising: The reference numerals used above are the same as those used in the embodiments of the present invention described later.

In the above-described manufacturing method, the p-type silicon substrate 11 can be formed by doping a silicon substrate with boron, and the n-type impurity can be introduced by ion implantation of phosphorus. Further, when the niobium carbonitride film 20 is selected as the superconducting material film 20 for forming the gate and the gate continuous portion, the niobium carbonitride film 20 targets niobium and is formed of a mixed gas of argon, nitrogen, and methane. Can be formed by a reactive high-frequency sputtering method at
When the niobium nitride film 20 is selected, the niobium nitride film 20
Can be formed by a reactive high frequency sputtering method in a mixed gas of argon and nitrogen, targeting niobium.

The present invention further utilizes the fact that the insulated gate field effect transistor obtained by the present invention is supposed to operate in a cryogenic environment, and uses the insulated gate field effect transistor obtained based on the above. As an integrated circuit device in which a plurality of transistors are integrated, the semiconductor layer 11 is the device substrate 26 itself of the integrated circuit device or a semiconductor layer formed on the device substrate 26, and includes the gate 14G and the gate wiring layer. We also propose an integrated circuit device to be used in a cryogenic environment below the superconducting transition temperature where 14L transitions to the superconducting state.

In this case, according to the present invention, a Josephson integrated circuit using a plurality of Josephson elements operating in a cryogenic environment is mounted on the integrated circuit device substrate. Also proposed is an integrated circuit device characterized in that at least some of the Josephson elements are electrically coupled to at least some of the plurality of insulated gate field effect transistors. An integrated circuit device wherein at least some of the field effect transistors are used as a signal level conversion interface between a Josephson integrated circuit and an external circuit (such as a semiconductor integrated circuit) outside a cryogenic environment. Also suggest.

[0016]

FIG. 1 shows the structure of one embodiment of an insulated gate field effect transistor 10 obtained according to the present invention, as well as the arrangement of a preferred embodiment of an integrated circuit device proposed by the present invention. I have. However, for the sake of convenience, the description will be started from the example of a desirable manufacturing process according to the present invention shown in FIG.

In each figure after FIG. 2A, a cross-sectional view up to the process is shown on the left side and a plan view is shown on the right side. First, as shown in FIG. In this preferred embodiment, a p-type silicon substrate 11 having a plane orientation (100) and preferably a boron-doped p-type impurity and a specific resistance of 3 to 5 Ωcm is prepared as a semiconductor layer 11 for forming an element.
This is subjected to a high-temperature treatment at 1100 ° C. for 45 minutes in pure oxygen, and further subjected to a high-temperature treatment at 1100 ° C. for 30 minutes in pure nitrogen to form a silicon oxide film (SiO _{2) having a} thickness of 100 to 120 nm on both front and back surfaces of the substrate 11. After forming the films (12, 13), argon (A) targeting niobium (Nb) is formed on the silicon oxide film 12 on the surface side.
r), a niobium carbonitride (NbCN) film 14 is finally formed as a starting member for forming a gate by a reactive high-frequency sputtering method in a mixed gas of nitrogen (N ₂ ) and methane (CH ₄ ). 200
Deposit to a thickness of about nm.

Next, as shown in FIG. 2B, a resist film 15 is formed, and the area and position of a region to be a drain region and a source region are defined by a known lithography technique. Opening, and using the patterned resist film 15 as an etching mask, carbon fluoride (C
F ₄ ) Dry etching by gas plasma, NbCN
An opening corresponding to the film 14 is opened, and the silicon oxide film 12 thereunder is also etched with hydrofluoric acid, or when high fine workability is required, dry etching is also preferably used at this time. Opening corresponding to the film 12 is also made. As a result, the surface of the substrate 11 is exposed at each of the openings. In addition, the dimension area between these pair of openings is
It is defined at the same time as a region that substantially constitutes the gate.

Thereafter, while using the resist film 15 as a shielding mask at the time of ion implantation while leaving the resist film 15, FIG.
As shown in (C), phosphorus (P) is preferably applied as an n-type impurity to the surface of the substrate 11 exposed to the opening by an accelerating voltage.
Ion implantation is performed at 50 KeV and a dose of 5 × 10 ¹⁵ cm ⁻² to form a pair of n-type regions 16, 16, one of which is a drain region and the other is a source region.

Next, after removing the resist film 15 by ultrasonic cleaning in acetone, in order to make the n-type regions 16 and 16 into n-type regions having good physical properties, NbCN is added in pure nitrogen. film
A temperature as high as 14 can withstand, but does not adversely affect other areas, and considering wasteful use of high temperatures, preferably at 800 to 900 ° C for an appropriate time, for example, about 20 to 30 minutes Anneal. This annealing or heat treatment is an essential step for improving the electrical characteristics of the finally manufactured insulated gate field effect transistor.

After this annealing, as shown in FIG. 2D, the NbCN film 14 located between the pair of n-type regions 16 is left as a gate 14G.
Except for leaving the gate continuity portion 14G 'continuing to 14G, other NbCN
In order to remove the film portion, a resist film 17 patterned into a corresponding pattern is formed by a known existing lithography technique, and is subjected to dry etching using a carbon fluoride gas plasma. The remaining gate 14G made of NbCN film
The silicon oxide film 12 sandwiched between the semiconductor substrate 11 and
This is what is called a gate insulating film 12G. That is, by this step, the gate is substantially formed in a self-aligned manner with respect to each of the drain and source regions, and the skeleton structure as an insulated gate field effect transistor is completed.

FIG. 3 shows a group of steps up to the completion of the formation of the wiring layer for each of the drain, source and gate regions. That is, first, after removing the resist film 17 shown in FIG. 2D by ultrasonic cleaning in acetone, a silicon oxide film (SiO ₂ film) 18 to be an interlayer insulating film 18 is successively formed. For example, it is formed to a thickness of about 200 nm by a high-frequency magnetron sputtering method. On the formed interlayer insulating film 18, a patterned resist film 19 patterned so as to have an opening for forming a contact for each of the pair of n-type regions 16, 16 and the gate continuous portion 14G 'is formed by a known method. An interlayer insulating film formed by lithography using the patterned resist film 19 as an etching mask.
Etch 18 with hydrofluoric acid or dry etch. As a result, as shown in FIG. 3A, contact forming openings 16H, 16H exposing the surfaces of the pair of n-type regions 16, 16 and gate contact forming exposing the gate continuity portion 14G ', respectively. An opening 14GH is formed.

Thereafter, the resist film 19 is removed by ultrasonic cleaning in acetone, preferably after Ar sputtering cleaning, and finally, as shown in FIG. As a starting material for forming a wiring layer electrically connected to the gate region and having a predetermined wiring pattern, preferably, the same material as that used for forming the gate, that is, the NbCN film 20 in this embodiment. Is deposited to a suitable thickness, for example, about 500 nm by a reactive high-frequency sputtering method (of course, this material penetrates and deposits in the openings 16H, 16H, and 14GH for forming the respective contacts, and the n-type regions 16, 16 and each surface of the gate continuity portion 14G '), and further thereon, a patterned resist film 21 patterned according to a wiring pattern to be finally obtained is coated with a known and suitable resin. It is formed by the photography technology.

When etching (preferably dry etching with high dimensional accuracy) is performed using the formed patterned resist film 21 as an etching mask, as shown in FIG. 3C, each of the n-type regions of the pattern to be finally obtained is obtained. (For drain and source regions) Wiring layers 16L, 16L and gate wiring layer
14L is obtained.

Thereafter, the resist film 21 is removed, and although not shown, the front side is covered with a resist layer, and then the silicon oxide film 13 on the back side of the substrate is removed with hydrofluoric acid. For example, when the back electrode 22 made of an NbCN film is formed to have a suitable thickness, for example, about 200 nm by the reactive high frequency sputtering method, the insulated gate type as one embodiment of the present invention whose sectional shape is shown in FIG. The field effect transistor 10 can be obtained.

In the insulated gate field effect transistor 10 shown in FIG. 1A, one of a pair of n-type regions 16 and 16, for example, the n-type region 16 on the left side in the figure is replaced with a source region 16S. If so, the other n-type region 16 can be used as the drain region 16D, and the surface region between the two regions 16S and 16D on the surface of the semiconductor substrate 11 is a so-called channel region 16C. Then, on the channel region 16C, via the gate insulating film 12, the source,
The gate 14G faces each of the drain regions 16S and 16D in a self-aligned relationship.

However, in the present device 10, both the gate 14G and the wiring 14L thereof (not shown in FIG. 1; see FIG. 3C) are both manufactured by the superconducting material, particularly in accordance with the above-described manufacturing process example. The device is composed of an NbCN film. Therefore, as shown in FIG. 1A, a cooling tank 23 filled with a refrigerant 24 (generally, liquid helium) capable of cooling the entire element 10 to a temperature lower than the temperature at which the superconducting material changes to a superconducting state. By operating the gate 14G and the wiring layer 14L, the resistance can be regarded as substantially zero.

This is a great effect, and the size of each element will be miniaturized in the future, while the chip size of an integrated circuit in which a large number of these elements are integrated will be greatly increased. Even if the per-element length is considerably increased, the effect is substantially negligible, and the signal propagation delay to the gate is greatly improved. This also means that the gate processing time (so-called gate delay) is greatly reduced when each element is considered as a single-stage gate, and as a result, the processing speed of the entire integrated circuit can be significantly increased. .

In the case of the above-described embodiment, the wirings 16L and 16L for the drain and source regions are also connected to the NbCN
Since the circuit is constituted by the film 20, in a circuit in which a signal is superimposed on these lines, the speed of signal propagation can be similarly increased.

However, as described with reference to FIGS. 2B and 2C, the NbCN film 14 for forming the gate 14G and the wiring layer 14L is finally formed during the above-described manufacturing process. In order to improve the electrical characteristics of the constructed insulated gate field effect transistor, a process of annealing the n-type regions 16 and 16 at a high temperature is added.
It was necessary to verify whether 14 would be damaged and its superconducting properties would not be impaired. Therefore, the present inventor relates to the superconducting transition temperature Tc of the 100 nm thick NbCN film 14 deposited on the 100 nm thick silicon oxide film 12 by the method described above,
The influence of the subsequent n-type region annealing at 800 ° C. was examined, and as shown in FIG. 4, the results showed no significant change even in the annealing time range from 10 minutes to 40 minutes.
The superconducting transition temperature Tc of the NbCN film 14 was about 15K or more, which was sufficiently satisfactory and stable.

Further, an experiment was conducted in view of the electrical characteristics of the insulated gate type field effect transistor. As a result, the insulated gate type field effect transistor 10 having a gate length of 5 μm and a gate width of 10 μm shown in FIG. As a result of operating while cooling to 4.2K with liquid helium 24, the drain-source voltage Vds versus drain current Id characteristic is as shown in FIG. 5 when the gate bias (gate voltage) Vg is in the range of 0 to 5V. Enhanced enhancement characteristics. “Kink” in the figure indicates that the carrier in the substrate 11 is “frozen”
In any case, as is apparent from this figure, it has been proved that the insulated gate field effect transistor 10 manufactured by the above-described process operates sufficiently satisfactorily. In addition, since it is an operation in a cryogenic environment,
In essence, the signal-to-noise ratio (S / N ratio) is much better.

In the above-described example of the manufacturing process, while the other parameters and the application method in each process are the same, the methane gas is used based on the mixed gas composition when forming the superconducting film 14 in the process shown in FIG. Is removed, a niobium nitride (NbN) film 14 is deposited instead of the NbCN film 14. Instead of forming the NbCN film 20 in the step shown in FIG.
The same applies when the film 20 is formed.

However, even if the NbN film 20 is used as a starting material for forming a gate, it will not
Withstands annealing at high temperatures of 16 and 16, and
By the same experiment as shown in, the NbCN
It was also found that the membrane 20 could be substituted. However, when depositing the NbN film 20, it is necessary to raise the substrate temperature to several hundred degrees Celsius.
A superconducting transition temperature of about 15 K similar to that of the CN film 20 was not obtained. Therefore, in that sense, it can be said that it is preferable to use the NbCN film 20 as seen in the above-described example of the manufacturing process.

Conversely, with other superconducting materials, for example, niobium, the temperature cannot be raised to the above-mentioned temperature in the subsequent high-temperature annealing of the n-type regions 16, 16, and a practical element is provided in that sense. Could not be determined to be usable.

FIG. 1B shows an example of an integrated circuit device including the element 10 according to the present invention shown in FIG. 1A. That is, the element 10 shown as the semiconductor substrate 11
A desired circuit is realized by using a plurality of the present elements 10 on an integrated circuit device substrate 26 which may be the semiconductor layer 11 itself, which is a base layer for building, or a separate substrate on which the semiconductor layer 11 is mounted. Integrated circuit 25 is formed, and this is a cooling tank
Josephson is immersed in the refrigerant 24 inside and operates in a cryogenic environment, and on the device substrate 26 is a Josephson integrated device using a plurality of Josephson elements that also operate in a cryogenic environment. The circuit 30 is mounted.

Therefore, if a hybrid integrated circuit is constructed in such a manner that at least some of the plurality of Josephson elements are electrically coupled to at least some of the plurality of elements 10, new functions utilizing the respective features can be obtained. An integrated circuit having the same can be obtained. Conversely, according to the present invention, such a hybrid integrated circuit increases its feasibility. This is because the superconducting material constituting each Josephson element and wiring in the Josephson integrated circuit 30 and the superconducting material constituting the gate and gate wiring, and preferably also the drain and source wiring in the present element 10 are the same material. This is because both integrated circuits 25 and 30 can be constructed on the same substrate while using many elementary processes in common.

In general, the Josephson integrated circuit 30 has to exchange signals with the semiconductor integrated circuit 31 outside the cryogenic environment, but the interface may still be difficult. However, in such a case,
In the integrated circuit 25 using the device 10 of the present invention, at least some of the plurality of insulated gate field effect transistors 10 used therein are connected to the Josephson integrated circuit 30 and an external circuit outside the cryogenic environment (generally, Semiconductor integrated circuit) 31
And can be used as an ultra-high-speed interface for signal level conversion between.

Although the embodiments of the present invention have been described in detail above, the device of the present invention as an apparatus as shown in FIG.
10 is of this kind, except that the gate and the gate wiring are made of niobium carbonitride or niobium nitride which can withstand high-temperature anneal among various materials which transition to a superconducting state under an extremely low temperature environment below the superconducting transition temperature. Various modified structures conventionally proposed as insulated gate field effect transistors can be employed.

[0039]

According to the present invention, the wiring delay related to the gate of an insulated gate field effect transistor can be greatly improved, and the obstacles to miniaturization and large area of an integrated circuit can be eliminated or greatly reduced.

From another point of view, the present invention can speed up the operation of an integrated circuit using an insulated gate field effect transistor.

Further, according to the manufacturing method of the present invention, it is possible to provide an insulated-gate field-effect transistor in which the wiring delay relating to the gate is extremely small at a practical and practical level.

In addition, according to the integrated circuit device of the present invention, a Josephson integrated circuit can be mixed with an external circuit such as a semiconductor integrated circuit placed outside a cryogenic environment. An ultra-high speed interface with an integrated circuit can also be easily constructed.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a cross-sectional structure of an insulated gate field effect transistor manufactured according to the present invention and an integrated circuit formed using the transistor.

FIG. 2 is an explanatory view up to an intermediate step when fabricating an insulated gate field effect transistor according to the present invention.

FIG. 3 is an explanatory diagram of a process from the above-mentioned halfway process to completion of a wiring layer.

FIG. 4 is an explanatory diagram showing that the superconducting transition temperature of the NbCN film used in the present invention is not adversely affected by the annealing process for forming the drain and source regions.

FIG. 5 is a characteristic diagram for verifying that an insulated gate field effect transistor manufactured according to the present invention actually functions satisfactorily.

[Explanation of symbols]

 10 Insulated gate field effect transistor of the present invention, 11 semiconductor layer or semiconductor substrate, 12 silicon oxide film, 12G gate insulating film, 14NbCN film, 14G gate, 14L gate wiring layer, 16 n-type region, 16D drain region, 16S source Area, 16L wiring layer, 18 interlayer insulating film, 20NbCN film, 23 cooling tank, 24 refrigerant (liquid helium), 25 insulated gate field effect transistor integrated circuit, 26 integrated circuit device substrate, 30 Josephson integrated circuit, 31 semiconductor Integrated circuit.

Continuation of the front page (72) Inventor Satoshi Matsumoto 1-4-1 Umezono, Tsukuba-shi, Ibaraki Pref. Japan Institute of Industrial Science and Technology (56) References JP-A-3-276763 (JP, A) JP-A-58- 67045 (JP, A) JP-A-60-154613 (JP, A) JP-A-64-68925 (JP, A) JP-A-61-267207 (JP, A) JP-A-63-138790 (JP, A) (58) Field surveyed (Int. Cl. ⁷ , DB name) H01L 39/00 H01L 39/22 H01L 39/24

Claims (1)

(57) [Claims] A drain region and a source region formed on the surface of the semiconductor layer so as to be separated from each other;
A method for manufacturing an insulated gate field effect transistor having a gate provided on a channel region between sources with a gate insulating film interposed therebetween, comprising: forming a silicon oxide film on a p-type silicon substrate; Forming a niobium carbonitride film or a niobium nitride film on the oxide film; and forming the drain region and source region defining openings in the silicon oxide film and the niobium carbonitride film or the niobium nitride film. Introducing an n-type impurity to form the drain region and the source region; and removing the formed drain region and the source region from 800 ° C.
Annealing for a predetermined time in a temperature range up to 900 ° C .; etching the niobium carbonitride film or the niobium nitride film according to a predetermined pattern to form a part of the niobium carbonitride film or the niobium nitride film, A portion located between the drain region and the source region and a predetermined pattern portion continuous with the portion are left as a gate and a gate continuous portion continuous with the gate, respectively, and the remaining gate and the semiconductor substrate Using the oxide film portion located between the silicon oxide film, the drain region and the source region as a gate insulating film;
Forming a series of interlayer insulating films on each surface of the gate and the gate continuity; and opening a contact formation opening in the interlayer insulating film with respect to each of the drain and source regions and the gate continuity. Forming a series of a niobium carbonitride film or a niobium nitride film for forming a wiring on the surface of the interlayer insulating film and in each of the contact forming openings; Forming a wiring layer for the drain region, a wiring layer for the source region, and a wiring layer for the gate, respectively.