JPH07115191A - Diamond field effect transistor and its manufacture - Google Patents

Abstract

PURPOSE:To improve the performance of a diamond FET by a method wherein a diamond layer which has high impurity concentration doped surface parts and source and drain regions which are separated from each other with a certain distance and a gate composed of a silicon carbide layer are provided and the gate is placed on an active channel region. CONSTITUTION:A diamond layer 12 formed on a support substrate 13 has a drain region 16 and a source region 15 which are horizontally separated from each other and an active channel region 14 spread between the source region 15 and the drain region 16. The surface parts 15a and 16a of the source region 15 and the drain region 16 are doped with high concentration impurities. Further, contact layers 15b and 16b on the surface parts l5a and l5b are composed of double-layer structures of titanium and gold or titanium carbide and gold. A silicon carbide layer 17 which is to be the gate of an FET 10 is formed on the diamond layer 12 which is the surface layer on the active channel region 14 and, further, between the surface parts 15a and 16a. A conductive contact layer17a is formed on the silicon carbide layer 17.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION The present invention relates to semiconductor devices,
In particular, it relates to a field effect transistor containing semiconductor diamond and a method for manufacturing the same.

[0002]

2. Description of the Related Art A conventional diamond field effect transistor (F) manufactured using a semiconductor material such as silicon.
ET) is widely used in application fields from signal amplification and switching to realization of functions of logic circuits and storage circuits. FETs are widely used, for example, in digital integrated circuits because they are simpler to manufacture than bipolar transistors.

Since diamond has semiconductor characteristics superior to those of silicon, germanium or gallium arsenide, diamond is highly regarded as a material for many semiconductor devices such as FETs. Because diamond has a higher energy bandgap, higher withstand voltage and higher saturation rate than these conventional semiconductor materials.
The nature of these diamonds significantly increases the cutoff frequency and maximum operating voltage compared to devices fabricated using silicon, germanium and gallium arsenide.

Silicon cannot be used at temperatures above about 200 ° C. and gallium arsenide cannot be used at temperatures above about 300 ° C. This temperature limitation is due in part to the relatively small energy bandgap of silicon (1.12 eV at room temperature) and the energy bandgap of gallium arsenide (1.42 eV at room temperature). In comparison, diamond has a large bandgap of 5.47 eV at room temperature and is thermally stable up to a temperature of about 1400 ° C.

Diamond has a higher thermal conductivity than any solid at room temperature and good thermal conductivity over a wide temperature range. The high thermal conductivity of diamond increases the effectiveness of using diamond to remove heat dissipation in integrated circuits, especially as integration densities increase. In addition, diamond has a small neutron cross section that causes its deterioration in a radiation environment, and diamond is a so-called radiation-resistant material.

Due to the advantages of diamond as a material for semiconductor devices, its growth and its use as high temperature electronic devices and radiation tolerant electronic devices is currently of interest. Since FETs are the basic building blocks of today's integrated circuits, there is interest in the design and fabrication of diamond FETs. For example, a diamond metal semiconductor field effect transistor (MESFET) manufactured by using a rapid thermal processing (RTP) technique for implanting and activating boron in a type 2a diamond substrate is referred to as “a diamond using shallow RTP boron doping”. MES
Described in a paper entitled "FET" (Tsai et al.
IEEE Electron Device Letters, Vol 12, No.4, PP.157
-159 April 1991).

The MESFET has a gate electrode that forms a rectifying contact with the underlying semiconductor diamond layer. Tsai
Discloses the use of cubic boron as a thermal diffusion source for introducing boron as a p-type dopant in diamond using RTP technology at elevated temperatures of about 1400 ° C. However, industrially available processing chambers are typically operable up to temperatures of about 1200 ° C,
Processing at the high temperatures mentioned above exceeds the capacity of the chamber.
Furthermore, type 2a used in MESFETs such as Tsai
Diamonds contain nitrogen, which produces nitrogen donors,
Supplement the acceptor. This compensation phenomenon reduces the effectiveness of some of the boron dopants.

Another known diamond FET is the "manufacture of insulated gate diamond FETs for high temperature applications" (Hewett et al, International High Temperature E).
lectronics Conference in Albuquerque, NM, pp. 168-
173, June 1991). In this paper, an insulated gate FET having a boron-doped diamond channel region formed by uniformly doping a diamond layer by a plurality of ion implantation steps
(IGFET) is disclosed. Hewett et al. Is I
It suggests that by heavily doping the source and drain regions of the GFET, such as by performing additional ion implantation steps, a significant improvement in the specific contact resistance can be obtained. . However, since this ion implantation process needs to be performed at an extremely low temperature, that is, at about 77 ° K, the implantation process requires cooling with liquid nitrogen.

US Pat. No. 5,107,315 (issued April 21, 1992; inventor, Kumagai, etc .; assignee, applicant of the present application;
Title of the Invention "MIS having a diamond insulating layer as a lower layer
"Type diamond field effect transistor" discloses a metal insulator semiconductor FET (MISFET) having a diamond insulating layer between a polycrystalline diamond layer and a metal gate layer. Similarly, US patent USP 5,072,264 (Jone
s; the title of the invention "Diamond transistor and its manufacturing method") and U.S. Pat. No. 5,114,871 (Jones; "Manufacturing diamond electronic devices") are both MISF having an insulating layer between a diamond substrate and a metal gate layer.
Discloses ET. The insulating layer materials disclosed in the Jones patent are oxides, nitrides, nitrogen oxides or carbides.

A conventional FET is manufactured by repeating a photolithography mask process and an etching process. However, it is difficult to align the masks that are sequentially formed with high accuracy during the manufacture of the FET. Therefore,
Prior art tolerances and resolutions have limited the size of FETs. This limit also limits the performance of the device, such as the operating frequency range.

The aforementioned US Pat. No. 5,144,871 discloses a self-aligned technique in which the gate electrode acts as a mask for ion implantation of the source and drain regions. In addition, photoresist deposition and associated UV exposure through transparent diamond substrates has been used to fabricate source and drain electrodes.

The present invention has been made in view of the above problems, and has a low resistance ohmic contact for a source and a drain, and uses a conventional device to form a highly accurate source, gate and drain region. An object is to provide a diamond field effect transistor that can be formed and a method for manufacturing the same.

[0013]

A diamond field effect transistor (hereinafter also referred to as an FET) according to the present invention has a highly doped surface portion and has source and drain regions spaced from each other. And a gate having a silicon carbide layer associated with the active channel region, the gate overlying the active channel region to allow modulation of the channel region by applying a signal to the gate. Has been. This gate is preferably optically transparent so that the FET can be used in optoelectronic applications.

The diamond layer is preferably formed on the substrate and is single crystal or polycrystalline diamond. In the case of polycrystalline diamond, it is preferable to form an insulating layer between the silicon carbide layer and the active channel region. This insulating layer is preferably an optically transparent, insulating diamond that can operate at high temperatures.

The heavily doped source and drain surfaces provide low resistance ohmic contacts, which enables high power and / or high frequency operation of the FET. The concentration of the doping material at the surface of the heavily doped source and drain regions is preferably about 10 ²⁰ cm ^-3 or more.

The diamond FET of the present invention can be manufactured as follows. First, a channel region is formed in the diamond layer by performing ion implantation with boron many times. A silicon layer is deposited on the diamond layer. The silicon layer is patterned and etched by conventional photolithography techniques to form openings for ion implantation in the source and drain regions.

After high temperature treatment at about 1000 ° C., about 120
By the two-step heat treatment of high temperature treatment at 0 ° C., the silicon formed on the channel region is changed into silicon carbide to form a gate. In addition, the surface portions of the source and drain regions damaged by the implantation due to this heat treatment are graphitized. The graphitized surface can be chemically etched to expose the heavily doped surface for the source and drain. A metal contact layer can then be deposited on the heavily doped surface to form a low resistance contact.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A preferred embodiment of the present invention will now be described in detail with reference to the accompanying drawings. The present invention is not limited to this embodiment, and various modifications can be made. The following example descriptions are provided to fully disclose the present invention. In the figures, layer and region thicknesses have been exaggerated for clarity. Further, the same reference numerals indicate the same components.

First, referring to FIG. 1, an FET 10 according to an embodiment of the present invention preferably has a diamond layer 12 formed on a support substrate 13. Diamond layer 1
2 may be either single crystal diamond or polycrystalline diamond. In the embodiment shown in FIG. 1, diamond layer 12 is preferably single crystal diamond.
Therefore, the substrate 13 is preferably single crystal diamond, or is made of a material having a good lattice matching with diamond, and allows the single crystal diamond to be formed thereon. For example, the substrate 13 may be natural diamond having a crystal lattice relatively close to that of diamond, single crystal nickel or copper, or an alloy of nickel and copper. As those skilled in the art will readily appreciate, the substrate 13 is electrically conductive so that the diamond layer 12 may be insulating diamond or an intermediate layer of insulating diamond (not shown) may be diamond. It is preferably provided between the layer and the substrate.

The diamond layer 12 has a source region 15 laterally spaced from a drain region 16. Further, the diamond layer 12 includes the source region 15 and the drain region 1.
6 has an active channel region 14 extending between it and. The source region 15 and the drain region 16 each have heavily doped surface portions 15a and 16a for forming low resistance ohmic contacts in each region. It is desirable that the heavily doped surface portions 15a and 16a each have an impurity boron concentration of about 10 ²⁰ cm ^-3 or more. Each conductive contact layer 15b and 16b is preferably provided on the heavily doped surface portions 15a and 16a of the source and drain regions. Contact layer 15
b and 16b are preferably metals, for example, two layers of titanium and gold or two layers of titanium carbide and gold, which form ohmic contacts with diamond and can withstand operation at relatively high temperatures. There is a structure.

The silicon carbide layer 17 is the active channel region 1
4 on the surface diamond layer 12 on the upper surface of the surface layer 4 and the heavily doped source and drain surface portions 15a and 16a.
It is located between The silicon carbide layer 17 thus serves as the gate of the FET 10. Silicon carbide is FET1
It is desirable to be optically transparent to allow zero optical applications. Conductive contact layer 17a is preferably formed on silicon carbide layer 17 to enable electrical connection with silicon carbide layer 17. The metal contact layer 17a can be formed to have one or more openings (not shown) for optically coupling through the underlying optically transparent silicon carbide layer 17. Alternatively, a transparent conductive material such as indium tin oxide (ITO) can be used.

Next, the FET 20 according to the second embodiment of the present invention.
Will be described with reference to FIG. FET 20 includes components similar to those shown and described in the first embodiment of FIG. The same components are assigned the same reference numerals and detailed description thereof will be omitted. However, the FET of the second embodiment
20 is typically a non-diamond substrate 2 such as silicon
The diamond layer 21 formed on 2 is polycrystalline diamond. As will be readily appreciated by those skilled in the art, polycrystalline diamond on non-diamond substrates usually has cost advantages over single crystal diamond.

Due to the grain boundaries and defects in polycrystalline diamond, the metal layer on polycrystalline diamond does not readily form rectifying contacts. Therefore, in the embodiment of the FET 20 including polycrystalline diamond, the active channel region in the diamond layer 21 and the silicon carbide layer 1 are
It is desirable to provide the insulating layer 23 between the insulating layer 23 and the insulating layer 7. The insulating layer 23 is preferably insulating diamond, which is optically transparent and suitable for operation at high temperatures.

Next, a method of manufacturing the FET 10 of the embodiment shown in FIG. 1 will be described with reference to FIGS. The homoepitaxial diamond layer 12 is formed on the appropriate substrate 1
3 is deposited using conventional diamond film deposition methods such as high plasma chemical vapor deposition, as will be readily appreciated by those skilled in the art. The surface of diamond layer 12 is then polished by conventional chemical and / or mechanical methods.

Next, as shown in FIG. 3, boron is ion-implanted by a conventional technique into a part of the diamond layer 12,
An intermediate structure including the active channel region 14 is formed. The active channel region 14 can be formed by a plurality of ion implantation steps, preferably three steps, to obtain a desired doping concentration of 10 ¹⁶ cm ^{-3 to} 10 ¹⁹ cm ^-3 . As those skilled in the art can easily understand, when the substrate is a conductive substrate, it is preferable to form the insulating diamond layer between the diamond layer 12 and the substrate 13. On the other hand, the diamond layer 12 is made of insulating diamond, and the channel region 1 is formed in the insulating diamond.
4 and the source and drain regions 15 and 16 may be formed.

The implantation process for forming the active channel region 14 does not require cooling of liquid nitrogen and can be easily performed. Rather, the injection can be done at room temperature or slightly above room temperature. The active channel region 14 of the present invention can be formed without the need for elevated temperatures of about 1400 ° C. such as boron diffusion in solids. Such high temperatures exceed the limits of most conventional processing equipment.

As shown in FIG. 4, a polycrystalline or amorphous silicon layer 17 is deposited over the structure of FIG. Silicon can be deposited by conventional deposition techniques such as sputtering or chemical vapor deposition. Next, the silicon layer 17
Are patterned using conventional photolithography techniques to form a pair of laterally spaced openings 15c and 1c.
Etched to form 6c. This opening 1
5c and 16c serve as masks for the source and drain regions 15 and 16. In addition, sidewall spacers 19, such as SiO ₂ or Si ₃ N _4, are formed adjacent to the portion of the silicon layer defining the gate 17 to define masked source and drain regions 15 and 16. can do.

FIG. 6 shows the source region 15 and the drain region 1.
6 shows implantation of impurities. This impurity implantation is used as a self-aligned mask in order to obtain high accuracy in manufacturing the FET 10. One or more implantation steps are performed to obtain the desired impurity distribution. This ion implantation step can be performed without the need for cooling with liquid nitrogen.

During implantation of the source and drain regions 15, 16 their respective outer surface portions are damaged by the implantation. Therefore, the structure is preferably graphitized by heat treating the surface portions 15d and 16d of the source and drain regions in two steps at about 1000 ° C. and about 1200 ° C. to produce the structure shown in FIG. As a result, the silicon layer changes to silicon carbide. The graphitized surface portions 15d and 16d are made of CrO ₃ + H ₂ SO ₄
Of the heavily doped outer surface portions 15a, 16a of the source and drain regions having a high doping concentration of about 10 ²⁰ cm ^-3 or more can be exposed, such as by chemical etching using a hot solution of .

As described above, the two-step heat treatment changes the silicon layer into the silicon carbide layer 17. In addition, silicon carbide is resistant to the water soluble chemical etch used to remove the graphitized surface portions 15d, 16d. Next, contact layers 15b, 16b and 17a
Are formed on the source, drain and gate respectively to facilitate interconnection with the source, drain and gate.

Next, a method of manufacturing the FET 20 of the second embodiment shown in FIG. 2 will be described with reference to FIG. The polycrystalline diamond layer 21 is deposited on a suitable non-diamond substrate 22 using conventional deposition methods. This diamond layer 21 is then polished and an insulating layer 23, preferably insulating undoped diamond, is deposited on the diamond layer 21 over the portion that will become the active channel region 20 (see FIG. 2). After that, the remaining steps described with reference to FIGS. 3 to 7 are performed to manufacture the FET 20 of the embodiment shown in FIG.

FETs 10 and 20 according to an embodiment of the present invention
Are easily manufactured and have source and drain regions 15 and 1
It has 6 highly-doped surface portions 15a and 16a, and low-resistance ohmic junctions are obtained on the surface portions 15a and 16a, which can improve the performance of the FET and the output processing capability. Furthermore, the silicon carbide gate 17 is preferably optically transparent, which allows optical utilization of the FET. Also, FETs are easily manufactured with high precision using a self-aligned process, and can be manufactured using commonly available equipment.

As will be apparent from the above description, the silicon carbide gate and other features of the present invention can be easily applied to a vertical FET in which the active channel region extends in the vertical direction through the diamond layer. it can.
Therefore, the present invention is not limited to the above embodiments, and various modifications can be made within the scope of the present invention based on the description of the claims of the present invention.

[0034]

As described above, according to the present invention,
Having low resistance ohmic contacts for the source and drain, conventional devices can be used to form high precision source, gate and drain regions.

[Brief description of drawings]

FIG. 1 is a first single crystal diamond FET according to the present invention.
It is sectional drawing which shows the Example of.

FIG. 2 is a cross-sectional view showing a second embodiment of the polycrystalline diamond FET according to the present invention which has an insulating layer under the gate.

FIG. 3 is a cross-sectional view showing an intermediate stage in the manufacturing process of the single crystal diamond FET shown in FIG.

FIG. 4 is a cross-sectional view showing an intermediate stage in the manufacturing process of the single crystal diamond FET shown in FIG.

5 is a cross-sectional view showing an intermediate stage in the manufacturing process of the single crystal diamond FET shown in FIG.

FIG. 6 is a cross-sectional view showing an intermediate stage in the manufacturing process of the single crystal diamond FET shown in FIG.

FIG. 7 is a cross-sectional view showing an intermediate stage in the manufacturing process of the single crystal diamond FET shown in FIG.

FIG. 8 is a cross-sectional view showing an intermediate stage in the manufacturing process of the polycrystalline diamond FET shown in FIG.

[Explanation of symbols]

 FETs 12, 21; Diamond layer 13; Substrate 14; Active channel region 15; Source regions 15a, 16a; Surface portions 15b, 16b, 17a; Conductive contact layer 16; Drain region 17; Silicon carbide layer 22; Non-diamond substrate 23; insulating layer

Claims (27)

[Claims] 1. A source and drain region laterally spaced apart and an active channel region therebetween, the source and drain regions having a heavily doped surface portion for forming a low resistance ohmic contact. Silicon carbide provided on the diamond layer between the diamond layer having and the heavily doped surface portions of the source region and the drain region and overlapping the active channel region to enable modulation of the active channel region. A diamond field effect transistor having a gate formed of layers. 2. The diamond field effect transistor according to claim 1, wherein the gate is optically transparent. 3. The heavily doped surface portions of the source region and the drain region each have an impurity doping concentration of 10 ²⁰ cm ⁻³ or more.
The diamond field effect transistor described in. 4. The diamond field effect transistor according to claim 1, wherein the diamond layer is single crystal diamond. 5. The diamond field effect transistor according to claim 1, wherein the diamond layer is polycrystalline diamond. 6. The diamond field effect transistor according to claim 5, wherein the gate further has an insulating layer provided between the diamond layer and the silicon carbide layer. 7. The diamond field effect transistor according to claim 6, wherein the insulating layer is an insulating diamond. 8. The diamond field effect transistor of claim 1, further comprising a substrate on the diamond layer opposite the gate. 9. A diamond layer having laterally spaced source and drain regions and an active channel region between them, and a modulation layer provided on the diamond layer corresponding to the active channel region. Field effect transistor having a gate made of silicon carbide 10. The diamond field effect transistor according to claim 9, wherein the gate is optically transparent. 11. The diamond field effect transistor of claim 10, wherein the source region and the drain region have heavily doped surface portions for forming ohmic contacts therein. 12. The heavily doped surface portions of the source region and the drain region are each 10 ²⁰ cm ^−3.
The diamond field effect transistor according to claim 11, which has the above impurity doping concentration. 13. The diamond field effect transistor according to claim 9, wherein the diamond layer is single crystal diamond. 14. The diamond field effect transistor according to claim 9, wherein the diamond layer is polycrystalline diamond. 15. The diamond field effect transistor of claim 14, wherein the gate further comprises an insulating layer between the polycrystalline diamond layer and the gate. 16. The diamond field effect transistor according to claim 15, wherein the insulating layer is an insulating diamond. 17. The diamond field effect transistor of claim 9, further comprising a substrate on the diamond layer opposite the gate. 18. A step of forming a source region and a drain region, and an active channel region between the source region and the drain region in a diamond layer, and the active channel region provided corresponding to the active channel region of the diamond layer. A step of forming a gate made of a silicon carbide layer for modulating a channel region, the method for manufacturing a diamond field effect transistor. 19. The method of manufacturing a diamond field effect transistor according to claim 18, wherein the step of forming the active channel region includes a step of ion-implanting a predetermined portion of the diamond layer once or plural times. . 20. The method for manufacturing a diamond field effect transistor according to claim 18, further comprising the step of heavily doping the surface portions of the source region and the drain region. 21. The step of heavily doping the surface portions of the source region and the drain region is a step of ion-implanting a predetermined portion of the diamond layer once or a plurality of times, and the obtained structure is annealed. And a step of graphitizing a surface portion of the drain region, and a step of removing the graphitized surface portion of the source region and the drain region to expose each heavily doped surface portion of the source region and the drain region. 3. The method according to claim 2, wherein
0. A method for manufacturing a diamond field effect transistor according to 0. 22. The step of masking an active channel region by patterning a silicon layer on a diamond layer prior to the step of forming the source region and the drain region. A method for manufacturing the diamond field effect transistor described. 23. The diamond field effect transistor according to claim 22, further comprising a step of annealing the obtained structure to change a part of the patterned silicon layer into a gate made of a silicon carbide layer. Manufacturing method. 24. The diamond electric field according to claim 18, wherein the diamond layer is polycrystalline diamond, and further comprising the step of forming an insulating layer between the polycrystalline diamond layer and the silicon carbide layer. Effect transistor manufacturing method. 25. A step of selectively ion implanting a diamond layer to form an active channel region, and a patterned silicon layer having openings for source and drain regions on the active channel region in the diamond layer. A step of forming, a step of ion-implanting a source region and a drain region into the diamond layer while selectively masking the diamond layer with the patterned silicon layer, and heat treatment to form a silicon carbide gate from the silicon layer. And a step of graphitizing the surface portions of the source and drain regions, and a step of removing the graphitized surface portions of the source region and the drain region to expose the heavily doped surface portions. Method for manufacturing diamond field effect transistor. 26. The method for manufacturing a diamond field effect transistor according to claim 25, further comprising the step of forming a spacer portion adjacent to the silicon layer and masking the active channel region of the diamond layer. 27. The method according to claim 25, wherein the diamond layer is polycrystalline diamond, and further comprising the step of forming an insulating layer between the polycrystalline diamond layer and the silicon carbide layer. Manufacturing method of diamond field effect transistor.