JPS5867045A - Cryogenic semiconductor device and its manufacture - Google Patents
Cryogenic semiconductor device and its manufactureInfo
- Publication number
- JPS5867045A JPS5867045A JP56165685A JP16568581A JPS5867045A JP S5867045 A JPS5867045 A JP S5867045A JP 56165685 A JP56165685 A JP 56165685A JP 16568581 A JP16568581 A JP 16568581A JP S5867045 A JPS5867045 A JP S5867045A
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- molybdenum
- resist
- film
- gate electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53285—Conductive materials containing superconducting materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
- H01L21/76891—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances by using superconducting materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Abstract
Description
【発明の詳細な説明】
本発明は超伝導電極配線を用いた極低温用半導体装置お
よびその製造法、さらに詳細には窒化モリブデンを超伝
導体として用いた極低温用半導体装置およびその製造方
法に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a cryogenic semiconductor device using superconducting electrode wiring and a manufacturing method thereof, and more particularly to a cryogenic semiconductor device using molybdenum nitride as a superconductor and a manufacturing method thereof. .
従来の半導体素子を用いた集積回路において電極配線は
、モ°↓ブデン、タングステン、クロム、タンタル、ア
ルミニウム等の金属単体、あるいはシリコン等の半導体
またはタングステンシリサイド、モリブデンシダサイド
等の金属間化合物を用いている。またこれらの材料がオ
ーム抵抗性を示す条件で使用している。そのため電極配
線は有限のオーム抵抗を有する。半導体集積回路の規模
が小さく、かつ配線のパターン幅がＩｐｍ以上と比較的
幅が広い場合紘それでも特に間亀は生じなかった。しか
し近年半導体集積回路の進歩拡著しく、ＭＯ８メモリを
例に取るならば、その集積度は３年に４倍という速度で
進展しておシ、２０世紀末までに１チツプ当シの集積度
祉メモリで２Ｘ１０ビツト、論理回路で２〜３Ｘ１０’
ゲート規模になると予想される。それにともない電極配
線の総配線長および表子間の平均配線長線、ともに飛躍
的に増大する。例えば、現在のチップの大きさが数語角
の回路規模１〜２ｘゲートのバイポーラＬ８工において
もすでに総配線長は４．０ｍにも達している。このため
１チツプ尚シの回路規模窄増大し複雑化するに従って配
線による遅延が増大し、半導体集積回路の性能に訃よ埋
すその影養は無視できなくなる。このように今後半導体
集積回路のよシ一層の大規模化、高密度化が進むと配線
遅延時間は集積回路の性能を決定する重要な因子となる
。さらに微細化が進むと、比例縮小則によれば、単位長
さ当りの抵抗は縮小率の逆数の２乗に比例して増大する
。′この２と社遅延を増大させるのみならず、電源配線
上での大きな電圧降下をもたらし集積回路を設計する上
で大きな制約となる。さらに微細化による配線の断面積
の減少は電流密度を増大させ、それによってエレクトロ
マイグレーションに起因する信頼性の低下を引き起す。In integrated circuits using conventional semiconductor elements, electrode wiring uses simple metals such as mobdenum, tungsten, chromium, tantalum, and aluminum, semiconductors such as silicon, or intermetallic compounds such as tungsten silicide and molybdenum cider. ing. Furthermore, these materials are used under conditions that exhibit ohmic resistance. Therefore, the electrode wiring has a finite ohmic resistance. Even when the scale of the semiconductor integrated circuit is small and the wiring pattern width is relatively wide, such as Ipm or more, no particular gap occurs. However, as semiconductor integrated circuits have progressed in recent years, the density of MO8 memory, for example, has increased four times every three years. 2x10 bits, 2~3x10' in logic circuits
It is expected to be on a gate scale. Accordingly, both the total wiring length of the electrode wiring and the average wiring length line between the front electrodes increase dramatically. For example, even in the current bipolar L8 circuit with a circuit scale of 1 to 2x gates whose chip size is several words square, the total wiring length has already reached 4.0 m. For this reason, as the circuit size of a single chip increases and becomes more complex, the delay due to wiring increases, and its impact on the performance of semiconductor integrated circuits cannot be ignored. As described above, as semiconductor integrated circuits become larger and more dense in the future, interconnect delay time will become an important factor in determining the performance of integrated circuits. As miniaturization progresses further, according to the proportional reduction law, the resistance per unit length increases in proportion to the square of the reciprocal of the reduction rate. 'The second problem not only increases the delay, but also causes a large voltage drop on the power supply wiring, which is a major constraint in designing integrated circuits. Furthermore, the reduction in the cross-sectional area of interconnects due to miniaturization increases current density, thereby causing a decrease in reliability due to electromigration.
ところで上記の微細化、大規模化、高密度化にともなっ
て生じる半導体集積回路の電極配線に関する問題は電極
配線を超伝導化することによって一挙に解決することが
できる。今までのところ超伝導配線はジョセフソン素子
を用いた集積回路でのみ実現されておシ半導体集積回路
上では実現されていない。しかして、その材料としては
鉛−金あるいは鉛−全一ビスマスあるいは鉛−インジウ
ムー金等の鉛系の超伝導材料あるいはニオブあるいはニ
オブの化合物等の超伝導材料が使用されてフトオ７技術
を用いることによって形成される。By the way, the problems related to the electrode wiring of semiconductor integrated circuits that arise due to miniaturization, larger scale, and higher density can be solved all at once by making the electrode wiring superconducting. So far, superconducting interconnects have only been realized in integrated circuits using Josephson elements, and not on semiconductor integrated circuits. Therefore, as the material, a lead-based superconducting material such as lead-gold, lead-all-bismuth or lead-indium-gold, or a superconducting material such as niobium or a niobium compound is used, and Futo7 technology is used. formed by.
しかしながらす７トオフエ程は信頼性に乏しく、微細か
つ大規模な集積回路の電極配線パターンを形成するのに
不向きである。また鉛系の超伝導材料は耐熱性にも乏し
〈従来の半導体集積回路製造工程に導入することは困難
である。一方二オブ系の超伝導材料も半導体集積回路製
造工程に導入するためには、コンタクト抵抗、応力の間
鵬、基板に対する密着性、あるいは微細加工性さらには
、ＭＯ８素子のゲート電極配線に使用した場合の汚染と
蒸着時のダメージという点で未解決の間組が多い。した
がってジョセフソン素子を用いた集積回路で使用されて
いるこれらの材料を用いて製造工程が全く異なシ、かつ
極めて微細な半導体集積回路上に超伝導電極配線を実現
するためには多くの検討を要し、多くの困難があった。However, the step-off process has poor reliability and is not suitable for forming electrode wiring patterns of fine and large-scale integrated circuits. Furthermore, lead-based superconducting materials have poor heat resistance and are difficult to introduce into conventional semiconductor integrated circuit manufacturing processes. On the other hand, in order to introduce niobium-based superconducting materials into the semiconductor integrated circuit manufacturing process, it is necessary to improve contact resistance, stress tolerance, adhesion to the substrate, microfabrication ability, and even the gate electrode wiring of MO8 devices. There are many unresolved problems in terms of contamination and damage during deposition. Therefore, in order to realize superconducting electrode interconnects on extremely fine semiconductor integrated circuits using these materials used in integrated circuits using Josephson devices, the manufacturing process is completely different, and many studies are required. It took a long time, and there were many difficulties.
本発明は半導体集積回路の電極配線を従来使用されてき
た常伝導材料の代シｋ、超伝導材料であるモリブデンの
窒化物を使用することを特徴とし、その目的は配線抵抗
に起因する上記欠点を除去し、かつ従来の半導体集積回
路製造技術と親和性の良い半導体装置に用いる超伝導電
極配線製造技術を提供するにある。The present invention is characterized in that molybdenum nitride, which is a superconducting material, is used instead of the conventionally used normal conductive material for the electrode wiring of a semiconductor integrated circuit, and its purpose is to eliminate the above-mentioned drawbacks caused by wiring resistance. It is an object of the present invention to provide a superconducting electrode wiring manufacturing technology for use in a semiconductor device, which eliminates the problem and has good compatibility with conventional semiconductor integrated circuit manufacturing technology.
モリブデンと窒素の化合物、特にＭｏＮとＭＯ！Ｎはそ
れぞれ１２＠にと５″にの超伝導転移温度を有し、これ
らのモリブデン化合物からなる薄膜は、モリブデン薄膜
を水素と窒素の混合ガス中で窒素と反応させることによ
シ容易に得ることができる。そのための窒化条件は水素
ガスと窒素ガスの流量比Ｈ，／Ｎ、：０．０１〜１０．
０ 、好ましくはＩＩｌ、／１１． ： ０．１〜１．
０．窒化温度４０−〇＠Ｃ〜９００＠Ｃ好ましくは５５
０℃〜ｓｏｏ＠ｃ 、窒化時間５〜６０分の範囲の中か
ら選ぶことができる。このようにモリブデンと窒素の化
合物からなる薄膜がモリブデン薄膜から容易に得ること
ができるために、モリブデンと窒素の化合物からなる電
極配線製造技術として従来からあるモリブデン電極配線
技術をそのまま利用することができる。このことはモリ
ブデンと窒素の化合物からなる超伝導配線の製造技術が
従来の半導体集積回路製造技術と極めて親和性の高い技
術であることを保障するものである。Compounds of molybdenum and nitrogen, especially MoN and MO! N has a superconducting transition temperature of 12@ and 5'', respectively, and thin films of these molybdenum compounds can be easily obtained by reacting molybdenum thin films with nitrogen in a mixed gas of hydrogen and nitrogen. The nitriding conditions for this are a hydrogen gas to nitrogen gas flow ratio H,/N: 0.01 to 10.
0, preferably IIl, /11. : 0.1~1.
0. Nitriding temperature 40-〇@C to 900@C preferably 55
The temperature can be selected from the range of 0° C. to soo@c and the nitriding time of 5 to 60 minutes. Since a thin film made of a compound of molybdenum and nitrogen can be easily obtained from a thin molybdenum film, the conventional molybdenum electrode wiring technology can be used as is for manufacturing electrode wiring made of a compound of molybdenum and nitrogen. . This ensures that the technology for manufacturing superconducting wiring made of a compound of molybdenum and nitrogen is highly compatible with conventional semiconductor integrated circuit manufacturing technology.
以下、実施例によシさらに詳しく本発明を説明する。Hereinafter, the present invention will be explained in more detail with reference to Examples.
〔第１の実施例〕
第１図（ＩＬ） Ｋ示すごと〈従来の半導体集積回路製
造技術によ）半導体基板２上に半導体素子領域１′およ
び素子間分離領域ｌを形成する。第１図において祉牛導
体素子製造工程としてＭＯＥｉＦＩＴを例として示しで
あるが、もちろん他の半導体素子、例えばＭ］ｅ８７Ｉ
Ｔ等であってもかまわない。次に電子ビーム加熱蒸着法
によって厚さ０．３μｍのモリブデン薄膜３を形成する
（第１図（ｂ））。そして電子ビームを用いたシソグラ
フィ技術にょルゲート電極のレジストパターン４を形成
゛する。使用したレジストはネガ型電子線レジストであ
るクロルメチル化ポリスチレン（ＣＭＢ ）である。こ
のレジストパターンをマスクとして平行平板電極型ドラ
イエツチング装置によ）モリブデン薄膜をサイドエツチ
ング無しに加工し、ゲート電極５を形成する（第１図（
Ｃ））。然るのちレジストを除去し、水素と窒素の流量
比Ｈ，／Ｎ、 ＝ ０．１ 、温度ｊ）Ｏ＠Ｏの雰囲気
中で３０分間の熱処理を行ない、モリブデンの窒化を行
なう。以上の工程によりＭｏ、Ｍからなる超伝導ゲート
電極配線５′が得られる（第１図（ｄ））。得られたゲ
ート電極５′をマスクとして砒素イオン打ち込みを行な
いソースとドレイン６を形成する。次にＯ’ＶＤ法によ
ｆｉ ＩＪン添加酸化膜７を堆積し、ポジ型しジメ）
ＰＰＭを使用した電子ビーム直接描画法によって、スル
ーホールパターンを形成する。そして平行平板形のドラ
イエツチング装置によりサイドエツチングを生じさせず
にリン添加酸化膜を加工しスルーホールを形成する。Ｉ
ＦＰＭレジストを除去した後、モリブデン８を電子ビー
ム加熱法忙よって０．３μ蒸着する（第１図（ｅ））。[First Embodiment] As shown in FIG. 1 (IL) K, a semiconductor element region 1' and an inter-element isolation region l are formed on a semiconductor substrate 2 (by conventional semiconductor integrated circuit manufacturing technology). In FIG. 1, MOEiFIT is shown as an example of the process for manufacturing a cattle conductor element, but of course other semiconductor elements, such as M]e87I
It does not matter if it is T, etc. Next, a molybdenum thin film 3 having a thickness of 0.3 μm is formed by electron beam heating vapor deposition (FIG. 1(b)). Then, a resist pattern 4 of a gate electrode is formed using a lithography technique using an electron beam. The resist used was chloromethylated polystyrene (CMB), which is a negative electron beam resist. Using this resist pattern as a mask, the molybdenum thin film is processed without side etching using a parallel plate electrode type dry etching device to form a gate electrode 5 (see Fig. 1).
C)). Thereafter, the resist is removed, and a heat treatment is performed for 30 minutes in an atmosphere of hydrogen to nitrogen flow ratio H,/N = 0.1 and temperature j)O@O to nitride molybdenum. Through the above steps, a superconducting gate electrode wiring 5' made of Mo and M is obtained (FIG. 1(d)). Using the obtained gate electrode 5' as a mask, arsenic ions are implanted to form a source and a drain 6. Next, a fi IJ-added oxide film 7 is deposited by the O'VD method and made into a positive type.
A through-hole pattern is formed by an electron beam direct writing method using PPM. Then, the phosphorus-doped oxide film is processed using a parallel plate type dry etching device to form through holes without causing side etching. I
After removing the FPM resist, 0.3 μm of molybdenum 8 is deposited by electron beam heating (FIG. 1(e)).
然るのち、ＣＭＢレジストを用いた電子ビーム直接描画
法によって電極配線レジストパターン９を形成し、レジ
ストパターンをマスクとして反応性スパッタエツチング
によってモリブデン薄膜１０をサイドエツチング無しに
エツチングする。（第１図（ｆ））最後にレジストを除
去し、前記窒化条件でモリブデンを窒化し、窒化モリブ
デンからなる超伝導配線１０′を形成する（第１図−）
。これによシ超伝導電極配線を用いた半導体装置として
動作させることができる。Thereafter, an electrode wiring resist pattern 9 is formed by electron beam direct writing using a CMB resist, and using the resist pattern as a mask, the molybdenum thin film 10 is etched by reactive sputter etching without side etching. (Fig. 1(f)) Finally, the resist is removed, and molybdenum is nitrided under the above nitriding conditions to form superconducting wiring 10' made of molybdenum nitride (Fig. 1-)
. This allows the device to operate as a semiconductor device using superconducting electrode wiring.
〔第２の実施例〕
ゲート電極用モリブデン薄膜を形成する工程までは第１
の実施例と全く同様である（第２図（ｂ））。[Second Example] The steps up to the step of forming the molybdenum thin film for the gate electrode are as follows.
This is exactly the same as the embodiment (FIG. 2(b)).
然るのち水素と窒素の流量比ｇ、／ａ！＝ｏ、ｔ 、温
度ｓｓｏ＠ｃの雰囲気中で３０分間の熱処理を行ないモ
リブデン３の窒化を行なう。その後電子ビーム直接描両
法によ）幅１μｍのゲート電極配線用レジストパターン
４を形成する。使用したレジストはネガ型のり胃ルメチ
ル化ポリスチレン（ｃｎｓ ）である。このレジストパ
ターン４をマスクにして窒化モリブデン薄Ｍ５を平行平
板型のドライエツチング装置を用いた反応性スパッタエ
ツチングによってサイドエツチングを生じさせることな
しに加工する（第２図（Ｃ））。レジストを除去し、望
みの窒化モリブデンからなる超伝導ゲート電極配線５′
を得る（第２図（ｄ））。その後実施例そのｌと同様の
工程を経てスルーホールを形成する。然るのち膜厚０４
３μｍのモリブデン薄膜８を形成し、前記窒化条件で窒
化を行なう（第２図（ｅ））。その後ＯＭＢレジストを
用いた電子ビーム直接描画法によシミ極配線パターン９
を形成し、レジストをマスクとして窒化モリブデン薄膜
ｌＯを反応性スパッタエツチングによシサイドエッチン
グ無しに加工する（第２図（ｆ））。最後にレジストを
除去し、窒化モリブデンからなる超伝導配線１０を得る
（第２図（ω）。After that, the flow rate ratio of hydrogen and nitrogen g, /a! A heat treatment is performed for 30 minutes in an atmosphere at a temperature of sso@c and a temperature of sso@c to nitride molybdenum 3. Thereafter, a resist pattern 4 for gate electrode wiring having a width of 1 μm is formed using an electron beam direct writing method. The resist used was negative tone methylated polystyrene (CNS). Using this resist pattern 4 as a mask, the thin molybdenum nitride M5 is processed by reactive sputter etching using a parallel plate type dry etching apparatus without causing side etching (FIG. 2(C)). The resist is removed and the desired superconducting gate electrode wiring 5' made of molybdenum nitride is formed.
(Figure 2(d)). Thereafter, through-holes are formed through the same steps as in Example 1. After that, film thickness 04
A 3 μm thick molybdenum thin film 8 is formed and nitrided under the above-mentioned nitriding conditions (FIG. 2(e)). After that, the stain electrode wiring pattern 9 was formed using the electron beam direct writing method using OMB resist.
A thin molybdenum nitride film 10 is processed by reactive sputter etching using the resist as a mask without side etching (FIG. 2(f)). Finally, the resist is removed to obtain superconducting wiring 10 made of molybdenum nitride (FIG. 2 (ω)).
これによシ超伝導電極配線を用いた半導体装置として動
作させることができる。This allows the device to operate as a semiconductor device using superconducting electrode wiring.
以上説明したように、本発明によれば半導体集積回路の
電極配線を超伝導配線化することによって、今後の大規
模化、高密度化そして微細化にと本ない重大化する種々
の問題すなわち配線長と配線抵抗の増大にともなう配線
遅延と電圧降下の増大、そして電流密度の増加にともな
うエレクトロマイグレーションの増大による信頼性の低
下等の問題を一挙に解決することができる。そして、本
発明の様に超伝導配線材料としてモリブデンの窒化物を
採用することは、モリプデシの窒化という技術を使用す
ることＫよって、上記の利点を有する超伝導配線を従来
の半導体集積回路製造技術に大きな変更を加えることな
しに、極めて容易に実現できることである。このことは
半導体集積回路製造技術の分野において、従来の技術と
の親和性がＪｉＬｂということは大きな利点を有するも
のである。As explained above, according to the present invention, by making the electrode wiring of a semiconductor integrated circuit into a superconducting wiring, various problems that will become serious due to future enlargement, high density, and miniaturization, such as wiring. Problems such as increased wiring delay and voltage drop due to increased wiring length and increased wiring resistance, and decreased reliability due to increased electromigration due to increased current density can be solved all at once. The use of molybdenum nitride as a superconducting wiring material as in the present invention is achieved by using a technology called molybdenum nitridation.Therefore, superconducting wiring having the above-mentioned advantages can be fabricated using conventional semiconductor integrated circuit manufacturing techniques. This can be achieved extremely easily without making any major changes. This means that in the field of semiconductor integrated circuit manufacturing technology, JiLb's compatibility with conventional technology has a great advantage.
第１図および第２図拡超伝導配線を使用した半導体集積
回路の製造工程を示したものである。第１図（ａ） 〜
（ｇ）は第１実施例の場合、第２図（ａ） 〜（ｇ）は
第２実施例の場合である。FIGS. 1 and 2 show the manufacturing process of a semiconductor integrated circuit using expanded superconducting wiring. Figure 1(a) ~
(g) shows the case of the first embodiment, and FIGS. 2(a) to (g) show the case of the second embodiment.
Claims (2)
ことを特徴とする極低温用半導体装置。(1) A cryogenic semiconductor device characterized by having superconducting electrode wiring made of molybdenum nitride.
、前記の薄膜にパターンを形成する工程と、前記モリブ
デンを水門と窒素の混合ガス中で熱処理を行なうことに
よって窒化する工程を含むことを特徴とする極低温用半
導体装置の製造方法。(2) The method includes the steps of forming a molybdenum thin film on a semiconductor substrate, forming a pattern on the thin film, and nitriding the molybdenum by heat-treating the molybdenum in a mixed gas of sluice and nitrogen. A method for manufacturing a semiconductor device for cryogenic temperatures.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56165685A JPS5867045A (en) | 1981-10-19 | 1981-10-19 | Cryogenic semiconductor device and its manufacture |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56165685A JPS5867045A (en) | 1981-10-19 | 1981-10-19 | Cryogenic semiconductor device and its manufacture |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5867045A true JPS5867045A (en) | 1983-04-21 |
Family
ID=15817089
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56165685A Pending JPS5867045A (en) | 1981-10-19 | 1981-10-19 | Cryogenic semiconductor device and its manufacture |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5867045A (en) |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60154613A (en) * | 1984-01-25 | 1985-08-14 | Hitachi Ltd | Semiconductor device for ultra-low temperature |
| EP0282012A2 (en) * | 1987-03-09 | 1988-09-14 | Semiconductor Energy Laboratory Co., Ltd. | Superconducting semiconductor device |
| DE3810494A1 (en) * | 1987-03-27 | 1988-10-27 | Hitachi Ltd | Integrated semiconductor circuit arrangement having a superconducting layer, and method for producing it |
| JPS63261745A (en) * | 1987-04-20 | 1988-10-28 | Hitachi Ltd | Semiconductor device |
| JPS63300537A (en) * | 1987-05-29 | 1988-12-07 | Nec Corp | Semiconductor device |
| JPS6461931A (en) * | 1987-09-02 | 1989-03-08 | Toshiba Corp | Semiconductor device |
| JPH01119084A (en) * | 1987-10-30 | 1989-05-11 | Nec Corp | Integrated semiconductor light emitting device |
| JPH02322A (en) * | 1987-11-16 | 1990-01-05 | Semiconductor Energy Lab Co Ltd | Manufacture of superconducting device |
| JPH07263765A (en) * | 1994-03-24 | 1995-10-13 | Agency Of Ind Science & Technol | Insulating gate field effect transistor, production thereof, and integrated circuit device of insulating gate field effect transistor |
-
1981
- 1981-10-19 JP JP56165685A patent/JPS5867045A/en active Pending
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60154613A (en) * | 1984-01-25 | 1985-08-14 | Hitachi Ltd | Semiconductor device for ultra-low temperature |
| EP0282012A2 (en) * | 1987-03-09 | 1988-09-14 | Semiconductor Energy Laboratory Co., Ltd. | Superconducting semiconductor device |
| DE3810494A1 (en) * | 1987-03-27 | 1988-10-27 | Hitachi Ltd | Integrated semiconductor circuit arrangement having a superconducting layer, and method for producing it |
| DE3810494C2 (en) * | 1987-03-27 | 1998-08-20 | Hitachi Ltd | Integrated semiconductor circuit device with superconducting layer |
| JPS63261745A (en) * | 1987-04-20 | 1988-10-28 | Hitachi Ltd | Semiconductor device |
| JPS63300537A (en) * | 1987-05-29 | 1988-12-07 | Nec Corp | Semiconductor device |
| JPS6461931A (en) * | 1987-09-02 | 1989-03-08 | Toshiba Corp | Semiconductor device |
| JPH01119084A (en) * | 1987-10-30 | 1989-05-11 | Nec Corp | Integrated semiconductor light emitting device |
| JPH02322A (en) * | 1987-11-16 | 1990-01-05 | Semiconductor Energy Lab Co Ltd | Manufacture of superconducting device |
| JPH07263765A (en) * | 1994-03-24 | 1995-10-13 | Agency Of Ind Science & Technol | Insulating gate field effect transistor, production thereof, and integrated circuit device of insulating gate field effect transistor |
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