JPS6142989B2 - - Google Patents

Info

Publication number
JPS6142989B2
JPS6142989B2 JP55057649A JP5764980A JPS6142989B2 JP S6142989 B2 JPS6142989 B2 JP S6142989B2 JP 55057649 A JP55057649 A JP 55057649A JP 5764980 A JP5764980 A JP 5764980A JP S6142989 B2 JPS6142989 B2 JP S6142989B2
Authority
JP
Japan
Prior art keywords
bit
data
line
circuit
fractional
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP55057649A
Other languages
English (en)
Japanese (ja)
Other versions
JPS56154852A (en
Inventor
Toshuki Odakawa
Yasuo Doi
Hideki Yamanaka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP5764980A priority Critical patent/JPS56154852A/ja
Publication of JPS56154852A publication Critical patent/JPS56154852A/ja
Publication of JPS6142989B2 publication Critical patent/JPS6142989B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/0078—Avoidance of errors by organising the transmitted data in a format specifically designed to deal with errors, e.g. location
    • H04L1/0083—Formatting with frames or packets; Protocol or part of protocol for error control

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Communication Control (AREA)
JP5764980A 1980-04-30 1980-04-30 Fractional bit control circuit of communication controller on high-level procedure system Granted JPS56154852A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5764980A JPS56154852A (en) 1980-04-30 1980-04-30 Fractional bit control circuit of communication controller on high-level procedure system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5764980A JPS56154852A (en) 1980-04-30 1980-04-30 Fractional bit control circuit of communication controller on high-level procedure system

Publications (2)

Publication Number Publication Date
JPS56154852A JPS56154852A (en) 1981-11-30
JPS6142989B2 true JPS6142989B2 (enExample) 1986-09-25

Family

ID=13061742

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5764980A Granted JPS56154852A (en) 1980-04-30 1980-04-30 Fractional bit control circuit of communication controller on high-level procedure system

Country Status (1)

Country Link
JP (1) JPS56154852A (enExample)

Also Published As

Publication number Publication date
JPS56154852A (en) 1981-11-30

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