JPS6142865B2 - - Google Patents
Info
- Publication number
- JPS6142865B2 JPS6142865B2 JP54073181A JP7318179A JPS6142865B2 JP S6142865 B2 JPS6142865 B2 JP S6142865B2 JP 54073181 A JP54073181 A JP 54073181A JP 7318179 A JP7318179 A JP 7318179A JP S6142865 B2 JPS6142865 B2 JP S6142865B2
- Authority
- JP
- Japan
- Prior art keywords
- chip carrier
- wiring board
- hole
- semiconductor element
- refrigerant
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/46—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements involving the transfer of heat by flowing fluids
- H01L23/473—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements involving the transfer of heat by flowing fluids by flowing liquids
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7318179A JPS55165659A (en) | 1979-06-11 | 1979-06-11 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7318179A JPS55165659A (en) | 1979-06-11 | 1979-06-11 | Semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS55165659A JPS55165659A (en) | 1980-12-24 |
JPS6142865B2 true JPS6142865B2 (enrdf_load_stackoverflow) | 1986-09-24 |
Family
ID=13510705
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP7318179A Granted JPS55165659A (en) | 1979-06-11 | 1979-06-11 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS55165659A (enrdf_load_stackoverflow) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5349498A (en) * | 1992-12-23 | 1994-09-20 | Hughes Aircraft Company | Integral extended surface cooling of power modules |
CN107316852B (zh) * | 2017-08-08 | 2019-09-27 | 苏州能讯高能半导体有限公司 | 一种半导体器件的散热结构及半导体器件 |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5599752A (en) * | 1979-01-25 | 1980-07-30 | Chiyou Lsi Gijutsu Kenkyu Kumiai | Structure for fitting ic chip |
-
1979
- 1979-06-11 JP JP7318179A patent/JPS55165659A/ja active Granted
Also Published As
Publication number | Publication date |
---|---|
JPS55165659A (en) | 1980-12-24 |
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