JPS6141176B2 - - Google Patents
Info
- Publication number
- JPS6141176B2 JPS6141176B2 JP55127156A JP12715680A JPS6141176B2 JP S6141176 B2 JPS6141176 B2 JP S6141176B2 JP 55127156 A JP55127156 A JP 55127156A JP 12715680 A JP12715680 A JP 12715680A JP S6141176 B2 JPS6141176 B2 JP S6141176B2
- Authority
- JP
- Japan
- Prior art keywords
- decoder
- input
- gate
- gates
- transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Compression, Expansion, Code Conversion, And Decoders (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12715680A JPS5753882A (ja) | 1980-09-16 | 1980-09-16 | Dekoodakairo |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12715680A JPS5753882A (ja) | 1980-09-16 | 1980-09-16 | Dekoodakairo |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5753882A JPS5753882A (ja) | 1982-03-31 |
| JPS6141176B2 true JPS6141176B2 (enExample) | 1986-09-12 |
Family
ID=14953013
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12715680A Granted JPS5753882A (ja) | 1980-09-16 | 1980-09-16 | Dekoodakairo |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5753882A (enExample) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61170140A (ja) * | 1985-01-24 | 1986-07-31 | Matsushita Electric Ind Co Ltd | コ−ド変換装置 |
-
1980
- 1980-09-16 JP JP12715680A patent/JPS5753882A/ja active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5753882A (ja) | 1982-03-31 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPS5917895B2 (ja) | 集積回路デジタル−アナログ変換器 | |
| US4369503A (en) | Decoder circuit | |
| JPH0336336B2 (enExample) | ||
| US4857772A (en) | BIPMOS decoder circuit | |
| EP0090186B1 (en) | Complementary logic circuit | |
| US6072413A (en) | Current output type digital-to-analog converter capable of suppressing output current fluctuation using a current mirror | |
| JPS6141176B2 (enExample) | ||
| JPH0573292B2 (enExample) | ||
| US5254887A (en) | ECL to BiCMIS level converter | |
| JPS5914828B2 (ja) | デコ−ダ回路 | |
| JP2548737B2 (ja) | ドライバ回路 | |
| JPS63272119A (ja) | 半導体集積回路装置 | |
| US4613774A (en) | Unitary multiplexer-decoder circuit | |
| JP2987971B2 (ja) | レベル変換回路 | |
| JP2513009B2 (ja) | ディジタル―アナログ変換回路 | |
| JP2580250B2 (ja) | バイポーラcmosレベル変換回路 | |
| JP2760047B2 (ja) | エミッタ結合型論理回路 | |
| US4954738A (en) | Current source technology | |
| JPS58225727A (ja) | ダ−リントン回路 | |
| KR840001498B1 (ko) | 반도체 기억장치의 데코오더 회로 | |
| KR840002027B1 (ko) | 디 코 더 회 로 | |
| SU1001479A1 (ru) | Интегральна логическа схема | |
| JPH04315319A (ja) | デコーダ | |
| JP2868245B2 (ja) | 半導体装置及び半導体メモリ | |
| KR920008047B1 (ko) | 논리회로 |