JPS6140042U - Digital binary increment circuit - Google Patents
Digital binary increment circuitInfo
- Publication number
- JPS6140042U JPS6140042U JP12511084U JP12511084U JPS6140042U JP S6140042 U JPS6140042 U JP S6140042U JP 12511084 U JP12511084 U JP 12511084U JP 12511084 U JP12511084 U JP 12511084U JP S6140042 U JPS6140042 U JP S6140042U
- Authority
- JP
- Japan
- Prior art keywords
- signal
- cao
- digital binary
- increment circuit
- binary increment
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は本考案の一実施例の回路図、第２図は従来例、
第３図は真理値表である。
１・・・ＩＮ信号、２・・・Ｃａ （キャリ）信号、３
・・・ＯＵＴ信号、、４・・・Ｃａｏ （キャリ）信号
、５・・・インバータ、６，７・・・トランスファゲー
ト、８，９・・・直通ゲート、１０・・・短絡ゲート。Figure 1 is a circuit diagram of an embodiment of the present invention, Figure 2 is a conventional example,
Figure 3 is a truth table. 1...IN signal, 2...Ca (carry) signal, 3
OUT signal, 4... Cao (carry) signal, 5... Inverter, 6, 7... Transfer gate, 8, 9... Direct gate, 10... Short circuit gate.
Claims (1)
、ＣａＯ（キャリ）信号を出力するデイジタル２進イン
クリメント回路において、 ＩＮ信号により制御される２つのＣＭＯＳトランスファ
ゲートと、Ｃａ信号により制御されるＮ形・Ｐ形の２つ
のＭＯＳ直通ゲートと、Ｃａｏ信号端子をアースに短絡
するＭＯＳ短絡ゲートと、ＩＮ信号を反転するＣＭα冒
ンバータとからなり、（イ） Ｃａ信号が、｝Ｎ信号
によるトランスファゲートの切替によって、ＣａＯ信号
またはＯＵＴ信号として出力し、 （口Ｉ ＩＮ信号またはＩＮ反転信号が、Ｃａ信号に
よる直通ゲートの切替によって、ＯＵＴ信号として出力
し、 （ハ）Ｃａｏ信号はＩＮ信号が“０のとき短絡ゲートに
より゜“０とされる ことを特徴とするデイジタル２進インクリメント回路。[Claim for Utility Model Registration] In a digital binary increment circuit that inputs an IN signal and a Ca (carry) signal and outputs an OUT signal and a CaO (carry) signal, two CMOS transfer gates controlled by the IN signal and , two MOS direct gates of N type and P type controlled by the Ca signal, a MOS shorting gate that shorts the Cao signal terminal to ground, and a CMα inverter that inverts the IN signal. is output as a CaO signal or an OUT signal by switching the transfer gate using the }N signal; A digital binary increment circuit characterized in that the Cao signal is set to 0 by a shorting gate when the IN signal is 0.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12511084U JPS6140042U (en) | 1984-08-17 | 1984-08-17 | Digital binary increment circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12511084U JPS6140042U (en) | 1984-08-17 | 1984-08-17 | Digital binary increment circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6140042U true JPS6140042U (en) | 1986-03-13 |
Family
ID=30683790
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12511084U Pending JPS6140042U (en) | 1984-08-17 | 1984-08-17 | Digital binary increment circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6140042U (en) |
-
1984
- 1984-08-17 JP JP12511084U patent/JPS6140042U/en active Pending
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