JPS6050518U - balanced modulator - Google Patents
balanced modulatorInfo
- Publication number
- JPS6050518U JPS6050518U JP14310483U JP14310483U JPS6050518U JP S6050518 U JPS6050518 U JP S6050518U JP 14310483 U JP14310483 U JP 14310483U JP 14310483 U JP14310483 U JP 14310483U JP S6050518 U JPS6050518 U JP S6050518U
- Authority
- JP
- Japan
- Prior art keywords
- transistors
- balanced modulator
- emitters
- bases
- collectors
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Amplitude Modulation (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は従来の平衡変調器の回路図。第２図は本考案の
平衡変調器の回路図。第３図は本考案の回路における入
出力の相関図。第４図は第２図のさらに具体的な回路図
。
１１．１１’、１２．１２’、２１．２１’。
２２．２２’・・・入力端子、１３．１３’、２３゜２
３′・・・出力端子、Ｑ１１〜Ｑ１６？ Ｑ２１〜Ｑ２
６・・・トランジスター。FIG. 1 is a circuit diagram of a conventional balanced modulator. FIG. 2 is a circuit diagram of the balanced modulator of the present invention. FIG. 3 is a correlation diagram of input and output in the circuit of the present invention. FIG. 4 is a more specific circuit diagram of FIG. 2. 11.11', 12.12', 21.21'. 22.22'...Input terminal, 13.13', 23°2
3'...Output terminal, Q11 to Q16? Q21~Q2
6...Transistor.
Claims (1)
のトランジスターのベース間を第１の入力端子とし、第
１及び第２のトランジスターのコレクターにそれぞれ定
電流源と、第１及び第２のトランジスターの相補極性で
ある第３・第４及び第５・第６のトランジスターのエミ
ッターが接続され、第３と第６及び第４と第５のトラン
ジスターのベースをそれぞれ接続して第２の入力端子と
し、第３と第５及び第４と第６のトランジスターのコレ
クターをそれぞれ接続して出力端子とじた平衡変調器。The first and second emitters are connected to the same constant current source.
A first input terminal is connected between the bases of the transistors, a constant current source is connected to the collectors of the first and second transistors, and third, fourth, and fifth input terminals having complementary polarities of the first and second transistors are connected. The emitters of the sixth transistors are connected, the bases of the third and sixth transistors and the fourth and fifth transistors are connected respectively to form a second input terminal, and the third and fifth transistors and the fourth and sixth transistors are connected. A balanced modulator with the collectors connected to each other and the output terminals closed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14310483U JPS6050518U (en) | 1983-09-14 | 1983-09-14 | balanced modulator |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14310483U JPS6050518U (en) | 1983-09-14 | 1983-09-14 | balanced modulator |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6050518U true JPS6050518U (en) | 1985-04-09 |
| JPH0212735Y2 JPH0212735Y2 (en) | 1990-04-10 |
Family
ID=30319536
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14310483U Granted JPS6050518U (en) | 1983-09-14 | 1983-09-14 | balanced modulator |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6050518U (en) |
-
1983
- 1983-09-14 JP JP14310483U patent/JPS6050518U/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0212735Y2 (en) | 1990-04-10 |
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