JPS6138935U - integrated circuit device - Google Patents

integrated circuit device

Info

Publication number
JPS6138935U
JPS6138935U JP12148484U JP12148484U JPS6138935U JP S6138935 U JPS6138935 U JP S6138935U JP 12148484 U JP12148484 U JP 12148484U JP 12148484 U JP12148484 U JP 12148484U JP S6138935 U JPS6138935 U JP S6138935U
Authority
JP
Japan
Prior art keywords
integrated circuit
circuit device
semiconductor layer
isolation region
isolating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12148484U
Other languages
Japanese (ja)
Inventor
明憲 高橋
Original Assignee
日本電気株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日本電気株式会社 filed Critical 日本電気株式会社
Priority to JP12148484U priority Critical patent/JPS6138935U/en
Publication of JPS6138935U publication Critical patent/JPS6138935U/en
Pending legal-status Critical Current

Links

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  • Element Separation (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本考案の一実施例を示す集積回路の部分断面図
である。 第２図は従来のボンデイングパツドまわりを示した集積
回路の断面図である。 第３図は本考案を説明するための光電変換回路の回路図
である。 １・・・・・・Ｐ型半導体基板、２・・・・・・島状Ｎ
型領域、３・・・・・・Ｎ十領域、４，４′・・・・・
・Ｐ型絶縁分離領域、５，５′・・・・・・増幅器の配
線、ＰＤ・・曲ホトダイオード、Ｒ１， Ｒｓ， Ｒ，
・・・・・・抵抗、Ｃ・・・・・・コンデンサ、Ａ・・
・・・・演算増幅器。FIG. 1 is a partial sectional view of an integrated circuit showing an embodiment of the present invention. FIG. 2 is a cross-sectional view of an integrated circuit showing the area around a conventional bonding pad. FIG. 3 is a circuit diagram of a photoelectric conversion circuit for explaining the present invention. 1... P-type semiconductor substrate, 2... Island-like N
Type area, 3...N10 area, 4, 4'...
・P-type insulation isolation region, 5, 5'...Amplifier wiring, PD...curved photodiode, R1, Rs, R,
...Resistance, C...Capacitor, A...
...Operation amplifier.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 半導体基板上に形成された半導体層に形成された集積回
路化増幅器の入力端子を形成する配線直下に前記半導体
層を分離する絶縁分離領域を配置したことを特徴とした
集積回路装置。1. An integrated circuit device, characterized in that an insulating isolation region for isolating the semiconductor layer is disposed directly under wiring forming an input terminal of an integrated circuit amplifier formed on a semiconductor layer formed on a semiconductor substrate.
JP12148484U 1984-08-08 1984-08-08 integrated circuit device Pending JPS6138935U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12148484U JPS6138935U (en) 1984-08-08 1984-08-08 integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12148484U JPS6138935U (en) 1984-08-08 1984-08-08 integrated circuit device

Publications (1)

Publication Number Publication Date
JPS6138935U true JPS6138935U (en) 1986-03-11

Family

ID=30680268

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12148484U Pending JPS6138935U (en) 1984-08-08 1984-08-08 integrated circuit device

Country Status (1)

Country Link
JP (1) JPS6138935U (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5310267A (en) * 1976-07-15 1978-01-30 Itt Semiconductor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5310267A (en) * 1976-07-15 1978-01-30 Itt Semiconductor device

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