JPS59146947U - semiconductor integrated device - Google Patents
semiconductor integrated deviceInfo
- Publication number
- JPS59146947U JPS59146947U JP4060483U JP4060483U JPS59146947U JP S59146947 U JPS59146947 U JP S59146947U JP 4060483 U JP4060483 U JP 4060483U JP 4060483 U JP4060483 U JP 4060483U JP S59146947 U JPS59146947 U JP S59146947U
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor integrated
- integrated device
- cross
- under
- buried layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第1図は従来方法によるレイアウト図、第2図、第3図
は本考案の一実施例のレイアウト図、第4図は第3図の
回路図である。
1・・・ポンディングパッド、2・・・A1配線、3・
・・分離層中心、4,5・・・n十埋込層コンタクト、
6・・・P層コンタクト、7・・・外部インタフェース
端子、8・・・配線、9・・・ダイオード。FIG. 1 is a layout diagram of a conventional method, FIGS. 2 and 3 are layout diagrams of an embodiment of the present invention, and FIG. 4 is a circuit diagram of FIG. 3. 1...Ponding pad, 2...A1 wiring, 3.
...separation layer center, 4,5...n ten buried layer contacts,
6... P layer contact, 7... External interface terminal, 8... Wiring, 9... Diode.
Claims (1)
成する分離島中の埋込層をクロスアンダ用導体に用いる
ことにより、クロスアンダ用領域を減少させることを特
徴とする半導体集積装置。A semiconductor integrated device characterized in that, in a dielectric isolation process, a buried layer in an isolation island constituting a bonding pad is used as a cross-under conductor to reduce a cross-under area.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4060483U JPS59146947U (en) | 1983-03-23 | 1983-03-23 | semiconductor integrated device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4060483U JPS59146947U (en) | 1983-03-23 | 1983-03-23 | semiconductor integrated device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS59146947U true JPS59146947U (en) | 1984-10-01 |
Family
ID=30171220
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP4060483U Pending JPS59146947U (en) | 1983-03-23 | 1983-03-23 | semiconductor integrated device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS59146947U (en) |
-
1983
- 1983-03-23 JP JP4060483U patent/JPS59146947U/en active Pending
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