JPS6025160U - Layered IC chip - Google Patents
Layered IC chipInfo
- Publication number
- JPS6025160U JPS6025160U JP11642683U JP11642683U JPS6025160U JP S6025160 U JPS6025160 U JP S6025160U JP 11642683 U JP11642683 U JP 11642683U JP 11642683 U JP11642683 U JP 11642683U JP S6025160 U JPS6025160 U JP S6025160U
- Authority
- JP
- Japan
- Prior art keywords
- chip
- layered
- stacked
- peripheral terminals
- recorded
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第1図は本考案による重ね合せチップの平面図、第2区
は第1図に示すものの断面図である。
図面中、1は下段ICチップ、2は上段ICチップ、3
はパッケージ受台、41は白金、4゜は絶縁体層、51
,5゜・・・は下段ICチップの周辺端子、61,6゜
・・・は上段ICチップの周辺端子、71.7□・・・
はパッケージのリード端子、81,8□・・・はリード
線である。FIG. 1 is a plan view of a stacked chip according to the present invention, and the second section is a cross-sectional view of the chip shown in FIG. In the drawing, 1 is the lower IC chip, 2 is the upper IC chip, and 3 is the lower IC chip.
is a package pedestal, 41 is platinum, 4° is an insulator layer, 51
, 5°... are peripheral terminals of the lower IC chip, 61,6°... are peripheral terminals of the upper IC chip, 71.7□...
are lead terminals of the package, and 81, 8□, . . . are lead wires.
Claims (1)
え避けて絶縁体層を介在して重ね合せて載置した上段の
ICチップからなることを特徴とする重ね合せICチッ
プ。A stacked IC chip comprising a lower IC chip and an upper IC chip stacked on top of each other with an insulating layer interposed therebetween, avoiding the peripheral terminals on the upper surface of the IC chip.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11642683U JPS6025160U (en) | 1983-07-28 | 1983-07-28 | Layered IC chip |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11642683U JPS6025160U (en) | 1983-07-28 | 1983-07-28 | Layered IC chip |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6025160U true JPS6025160U (en) | 1985-02-20 |
Family
ID=30268390
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP11642683U Pending JPS6025160U (en) | 1983-07-28 | 1983-07-28 | Layered IC chip |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6025160U (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05211281A (en) * | 1991-09-13 | 1993-08-20 | Internatl Business Mach Corp <Ibm> | Stepped package for electronic device |
-
1983
- 1983-07-28 JP JP11642683U patent/JPS6025160U/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05211281A (en) * | 1991-09-13 | 1993-08-20 | Internatl Business Mach Corp <Ibm> | Stepped package for electronic device |
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