JPS6138504B2 - - Google Patents

Info

Publication number
JPS6138504B2
JPS6138504B2 JP56162687A JP16268781A JPS6138504B2 JP S6138504 B2 JPS6138504 B2 JP S6138504B2 JP 56162687 A JP56162687 A JP 56162687A JP 16268781 A JP16268781 A JP 16268781A JP S6138504 B2 JPS6138504 B2 JP S6138504B2
Authority
JP
Japan
Prior art keywords
memory
data
access
address
cache
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP56162687A
Other languages
English (en)
Japanese (ja)
Other versions
JPS5864688A (ja
Inventor
Tadaaki Bando
Yasushi Fukunaga
Yoshinari Hiraoka
Hidekazu Matsumoto
Tetsuya Kawakami
Toshuki Ide
Takeshi Kato
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Hitachi Industry and Control Solutions Co Ltd
Original Assignee
Hitachi Engineering Co Ltd
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Engineering Co Ltd, Hitachi Ltd filed Critical Hitachi Engineering Co Ltd
Priority to JP56162687A priority Critical patent/JPS5864688A/ja
Publication of JPS5864688A publication Critical patent/JPS5864688A/ja
Publication of JPS6138504B2 publication Critical patent/JPS6138504B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
JP56162687A 1981-10-14 1981-10-14 デ−タ処理装置 Granted JPS5864688A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56162687A JPS5864688A (ja) 1981-10-14 1981-10-14 デ−タ処理装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56162687A JPS5864688A (ja) 1981-10-14 1981-10-14 デ−タ処理装置

Publications (2)

Publication Number Publication Date
JPS5864688A JPS5864688A (ja) 1983-04-18
JPS6138504B2 true JPS6138504B2 (enrdf_load_stackoverflow) 1986-08-29

Family

ID=15759386

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56162687A Granted JPS5864688A (ja) 1981-10-14 1981-10-14 デ−タ処理装置

Country Status (1)

Country Link
JP (1) JPS5864688A (enrdf_load_stackoverflow)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6054057A (ja) * 1983-09-02 1985-03-28 Hitachi Ltd キャッシュメモリ制御装置
JPS6079446A (ja) * 1983-10-06 1985-05-07 Hitachi Ltd 多重仮想記憶デ−タ処理装置
FR2590699B1 (fr) * 1985-11-25 1994-07-01 Nec Corp Systeme assurant la coherence pour les contenus d'une antememoire

Also Published As

Publication number Publication date
JPS5864688A (ja) 1983-04-18

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