JPS6136652B2 - - Google Patents
Info
- Publication number
- JPS6136652B2 JPS6136652B2 JP56066467A JP6646781A JPS6136652B2 JP S6136652 B2 JPS6136652 B2 JP S6136652B2 JP 56066467 A JP56066467 A JP 56066467A JP 6646781 A JP6646781 A JP 6646781A JP S6136652 B2 JPS6136652 B2 JP S6136652B2
- Authority
- JP
- Japan
- Prior art keywords
- gate
- accumulator
- instruction
- input
- data
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000012360 testing method Methods 0.000 claims description 25
- 238000012545 processing Methods 0.000 claims description 12
- 238000012546 transfer Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 3
- 101150023727 ald2 gene Proteins 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/0751—Error or fault detection not based on redundancy
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Debugging And Monitoring (AREA)
- Test And Diagnosis Of Digital Computers (AREA)
- Microcomputers (AREA)
- Executing Machine-Instructions (AREA)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56066467A JPS57182248A (en) | 1981-05-01 | 1981-05-01 | Arithmetic processor |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56066467A JPS57182248A (en) | 1981-05-01 | 1981-05-01 | Arithmetic processor |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS57182248A JPS57182248A (en) | 1982-11-10 |
JPS6136652B2 true JPS6136652B2 (ko) | 1986-08-19 |
Family
ID=13316607
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP56066467A Granted JPS57182248A (en) | 1981-05-01 | 1981-05-01 | Arithmetic processor |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS57182248A (ko) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS59211123A (ja) * | 1983-05-16 | 1984-11-29 | Nec Corp | 半導体集積回路 |
JPH01112434A (ja) * | 1987-10-27 | 1989-05-01 | Nec Corp | マイクロコンピュータ |
-
1981
- 1981-05-01 JP JP56066467A patent/JPS57182248A/ja active Granted
Also Published As
Publication number | Publication date |
---|---|
JPS57182248A (en) | 1982-11-10 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
EP0238090A2 (en) | Microcomputer capable of accessing internal memory at a desired variable access time | |
JPH0612863A (ja) | デュアルポートdram | |
EP0267613A2 (en) | Micro processor capable of being connected with coprocessor | |
US5303354A (en) | Data transfer system between registers for microcomputer | |
US4460972A (en) | Single chip microcomputer selectively operable in response to instructions stored on the computer chip or in response to instructions stored external to the chip | |
JPS6136652B2 (ko) | ||
US5828859A (en) | Method and apparatus for setting the status mode of a central processing unit | |
JPS6029980B2 (ja) | テスト・モ−ド設定機能をもつワンチツプ・マイクロ・コンピユ−タ | |
KR910001708B1 (ko) | 중앙처리장치 | |
JPS5821300B2 (ja) | デンシケイサンキ ノ メモリアドレスシテイホウシキ | |
JPS6362778B2 (ko) | ||
JPS6019538B2 (ja) | プログラム書込み方式 | |
JPS60123952A (ja) | 入出力制御方式 | |
JPH05282133A (ja) | 演算方式 | |
KR0171173B1 (ko) | 원칩 마이크로 컴퓨터 | |
JPH01121965A (ja) | マイクロプロセッサ | |
JPH01116702A (ja) | シーケンスコントローラ | |
JPH0545978B2 (ko) | ||
JPH08305564A (ja) | マイクロコンピュータ | |
JPS6346558A (ja) | スタンバイram内多バイトデ−タの保護方式 | |
JP2657947B2 (ja) | データ処理装置 | |
JP2984628B2 (ja) | マイクロコンピュータ | |
JPS60189043A (ja) | プロセツサ | |
JPH03189727A (ja) | 制御記憶ロード方式 | |
JPH03161845A (ja) | 情報処理装置 |