JPS6129596B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a synchronization signal generator suitable for use in television cameras and the like.

As is well known, the synchronization generator generates signals having various frequencies necessary for the synchronization of television signals. Various frequencies are formed using frequency dividers. For example, in an NTSC synchronization signal generator, multiple frequency dividers are provided, and the color subcarrier frequency _SC is used as the reference original oscillation frequency.
This frequency 4 _SC is appropriately divided to form a color subcarrier signal of frequency _SC , a horizontal synchronization signal, a vertical synchronization signal, etc.

By the way, since the operating states (counting states) of the plurality of frequency dividers provided in this synchronizing signal generator when the power is turned on are different, various signals S
The phase relationship between _H , S _V , S _SC , etc. is not constant.
Therefore, these phase relationships must be regulated to be constant.

Furthermore, when outputs from a plurality of television cameras are edited using a VTR, for example, and the camera output is a color video signal, editing must be done so that the phase of the color subcarrier signal S _SC is continuous. Therefore, when editing a color video signal, a color framing signal is used as a frame identification signal.

If we consider the NTSC color system now, the phase of the color subcarrier signal, the phase of the vertical synchronization signal, and the phase of the horizontal synchronization signal all match in four field periods, so the frequency of the color framing signal is the same as that of the vertical synchronization signal. It is necessary that the frequencies be at least 1/4. In this case, the original oscillation frequency 4 _SC
Since the phase of the color subcarrier signal S _SC created by counting down to 1/4 and the phase of a signal with a frequency of 1/4 _V created by a separate frequency division operation etc. are not always in a constant relationship, 1 /4 _V signal itself cannot be used as a color framing signal.

Therefore, this invention uses a signal obtained by dividing the original oscillation frequency 4 _SC to 1/4 _V to uniquely fix the counting phase of a counter that divides the original oscillation frequency 4 _SC to obtain the color subcarrier signal S _SC . By doing so, the signal obtained by dividing the frequency by 1/4 _V is given the meaning of color framing.
This invention applies not only to the NTSC system but also to the so-called PAL-M system.
This method can also be applied to a synchronization signal generator using the above method.

However, in the PAL-M system, a 1/4 _V signal cannot be used as a color framing signal, and a 1/8 _V signal obtained by further dividing this 1/4 _V signal into 1/2 is used.

Therefore, according to the present invention, the 1/4 counter that divides the original oscillation frequency 4 _SC has its counting phase fixed by this 1/8 _V frequency signal. In this way, the phase of the color subcarrier signal S _SC and the phase of the 1/8 _V signal are always fixed, so the 1/8 _V signal can be used as a color framing signal.

Hereinafter, a specific configuration of an example of the present invention applied to a synchronization signal generator for obtaining an NTSC synchronization signal will be described with reference to FIG.

However, as will become clear from what will be discussed later,
In each of the embodiments shown in FIGS. 1 and 6, the 1/4 _V or 1/8 _V signal is passed through the standardization circuit once, and then the 1/4 V or 1/8 V signal is
4 counters, but this point is not the essence of this invention. It should be noted in advance that these standardization circuits have specific configurations that take into account the delay of each frequency division counter, and may not be necessary depending on the selection and improvement of the elements used.

In the figure, 1 is an oscillator for a 4 _SC reference signal, which is supplied to a frequency divider (counter) 2 to 1/
455 to form a synchronizing frequency signal _{S2H with twice the horizontal frequency 2H ,} which is further supplied to the 1/2 counter 3 to generate the vertical synchronizing frequency S _V (pulse signal with a duty of 50%). It is formed. 5 is 1/
From this, a color subcarrier signal S _SC consisting of a pulse signal with a duty of 50% is formed by the counter No. 4.

Note that the horizontal and vertical synchronization frequency signals S _H , S _{V ,} etc. are supplied to a synchronization pulse forming circuit (not shown), from which well-known horizontal synchronization pulses, vertical synchronization pulses, etc. are formed.

On the other hand, 10 is a color framing signal forming circuit, which corresponds to a color framing signal with a cycle corresponding to the number of fields in which the phase of the color subcarrier signal S _SC goes around, that is, any one of the fields from the first field to the fourth field. A color framing signal P _D is formed. First, circuit 1
1, a pulse corresponding to an odd field or an even field is formed. Because of that,
The vertical synchronization frequency signal S _V obtained by the counter 4 and the vertical synchronization frequency signal S _V delayed by a fixed time D ₂ in the delay circuit 12 are supplied to the exclusive OR circuit 13, and in the odd field, In the even field, _{the pulse P E shown} in H in the figure is formed.

In addition, in FIG. 2, the delay time _D1 is the amount of delay caused by the counter 4, and the delay time D1 is the amount of delay caused by the counter 4, and
D is the vertical synchronization frequency signal S _VO in each field,
In the figure, E and _F show vertical synchronization frequency signals S _VO and S _VE delayed by D ₂ .

The pulses P _O and P _E are supplied to the AND circuit 14 together with the horizontal synchronization frequency signal S _H obtained by the counter 3 . The AND output P _A (FIG. 2I) is obtained only for odd fields. Thus, first, the phase relationship between the horizontal and vertical frequency signals S _H and S _V is fixed. This AND output P _A is obtained corresponding to an odd field, but it is not possible to determine whether this AND output P _A is an AND output for an odd frame or an even frame, so the frame and field cannot be specified. . Therefore, the AND output P _A is further 1/2 counter 15
A color framing signal P _D as shown in FIG. 3B is formed.

Since this color framing signal P _D has a period of four fields, it becomes a pulse corresponding to any one of the fields from the first field to the fourth field, and becomes a signal in which a field, that is, a frame is specified. In the embodiment, it is obtained corresponding to an odd number frame (first field).

Note that this color framing signal P _D may be further waveform-shaped and the signal shown in FIG. 3C may be used as the color framing signal P _D '.

By the way, color framing is based on the premise that the phase relationship between the color framing signal P _D and the color subcarrier signal S _SC is always fixed. However, there are four types of phase relationships that can occur when the power is turned on, and there is no guarantee as to which phase relationship will occur. Unless a constant phase relationship (for example, 0 phase) is always maintained even when the power is turned on, it cannot function as a color framing signal.

Therefore, in the present invention, by configuring the counter 5 to be controlled by the color framing signal P _D (the period of which is equal to the field period in which the phase of the signal S _SC goes around), the above-mentioned fixed phase relationship can be obtained. This is what we are trying to do.

Here, in the circuit actually used, the reference frequency is 4f _SC
Since a large number of counters are involved before the frequency is divided to form the color framing signal P _D , the color framing signal P _D is slightly delayed due to the intervention of these counters, but this time delay is compensated by the logic circuit used. It also varies depending on external factors such as temperature. The counting state of the counter 5 controlled by the signal S _1/2H is different depending on whether the variation is within one clock of the reference signal or more than one clock. Therefore, when the counter 5 is controlled by the color framing signal P _D having such a fluctuation component, the signal P _D
It is not possible to obtain a fixed phase relationship between and S _SC .

On the other hand, if the color framing signal P _D is controlled by normalizing it to the reference signal S _O , the above-mentioned variation is absorbed by this standardization, and as a result, the control timing for the counter 5 is always constant, and the above-mentioned constant Phase relationships can be obtained.

The control signal for the counter 5 may be the color framing signal P _D itself as described above, but
The example described below facilitates the formation of control signals (pulses) for the counter 5.

That is, the counting state of the counter 5, such as resetting and loading, is controlled depending on whether the state of the control pulse having a pulse width within one clock of the reference signal S _O is "0" or "1". Therefore, if this control pulse has a pulse width of one clock or more, it is unclear how the counting phase of the counter 5 will be controlled, and the counter 5 will be controlled so that it is always in a constant counting state. I can't.

Since it is extremely difficult to form a control pulse with a pulse width within one clock from the color framing signal P _D , it is necessary to use some means to form a control pulse with the above-mentioned pulse width. In this embodiment, the purpose is achieved by using a 4-field cycle color framing signal P _D standardized to 4 _SC clock pulses as a control pulse.

Next, the standardization circuit 20 which performs the above operation
I will explain about it.

In this example, the color framing signal P _D is set to 2
A first standardization circuit 20A for standardizing the _H signal S to _2H , and a second standardization circuit 20B for standardizing the _4SC reference signal S _O with the standardized signal related to _2H . configured. The explanation will start from the first normalization circuit 20A.

As shown in the figure, this is composed of two D-type flip-flop circuits 21 and 22, and a color framing signal P _D is supplied to each clear terminal Cl, and a _2H signal S _2H is supplied to a clock terminal CK. . Since DC voltage B+ is applied to the data terminal _D1 of the flip-flop circuit 21 in the previous stage,
As shown in FIG. 4, the color framing signal P is delayed by τ ₁ from the rising edge of the clock signal _S2H .
When _{signal D} (B in the same figure) is input, the output S _q1 of the _Q1 terminal rises as shown in C in the figure at the rise of the signal S _2H immediately after the input of this color framing signal P _D. The inverted output _q1 (D in the same figure) is supplied to the data terminal _D2 of the flip-flop circuit 22 in the subsequent stage, so the output _Sq2 of the _Q2 terminal is one cycle of the signal _S2H immediately after the input of the color framing signal _PD . The _2H signal S _2H is standardized based on the color framing signal P _D , which is obtained only during this one cycle in synchronization with the rising edge of the signal P D (see E in the figure).

Note that the above-mentioned time delay τ ₁ is the amount of delay that occurs between the _2H signal S _2H and the color framing signal P _D due to the intervention of a counter or the like.

This standardized output (first standardized output) S
_q2 is supplied to the clear terminal Cl of the second standardization circuit 20B. The second standardization circuit 20B has the same configuration as the first standardization circuit 20A, and includes a pair of D-type flip-flop circuits 25 and 26. A _4SC reference signal _S0 to be finally standardized is supplied to each clock terminal CK.

The operation for standardization is as shown in FIG. The time delay of τ ₂ that occurs between the reference signal S _O and the first standardized output S _q2 is the amount of delay caused by the counter 2, and the first standardized output that has this time relationship now When S _q2 is input to the clear terminal _Cl , an output as shown in _{FIG .} S _q4 is obtained. That is, by the first normalized output S _q2 for the 2 _H signal S _2H , 4
_{The SC} reference signal S _O is standardized.

The second normalized output S _q4 has a pulse width within one cycle of the reference signal S ₀ as shown in FIG.

Therefore, if the counter 5 is controlled (specifically, loaded to "1, 0") with such a second normalized output S _q4 , the phase of the color framing signal P _D and the color subcarrier signal S _SC can be changed. The relationship remains constant.
Therefore, color framing can be performed correctly by editing based on the above-mentioned color framing signal P _D (or P _D ').

When the present invention is applied to a synchronization signal generator whose standard system is PAL-M system, its configuration becomes as shown in FIG. The PAL-M system also uses 4 _SC as the reference frequency. However, 4 _SC is different from the case of the NTSC system, and 4 _SC = 909 _H.

The reference signal S _O obtained by the oscillator 30 is sent to the counter 31
The output S _101H is further divided into 1/101 by a counter 32 to form a horizontal synchronization frequency signal S _H . This horizontal synchronous frequency signal S _H is transmitted to the color framing signal forming circuit 10.
counters 33 and 34 in this example.
A forming circuit 10 is configured. That is, first, the horizontal frequency _H is divided by 1/525 in the counter 33 to form an output S _1/2V having a vertical frequency of 1/2. This output S _1/2V is a signal corresponding to an odd or even field.

Here, in the PAL-M system, the relationship between the color subcarrier frequency _SC and the vertical frequency _V is expressed as _SC = 909/4 _H = 909/4 x 525/2 _V ... (1) Therefore, the color subcarrier frequency It takes eight fields for the phase of the signal S _SC to complete one cycle. Therefore, the output S _1/2V is further divided into 1/4 by the counter 34, and the output P _D of 8 feed periods in which the phase relationship between the horizontal synchronization frequency signal S _H and the vertical synchronization frequency signal S _V is fixed is obtained. This resets the counter 35 which obtains the color subcarrier signal S _SC (frequency _SC ).

This output P _D has a period of 8 fields, and the first
Since the output corresponds to any field from the field to the eighth field, this output P _D corresponds to the color framing signal shown in FIG. In this example, since the output P _D is obtained for the first field, this output P _D indicates the first field.

Counter 3 by color framing signal _D
5, the above-mentioned embodiment is similarly controlled.
It is preferable to normalize this color framing signal P _D to a reference signal S _O. Therefore, in this example as well, the standardization circuit 20 is provided, and the color framing signal P is output in the first standardization circuit 20A.
_D is normalized to a signal _S101H of _101H , and the first normalized output _Sq2 normalized to this signal _S101H is further supplied to the second normalization circuit 20B, which converts it into a reference signal _S0. Standardized. This reference signal S _O
Counter 3 with the second normalized output S _q4 normalized to
5 is controlled.

By the way, since a counter generally only performs frequency division by an integer, the output S obtained from the counter 32
It is not possible to directly obtain the vertical synchronization frequency signal S _V from _H. That is, this is because there is a relationship of 2 _H =525 _V. Therefore, in this example, 2 _h ( _h is the horizontal frequency) obtained by a PLL (phase locked loop) system is used for the divided output of the vertical synchronization frequency signal S _V.

40 is this PLL system, and the oscillation frequency of the voltage controlled oscillator (VCO) 41 is selected to be 2n _h .
This oscillation output is frequency-divided by 1/n by a counter 42 to form a signal _S2h with a frequency of _2h . Then, this frequency-divided output is further processed by the counter 43 to 1/
2 to form a signal Sh with a horizontal frequency _h , this and the horizontal synchronizing frequency signal S _H obtained by the counter 32 are phase-compared in a phase comparator 44, and the comparison output is passed through a low-pass filter 45.
It is supplied to VCO41 as a control voltage.
This PLL 40 causes the phase of frequency _h to match the phase of frequency _H. As a result, the phase of the frequency _2h also matches the phase of _H.

The signal S _2h of 2 _h is frequency-divided by 1/525 by a counter 47 to form a vertical synchronization same wave number signal S _V .

48 is a burst flag pulse BF forming circuit;
Reference numeral 49 denotes a line signal (alternative signal) ALT forming circuit, all of which are formed based on the _2h signal _S2h . The counter 47 and the forming circuits 48 and 49 are both reset by the color framing signal P _D to regulate the phase relationship.

As explained above, according to the present invention, since the counters 5 and 35 are controlled by the color framing signal P _D , the horizontal synchronization frequency signals S _H ,
The phase relationship between the color subcarrier signal S _SC and the color framing signal P _D and the phase relationship between these and the vertical synchronization frequency signal S _V can always be kept constant. Since a color framing signal P _D corresponding to a specific frame can be easily generated, this color framing signal P _D can be supplied to an editing machine such as a VTR together with the camera output (color video signal) to provide a control signal during editing. If you use it as a , you can easily create color framing.

Note that since the circuit system that controls the counters 5 and 35 using the color framing signal P _D only needs to operate for a certain period of time after the power is turned on, a switch may be provided to open this circuit system.

[Brief explanation of the drawing]

FIG. 1 is a system diagram showing one example of this invention, FIGS. 2 to 5 are waveform diagrams for explaining its operation, and FIG. 6 is a system diagram showing another example of this invention. 1, 30 is an oscillator for the reference signal S _O , 2 to 5, 1
5, 31 to 35, 42, 43, and 45 are frequency dividing counters, 20 is a standardization circuit, and 10 is a color framing signal P _D forming circuit.

Claims (1)

[Claims] 1. The oscillation output of the reference oscillator is supplied to a frequency divider to form a color subcarrier signal, and the oscillation output is further supplied to a color framing signal forming circuit comprising a plurality of frequency dividers to form a color framing signal. and a synchronization signal generator, wherein the frequency divider for forming the color subcarrier signal is controlled based on the color framing signal so that the phase of the color subcarrier signal with respect to the framing signal is fixed.