JPS6054525A - Pll device - Google Patents

Abstract

PURPOSE:To make it possible to make a device small-sized and reduce the variance of a frequency near a stable frequency by using an analog sampling circuit instead of a low-pass filter, a phase comparator, and a frequency divider in a PLL oscillator. CONSTITUTION:The analog sampling circuit (AS)13 samples the analog value of an input f2 to a data input terminal D when an input f1 to a clock input terminal C rises, and the AS13 latches data till a next sampling time and outputs it from an output terminal Q. When the input f2 is raised relatively, a sampling point is changed from a point (a) to a point (b), and therefore, the oscillation frequency of a voltage control oscillator VCO14 is lowered, and the frequency and the phase are converged to a prescribed value. Thus, the device can be made small-sized, and the variance of the frequency of the VCO is reduced according as the frequency of the VCO approaches the stable frequency.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention is used, for example, in a television signal generator for a personal computer for transmitting a video signal and providing image information to a television receiver for general home use. This invention relates to a PLL device.

Conventional configurations and their problems Generally, video signals are sent to a home television receiver,
A VD that produces a video signal in a television signal generator for a personal computer to provide image information.
L called P (video display processor)
SI is given as a timing source for synthesizing a video signal with a fixed frequency 11 signal. On the other hand, an encoder for converting a color television signal to the NTSC system or PAL system modulates the video signal with two orthogonal subcarrier signals of the modulation frequency f2 to create a composite signal. When the frequencies f1 and f2 deviate from the fixed frequency 2 phase relationship, a striped pattern appears on the screen.
The striped pattern appears to move as if flowing, and its state changes every moment. Therefore, the frequency f1. It was necessary to maintain f2 in a constant frequency-one-phase relationship with the PLL device.

A PLL device conventionally used for the above-mentioned purpose divides the frequency f1 output from a reference oscillator 1 by 1/N1 using a first frequency divider 2, as shown in FIG. On the other hand, the frequency f2 output from the voltage controlled oscillator 6 to which the output of the phase comparator 3cl is given via the low-pass filter 4 is divided by 1/N2 by the second divider 6, and the frequency f2 is divided by 1/N2 to the phase comparator 3cl. 3 and the respective different frequencies f1. The configuration was such that f2 was kept at a constant speed.

However, in the configuration of the PLL device described above, it is necessary to use frequency dividers 2 and 6, respectively, so that the input frequencies to the phase comparator 3 are equal. However, the disadvantage was that the configuration was complicated. The phase comparator 3 is composed of a multiplier, and its characteristics are as shown in FIG. 2, as shown in FIG. v
The pulse width output v3 is inversely proportional to φ according to the phase difference φ of 2.
Therefore, the output v4 of the low-pass filter 4 has φ of 00
Therefore, it cannot operate unless the frequencies are equal. An example of application of the above-mentioned PLL device to a television signal generator in a personal computer is shown in FIG. In Figure 3, A is a VDP, 8 is a PAL encoder (hereinafter referred to as ENC),
9 is a horizontal synchronization signal separation device (hereinafter referred to as H-8EP);
1o is an orthogonal subcarrier generator for video signal modulation (hereinafter referred to as C3O). The above C3O1o corresponds to the chrominance subcarrier fsc and the chrominance subcarrier fsc.
It outputs a chrominance subcarrier f/9oo, fsc/27o0C with a phase difference of 2°, 2000. In addition, the above VDP completion is a signal Y1 color difference signal R-Y which is a combination of a luminance signal, a horizontal synchronization signal, and a vertical synchronization signal.
, B-Y, and outputs a composite video signal encoded into a PAL signal from the ENCs.

According to the broadcasting standard, the chrominance subcarrier fsc and horizontal synchronization frequency fH are each fSC = 4.4336.
1875MH2 fH=15.625KH2.

VDP7 horizontal synchronization timing is frequency 11 1/e
Since it is obtained by dividing the frequency by 84, f1/684 = fH fl-15, 625KHz x 684-10-687
It becomes 5MHz. The frequency 41sc of the oscillator 1 for generating the chrominance subcarrier fsc and fsc/9CP, 2700 is 4 f SC"" 17 , 734475 MHz. Therefore, in order to maintain the relationship between the chrominance subcarrier fscl and the horizontal synchronization frequency fH as per the broadcasting standard, it is necessary to oscillate f 1-10-6875 MHz 4fSC=17.734475 MHz.

However, the dot timing is 68 within one horizontal line period.
4, whereas the chrominance subcarrier fsc
The number of cycles is fsc ÷ fH = 253.7516, which is not an integer, and a flowing pattern occurs on the screen at the boundary between different colors, so fBC + fH is converted into an integer, and fsc + f
While there are 684 dot timings in 0, that is, one horizontal line period, which is changed to H-284,
The number of cycles of the chrominance subcarrier fSC is also required to be an integer number of 284, that is, U~-=JL 284 684 j, = f.

The relationship 71 171 must be maintained perfectly. Therefore, in the PLL device described above, a 10th frequency divider and a 2nd frequency divider are required.

1 When the above-mentioned PLL device is applied to a television signal generator in a Nokuichi sonal computer, the horizontal synchronizing signal is separated in the H-3I4'9,
The horizontal synchronizing signal included in the Y signal among the output signals of the VDP 7 has to be constructed with a large branching stage as described above when the configuration of the VDP 7 is simplified.

Purpose of the Invention The present invention provides a PLL that can maintain a constant two-frequency phase relationship even if the input signals to the phase comparator do not have the same frequency.
The purpose is to provide equipment.

Structure of the Invention In order to achieve the above object, the present invention provides a first input terminal for each clock and data input terminal of an analog sampling circuit.
．． applying each of the second input signals to this analog l1
17? The output of the sampling circuit is the above-mentioned No. 1. The present invention is characterized in that the frequency and phase relationship between the first and second input signals are maintained constant by feeding back to the oscillator that generates the second input signal to change the frequency.

DESCRIPTION OF THE EMBODIMENT FIG. 4 shows an embodiment of the present invention. In FIG. 4, 11 is a reference oscillator (hereinafter referred to as O3C), and 12 is
/N1 frequency divider, 13 is an analog sampling circuit (hereinafter referred to as As), 14 is a voltage controlled oscillator (hereinafter referred to as V'CO), and the frequency is divided by 08C11 and applied to the clock input terminal C of AS13. The oscillation output of VC○14 is A
It is applied to the data input terminal of S13. The latch output terminal Q of AS13 is connected to the oscillation frequency control voltage input terminal of VCOq4.

Here, AS13 is the input f1 to the clock input terminal C.
The analog value of the input f2 to the data input terminal is sampled at the rising edge of f1, and the sampled data is output from the latch output terminal Q until the next rising edge of the input f1, that is, the sampling timing.

Further, as shown in FIG. 5, VCCN 4 has one end connected to the control voltage input terminal 21 and the other end of the resistor 22 grounded via a variable capacitance diode 23, and connects the resistor 22 and the variable capacitance diode to the connection point. is grounded via a capacitor 24.26, and the connection point of the capacitor 24.25 is grounded via an inductance 26 and a capacitor 27.28, and a resistor 29 and a CMOS inverter are connected in parallel to the series circuit of the inductance 26 and capacitor 27. 3° is connected, and the connection point between the CMOS inverter 30 and the resistor is connected to the output terminal 32 via the CMOS inverter 31. It is configured to change the frequency of the oscillation output output from 32.

In such a configuration, AS shown in FIG.
When the lock input waveform W1 of 13 is at point a of the output waveform W2 of VCC) + 4, when the value is fed back to the VCD 14, fl-n2f remains, but if n2- is configured as a positive integer, the input f1 due to disturbance Furthermore, if the frequency of f2 fluctuates and the input f2 relatively increases, the number of cycles of the waveform W2 of the input f2 until the next sampling timing increases and is sampled at point b in FIG. 6.

Therefore, the output of the AS 13 decreases further until the next sampling timing, so the oscillation frequency of the VCO 1 4 decreases, and a feedback force acts to restore the original state to the influence of the disturbance. Therefore, input f1
Waveform w4v? At the sampling timing, a stable state exists when the waveform W2 of the input f2 is at a specific level within the range of the downward slope to the right, and the inputs f1 and f2 can be maintained in a constant frequency two-phase relationship.

That is, in Fig. 6, when Wl is sampled, W2 is a
If we take the point value, we will be in a stable state, but due to disturbance, b
When the value at a point is taken, the voltage difference between the value at point a and the value at point b of Wl is fed back to vCO 14 as an error voltage. Then, at the time of the next sampling, the error voltage is fed back at a timing when the error voltage becomes smaller. As a result, the error voltage fed back becomes smaller over time9, and is finally focused on the original feedback output voltage at point a. In this process, the error output voltage that is fitted back becomes smaller over time, so the change in the oscillation frequency of VCO14 decreases over time, and when the stable state, point a, is reached, the change in the oscillation frequency of C014 is minimal. become. This is a characteristic obtained by continuously changing the feedback output voltage with respect to the phase shift at the sampling point, and it is possible to obtain the same effect as the output voltage change curve of the conventional example (the case shown in Figure 2). It shows.

In addition, in the above embodiment, the data input terminal DK of AS13
The configuration is such that the output of the VCO 14 is added and the output of the frequency divider 12 is added to the clock input terminal C. In addition, as shown in FIG. It may be configured to add the output f1 obtained by frequency-dividing the output of vC014.

FIG. 8 shows a case where the above-described PLL device of the present invention is applied to a television signal generation device in a personal computer. In FIG. 8, the signal to the clock cell M of the phase comparator AS13 is connected, and SC is connected to the data input terminal, and the following relationship is obtained.

Here, both the fl and 4fSC oscillators use crystal oscillators.

The cycle is the design value, but even if it is 283 cycles, it is 285
Even if the cycle is an integer, there is a possibility that it will be locked.The deviation of 0 1 cycle occurs when a deviation of 84 knee - 3520 ppm occurs in the relative frequency relationship of fl and f2.In this example, a crystal oscillator is used, and this Prevents misalignment,
Only the oscillation frequency of 4fsc is adjusted to match the specified frequency, and the oscillation frequency of fl is not adjusted.

Effects of the Invention As described above, according to the present invention, since the N2 frequency divider can be omitted by using an analog sampling circuit, it is possible to reduce the cost, size, and power consumption of the device. Further, even if a change in the frequency of the VCO occurs due to a disturbance, the change in the frequency of the VCO becomes smaller as the VCO approaches a stable frequency. At a stable layer wavenumber where the oscillation frequency of the VCO is focused, the fluctuation can be minimized.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a conventional PLL device, FIG. 2 is a waveform diagram of each part thereof, FIG. 3 is a block diagram showing an example of application to a television signal generator in a personal computer, and FIG. 4 is a block diagram of a conventional PLL device. A block diagram showing an embodiment of the PLL device, FIG. 6 is a specific circuit diagram of the VCO in the device,
Figure 6 is a waveform diagram of each part to explain the operation of the device, Figure 7 is a block diagram showing another embodiment of the PLL device of the present invention, and Figure 8 is a diagram of the PLL device of the present invention. (- It is a block diagram showing an application to a television signal generation device in a nonal computer. 11...Reference oscillator, 12... Frequency divider, 13... Analog sampling circuit, 14・
...Voltage cloth 1] Control oscillator. Name of agent: Patent attorney Toshio Nakao 1 person Figure 1 Figure 2 18θ6 b' f/J9ρ0-φ Figure 3 Figure 4

Claims (1)

[Claims] 1st. The second input signal is connected to the clock input terminal and the data terminal of the analog sampling circuit, respectively, and the output of the analog sampling circuit is fed back to the oscillator that generates the first or second input signal to generate a change in frequency. Let, set 0