JPS6129070B2 - - Google Patents

Info

Publication number
JPS6129070B2
JPS6129070B2 JP56205120A JP20512081A JPS6129070B2 JP S6129070 B2 JPS6129070 B2 JP S6129070B2 JP 56205120 A JP56205120 A JP 56205120A JP 20512081 A JP20512081 A JP 20512081A JP S6129070 B2 JPS6129070 B2 JP S6129070B2
Authority
JP
Japan
Prior art keywords
circuit
memory cell
voltage
correction
bit line
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP56205120A
Other languages
English (en)
Japanese (ja)
Other versions
JPS58108090A (ja
Inventor
Takeshi Takeya
Hirotoshi Sawada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP56205120A priority Critical patent/JPS58108090A/ja
Publication of JPS58108090A publication Critical patent/JPS58108090A/ja
Publication of JPS6129070B2 publication Critical patent/JPS6129070B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits

Landscapes

  • Static Random-Access Memory (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
JP56205120A 1981-12-21 1981-12-21 メモリ回路 Granted JPS58108090A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56205120A JPS58108090A (ja) 1981-12-21 1981-12-21 メモリ回路

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56205120A JPS58108090A (ja) 1981-12-21 1981-12-21 メモリ回路

Publications (2)

Publication Number Publication Date
JPS58108090A JPS58108090A (ja) 1983-06-28
JPS6129070B2 true JPS6129070B2 (cs) 1986-07-04

Family

ID=16501747

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56205120A Granted JPS58108090A (ja) 1981-12-21 1981-12-21 メモリ回路

Country Status (1)

Country Link
JP (1) JPS58108090A (cs)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6584026B2 (en) 2000-06-28 2003-06-24 Kabushiki Kaisha Toshiba Semiconductor integrated circuit capable of adjusting input offset voltage
JP4965883B2 (ja) * 2006-04-07 2012-07-04 株式会社東芝 半導体集積回路装置および半導体集積回路装置のトリミング方法
JP5452348B2 (ja) * 2009-07-27 2014-03-26 ルネサスエレクトロニクス株式会社 半導体記憶装置

Also Published As

Publication number Publication date
JPS58108090A (ja) 1983-06-28

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