JPS6129070B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a high-density memory circuit that stores information in each memory cell formed in large numbers on a single substrate.

Conventionally, this type of memory circuit has a large number of circuit groups (hereinafter referred to as row circuits) whose configuration is shown in FIG. The memory cell includes a mechanism for inputting and outputting data from the memory cells to the outside, and a mechanism for controlling the row circuit and the mechanism. The row circuit is N
(N is an even number of 1 or more) memory cells MC ₁ , MC ₂ , ... MC〓, MC〓 ₊₁ , MC _N ,
It is composed of two precharge circuits PC ₁ and PC ₂ , a sense amplifier circuit SA, a data input/output circuit DIO, two bit lines BL ₁ and BL ₂ , and two dummy cell circuits DC ₁ and DC ₂ . Circuit PC ₁ , dummy cell circuit DC ₁ , memory cell MC ₁ , MC ₂ ,...
MC = bit line BL ₁ , precharge circuit PC ₂ ,
Dummy cell circuit DC ₂ , memory cell MC ₊₁ ,
MC〓 ₊₂ , . . . MC _N and the data output circuit DIO are connected to the bit line BL ₂ , respectively, and the sense amplifier circuit SA is connected to both the bit lines BL ₁ and BL ₂ . Memory cells MC ₁ , MC ₂ , ... MC _N are the second
As shown in the figure, it is composed of a field effect transistor Q _M and a capacitor _CM . The drain of the field effect transistor Q _M is connected to the bit line B, and the source of the field effect transistor Q _M is connected to the capacitor _CM. is connected to the first terminal of
The second terminal of the capacitor C _M is supplied with a DC voltage V _DD and the gate of the field effect transistor Q _M is connected to the word line. Hereinafter, the connection point between the source of the field effect transistor Q _M and the first terminal of the capacitor _CM will be referred to as a node _NM . dummy cell
As shown in Figure 3, DC ₁ and DC ₂ are composed of field effect transistors Q _D1 and Q _D2 and a capacitor C _D. The drain of Q _D1 is connected to the bit line, and the field effect transistor Q _D1 source,
The drain of the field effect transistor Q _D2 and the first terminal of the capacitor C _D are connected to each other, the gate of the field effect transistor Q _D1 is connected to the dummy word line DW, and the second terminal of the capacitor C _D is connected to each other.
A DC voltage V _DD is supplied to the terminal of the field effect transistor Q D2, and a DC voltage V _SS is supplied to the source of the field effect transistor Q _D2 .
is supplied, and a clock signal φ _R is supplied to the gate of transistor Q _D2 . Hereinafter, the source of the field effect transistor Q _D1 , the drain of the field effect transistor Q _D2 , and the first of the capacitor C _D
The connection point of the terminals is called the node N _D. As shown in Fig. 4, the sense amplifier circuit SA is composed of field effect transistors Q _S1 and Q _S2 , and the drain of the field effect transistor Q _S1 and the gate of Q _S2 are connected to the bit line BL ₁ , and the electric field The drain of the effect transistor Q _S2 and the gate of the field effect transistor Q _S1 are connected to the bit line BL ₂ , and a clock signal φ _D is supplied to the source of the field effect transistor Q _S1 and the source of the field effect transistor Q _S2 . ing.

In explaining the operation of this conventional memory circuit below, it is assumed that the DC voltage V _SS is a reference voltage, V _DD is a high voltage, and the field effect transistors Q _M , Q _D1 , Q _D2 , Q _S1 and Q _S2 are both N
Assume that it is a channel type normally-off type field effect transistor. In this memory circuit, one bit of memory information is stored in each memory cell, and the memory information is associated with the level of voltage at node N _M in the memory cell. In order to read stored information from a memory cell, one of the memory cells included in the row circuit is selected, and the signal transmitted to the bit line by the selected memory cell is amplified by a sense amplifier SA. data input/output circuit DIO
The signal is output to the outside of the storage circuit through. As mentioned above, selection of a memory cell is performed by setting the word line connected to the memory cell to a high potential, and if the memory cell to be selected is connected to the bit line _BL1 , the dummy cell circuit _DC2 is selected (selection of a dummy cell is performed by setting the dummy word line connected to the dummy cell to a high potential), and if the selected memory cell is connected to bit line _BL2 , the dummy cell is selected. Circuit DC ₁ is selected. In the following explanation, the value of the parasitic capacitance of the bit line _BL1 is set as C _B1 , and the bit line
Let the value of the parasitic capacitance of BL ₂ be C _B2 , and the capacitor C _M
Let the value of the capacitance of the capacitor C _CM be C CM and the value of the capacitance of the capacitor C _D be C _CD . A detailed explanation of the operation when memory cell MC _N is selected will be given below. Before a read operation is performed, the precharge circuit
Bit lines BL ₁ and BL ₂ are set to high voltage V by PC ₁ and PC ₂ .
The clock signal _φR , which is set to _DD and is supplied to the dummy cell circuits DC ₁ and DC ₂ , is set to a high potential and then brought to a low potential again.
The connection point N _D between DC ₁ and DC ₂ is set to the V _SS voltage, that is, the reference voltage. At this time, the clock signal φ _D supplied to the sense amplifier SA is set to a high voltage, and the field effect transistors Q _S1 and Q _S2 are non-conductive. Next, when memory cell MC _N and dummy cell circuit DC ₁ are selected, transistor Q _M of memory cell MC _N and field effect transistor Q _D1 of dummy cell circuit DC ₁ are both rendered conductive. Since the node N _D of the dummy cell circuit DC ₁ was set to the reference voltage (0 V), when the field effect transistor Q _D1 becomes conductive, the charge on the bit line BL ₁ is transferred to the capacitor C _D of the dummy cell circuit DC ₁ and the bit line. divided between the parasitic capacitances of BL ₁ , the voltage on bit line BL ₁ is V _DD
It changes from C _B1 /C _B1 +C _CD ·V _DD . if,
If the voltage at node N _M of memory cell MC _N is V _DD , even if memory cell MC _N is selected, the voltage on bit line BL ₂ will be V _{DD .}
remains. Conversely, if the node N _M of the memory cell MC _N is 0 [V], the memory cell
When MC _N is selected and field effect transistor Q _M of memory cell MC _N is in a conductive state, bit line BL ₂
The voltage changes from V _DD to C _B2 /C _B2 +C _CM ·V _DD .

Normally, the bit line parasitic capacitances C _B1 and C _B2 are designed to be equal, and V _DD and C _B2 /C _B2 +C _CM・V
The capacitance value C _CD of the capacitor is designed so that the intermediate potential of _DD becomes C _B1 /C _B1 +C _CD ·V _DD . In order to reduce the area of the memory cell and realize a high-density memory circuit, the capacitance value C _CM of the capacitor _CM cannot be increased, and the capacitance values C _CM , C _CD are replaced by parasitic capacitances _CB1 ,
Since it is very small compared to C _B2 , C _B2 /C _B2 +C
_CM ·V _DD , C _B1 /C _R1 +C _CD ·V _DD is a potential very close to V _DD , and the potential difference therebetween is usually several hundred mV or less.
The sense amplifier SA amplifies this minute potential difference between the bit lines BL ₁ and BL ₂ .

As mentioned above, after a slight potential difference is applied to the bit lines BL ₁ and BL ₂ by the memory cell and the dummy cell,
The clock signal _φD is set to a low potential and the bit line
Charge is discharged through one of the field effect transistors Q _S1 or Q _S2 such that the voltage of BL ₁ and BL ₂ , whichever is lower, becomes an increasingly lower potential;
The minute potential difference between the bit lines BL ₁ and BL ₂ expands, resulting in a large amplitude signal. When memory cell MC _N is selected and node N _M of memory cell MC _N stores a high voltage, bit line BL ₁ becomes C _B1 /C _B1 + C _CD · V _DD , and bit line BL ₂ becomes V _DD. Since the sense amplifier SA is set to
bit line _BL1 is set to 0 [V] and bit line _BL2 is kept at _VDD . memory cell
When MC _N is selected and node N _M of memory cell MC _N stores a low voltage, bit line BL ₁ becomes C _B1 /C _B1 + C _CD V _DD and bit line BL ₂ becomes C _B
2 /C _B2 +C _MD・V _DD , so the bit line BL ₁ is kept at C _B1・V _DD /C _B1 +C _CD by the sense amplifier SA, and the bit line BL ₂ is kept at 0 [V]. is set to In this way, the contents of the selected memory cell are taken out as a large amplitude signal on the bit line and output through the data input/output circuit DIO.

As explained above, the sense amplifier SA amplifies the minute signal transmitted from the memory cell to the bit line into a large amplitude signal.
Field effect transistors Q _S1 and Q _S2 that constitute SA
have the same threshold voltage, and the field effect transistor Q _S
1 , the gain constants of Q _S2 are the same, and the bit lines BL ₁ ,
If the parasitic capacitances C _B1 and C _B2 of BL ₂ are the same, in principle any small signal can be amplified correctly.
However, it is usually difficult to make the above circuit constants exactly the same, and there are some discrepancies. Therefore, the minute signal transmitted to the bit line needs to have an amplitude within a certain limit, and for that purpose, it is necessary to make C _CM larger than a certain limit. This is a major factor controlling the

The present invention is characterized by the addition of a sense amplifier circuit and a mechanism for correcting bit line asymmetry in order to eliminate the drawbacks of the conventional memory circuit, and embodiments thereof will be described in detail below.

In the row circuit of the memory circuit according to the first embodiment of the present invention, as shown in FIG. 5, a correction circuit CL _{1 is connected to BL 1 of} the conventional memory circuit shown in FIG.
The configuration is exactly the same as that of FIG. 1 except that the correction circuit CL ₂ is connected to BL ₂ . Correction circuit CL ₁
(CL ₂ ) is composed of a signal generation circuit G _{1 (} G _{2 )} and a correction memory cell _{M 1 (} M ₂ ) _. ) is controlled.

In the following explanation, as in the explanation of the operation of the conventional memory circuit, the DC voltage V _SS is a reference voltage,
0 volt, whereas V _DD is assumed to be a high voltage, and the field effect transistor is assumed to be of N-channel type and normally reoff type unless otherwise specified. The operation period of the memory circuit of this embodiment is divided into a correction period, a read period, a write period, and a standby period. Among these, the read period is a period for outputting already stored information to the outside, and as described for conventional memory circuits, minute electrical signals output from memory cells to bit lines are detected. . The operation during the write period is the same as the operation during the read period, except that an electric signal larger than the electric signal output from the memory cell is applied from the data input/output circuit DIO to the bit line BL ₂ of the selected row circuit. It is. During the standby period, the word line and dummy word line are set to a low potential, and the bit line is set to a high voltage V _DD to maintain the information stored in each memory cell while waiting for the next reading period or Ready for the writing period. Although a read period, a write period, and a standby period are provided in conventional memory circuits, the correction period is unique to the present invention and is provided immediately after power-on and prior to the write period and the read period. During the correction period, the asymmetry between the sense amplifier circuit and the bit line of each row circuit is tested, and the test results are stored in the correction memory cells _M1 and _M2 . During the read period and write period, prior to the operation of the sense amplifier circuit, the signal generation circuits _G1 and
_G2 adjusts the voltages of bit lines _BL1 and _BL2 according to the stored contents of correction memory cells _M1 and _M2, respectively, and operates to cancel the asymmetry between the sense amplifier circuit and the bit lines. If there is asymmetry in the sense amplifier circuit or bit line, when the voltage on bit line BL ₁ is higher than the voltage on bit line BL ₂ by a certain voltage or more, bit line BL ₁ is detected as a high voltage, and in other cases, the bit line is detected as high voltage.
BL ₂ is detected as high voltage. The above-mentioned constant voltage will be referred to as the offset voltage of this sense amplifier circuit. If the offset voltage is positive, the bit line BL ₁
has a tendency to be easily detected at a low voltage, and if the offset voltage is negative, _BL1 has a tendency to be easily detected at a high voltage. The offset voltage is a value that fluctuates due to uncertain factors during manufacturing, and also varies depending on each row circuit. Further, when the information stored in the correction memory cell M ₁ (M ₂ ) is "0", the signal generation circuit G ₁ (G ₂ ) outputs the bit line BL ₁
(BL ₂ ) voltage is not affected. The operation during the correction period will be explained next.

First, information "0" is stored in the correction memory cells _M1 and _M2 , and then, by the same operation as in the write period, the memory cells MC1 and _M2 of each row circuit are stored.
Node N _M of MC _N is set to 0 volts. Next, the bit lines BL ₁ and BL ₂ are set to a high voltage V _DD , and the nodes _ND of the dummy cell circuits DC ₁ and DC ₂ are set to 0 volts by the clock signal φ _R. Next, select the memory cell MC ₁ and the dummy cell circuit DC ₂ , change the bit line BL ₁ to C _B1 /C _R1 + C _CM · V _DD , and connect the bit line B
L ₂ is set to C _B2 /C _R2 +C _CD ·V _DD . C _B1 /
The difference between C _B1 +C _CM・V _DD and C _B2 /C _B2 +C _CD・V _DD is the sense amplifier circuit.
This is the amount of signal given to SA and will be called _VS. (It is assumed that V _S is positive.) After setting the bit line BL ₁ to a voltage lower than the bit line BL ₂ by the signal amount V _S as described above, the sense amplifier circuit SA is operated. If the offset voltage is smaller than -V _S , bit line _BL1 is detected as high voltage and bit line _BL2 is detected as low voltage, and if the offset voltage is larger than -V _S , bit line BL is detected as high voltage. ₁ is detected as low voltage and bit line _BL2 is detected as high voltage. Next, information is input to _{the correction memory cell M1 according} to the large amplitude signal given to the bit line BL1 by the above operation, and if the bit line _BL1 is at a high voltage, that is, the offset voltage is - If it is smaller than V _S , information "1" is stored in the correction memory cell _M1 ,
In other cases, information "0" is stored in the correction memory cell _M1 . Next, select memory cell MC _N and dummy cell DC ₁ in the same way as above, and connect the bit line.
After setting BL ₂ to a voltage lower than bit line BL ₁ by V _S , the sense amplifier circuit SA is operated, and according to the large amplitude signal obtained on bit line BL ₂ , a signal is applied to correction memory cell M ₂ . Information is stored. In this way, at the end of the correction period, if the offset voltage is smaller than -V _S , information "1" is stored in the correction memory cell _M1 and information "0" is stored in the correction memory cell _M2 . , the offset voltage is V _S
If it is larger, information "0" is stored in the correction memory cell _M1 and information "1" is stored in the correction memory cell _M2 . When information “1” is stored in the correction memory cell M ₁ (M ₂ ), the signal generation circuit
_The signal generating circuit G ₁ (G ₂ ) is designed to lower the voltage of the bit line BL ₁ (BL ₂ ) by 2V _S before _the sense amplifier circuit SA operates. Therefore, in the read period and write period, when the offset voltage is smaller than -V _S , the sense amplifier circuit SA operates as if the offset voltage had increased by 2V _S , and when the offset voltage is larger than V S, the sense amplifier circuit SA operates as if the offset voltage had increased by 2V _S. The sense amplifier circuit SA operates as if the offset voltage had been reduced by 2V _S. Therefore, even if the stochastic distribution of the offset voltage ranges from -3V _S to 3V _S , the effective offset voltage operates as if it were distributed from -V _S to V _S. Therefore, assuming that the offset voltage distribution is constant, by using such a correction means, the signal voltage V _S from the memory cell can be reduced to about 1/3, making it possible to downsize the memory cell. Become.

FIG. 6 shows a specific example of the correction circuit, in which the correction memory cells M are field effect transistors Q _C5 , Q
It consists of a flip-flop circuit consisting of _C6 and load resistors R ₁ and R ₂ , and a gate field effect transistor Q _C4 for writing correction information into the flip-flop circuit using a clock signal φ _C during the correction period. Further, in the signal generating circuit G, field effect transistors Q _C1 , Q _C2 , Q _C3 and a capacitor C ₁ are connected as shown in the figure, and the clock signal φ _R
After setting _the node N _C1 to a _{constant potential by} bit line
Electrical connection with BL is controlled. When the transistor Q _C2 is controlled to be conductive, a correction voltage determined by the capacitance of the capacitor C ₁ can be applied to the bit line BL.

FIG. 7 shows another specific example of the correction circuit.
The correction memory cell M is a field effect transistor Q _C1
The signal generation circuit is constructed using _{a field effect transistor QC7 and} a capacitor _C2 to provide a correction capacitance to the bit line.

In the first embodiment, two correction circuits
CL ₁ and CL ₂ were used, but the second embodiment, the configuration of which is shown in FIG. 8, uses four correction circuits CL ₁ , CL ₂ ,
It is equipped with CL ₃ and CL ₄ , and the correction circuits CL ₁ and CL ₃ are
_BL1 , correction circuits _CL2 and _CL4 are connected to the bit line _BL2 , respectively. Just like the correction circuits CL ₁ and CL ₂ , the correction circuits CL ₃ and (CL ₄ ) are signal generation circuits G ₃
(G ₄ ) and a correction memory cell M ₃ (M ₄ ), and the signal generation circuit G ₃ (G ₄ ) is controlled by the correction memory M ₃ (M ₄ ).
A correction period is also provided in the second embodiment.
In the first half of the correction period, information regarding the offset voltage is stored in the correction circuits CL ₁ and CL ₂ by the same operation as in the first embodiment, and the width of the effective offset voltage distribution is reduced by 4V _S. In the second half of the correction period, while correction is performed by correction circuits CL ₁ and CL ₂ , correction circuits CL ₃ and CL ₄ are provided with the effective value corrected by correction circuits CL ₁ and CL ₂ in exactly the same manner as in the first embodiment. information regarding the offset voltage. By using four correction circuits in this way, the width of the offset voltage distribution can be effectively reduced to 8V _S.
can be reduced.

By further increasing the number of correction circuits, it is also possible to further effectively reduce the width of the offset voltage distribution.

In the above embodiment, the signal generation circuits G ₁ and G ₂ have the function of lowering the voltage of the bit lines BL ₁ and BL ₂ by a certain amount.
G ₁ and G ₂ are the parasitic capacitances C _B1 and C _B of the bit lines BL ₁ and BL ₂
It may have a function of increasing the number by ₂ .

In the above embodiment, the correction memory cells M ₁ ,
Although _M2 is a so-called static type memory cell, it may also be a dynamic type memory cell or a programmable ROM. In the case of a dynamic memory cell, it is necessary to provide a periodic correction period even after the power is turned on, and in the case of a programmable ROM, it is sufficient to provide a correction period only once after manufacture.

In the first embodiment, the node N _M of the memory cells M _C1 and M _CN is set to 0 volts at the beginning of the correction period, and then immediately before operating the sense amplifier circuit SA to obtain correction data, The voltage difference between the two bit lines was set to V _S . Therefore, the offset voltage is corrected only when the absolute value of the offset voltage is greater than or equal to _VS.
No correction is made if the absolute value of the offset voltage is slightly smaller than V _S . However, there are stochastic variations in the signals output from the memory cells to the bit lines, and there may also be manufacturing variations in the correction circuit, so even if the absolute value of the offset voltage is slightly smaller than V _S , the correction may not be possible. If this is done, the object of the present invention can be achieved more reliably.

FIG. 9 shows a row circuit of a third embodiment that is improved in this respect. The row circuit of the third embodiment is shown in FIG.
It is constructed by adding a field effect transistor _Q1 to the row circuit of the embodiment, and the field effect transistor
The source and drain of Q ₁ are bit lines BL ₁ and BL ₂
A clock signal _φ1 is supplied to the gate of the transistor _Q1 .
At the beginning of the correction period of the third embodiment, first,
Bit lines BL ₁ and BL ₂ are precharge circuits PC ₁ and PC ₂
The clock signal φ ₁ is then set to a high voltage by
is set to high voltage. Next, sense amplifier circuit SA
The clock signal φ _D supplied to the circuit is set from a high voltage to a low voltage. At this time, since the clock signal φ ₁ is set to a high voltage, the bit lines BL ₁ and BL ₂ are electrically connected, and even if the clock signal φ _D is set to a low voltage, the normal detection amplification operation will not occur. Bit lines BL ₁ and BL ₂ are both connected to the clock signal φ _D
The voltage is set to the voltage obtained by adding the threshold voltage of the field effect transistor to the voltage of . Assuming that the low voltage of clock signal φ _D is 0 volts, bit lines BL ₁ and BL ₂ will be set to a threshold voltage. At this time, if the world line connected to memory cells MC ₁ and MC _N is kept at high voltage, memory cells MC ₁ and MC N
Node N _M of MC _N is set to the above threshold voltage. After this, the clock signal φ ₁ is again set to a low voltage and the bit line BL ₁ and
After setting BL ₂ to high voltage V _DD , memory cell MC ₁
and select dummy cell circuit DC ₂ , bit line BL ₁
The voltage difference between and BL ₂ is smaller than V ₁ (this value is called V′ ₁
). On the other hand, signal generation circuit G ₁
By also setting the amount of correction by _G2 to _2V'1 , correction can be performed even when the absolute value of the offset voltage is smaller than _Vs.

In the third embodiment described above, only when operating the sense amplifier circuit for inspection during the correction period, the bit line voltage is changed in order to reduce the voltage of the signal from the memory cell compared to the normal read period. It was set equal to the threshold voltage of the field effect transistor.
However, the point is that the bit line voltage is lower than the write voltage to the memory cell during the normal write period (i.e., 0 volts and V _DD in the embodiment) and the intermediate voltage V _DD /2.
By setting the voltage to a value close to , and setting the node N _M of the memory cell to this voltage, it is possible to obtain a smaller signal voltage than in the read period.

In the third embodiment described above, by setting the bit line voltage differently from the write period, the voltage at the node N _M of the memory cell was set, and a smaller signal amount than usual was obtained during the correction period. The write voltage to the memory cell during the correction period is made equal to the normal write voltage, and after the refresh period of this memory circuit or a longer period of time has elapsed, the memory cell is selected and a smaller electrical signal than usual is applied to the bit line. obtained,
The sense amplifier circuit may be operated for testing purposes. Further, in this case, a large number of memory cells may be selected one after another, and the sense amplifier circuit may be tested based on the electrical signal from the memory cell having the smallest signal voltage amount.

As explained above, according to the present invention, the width of the offset voltage distribution of the sense amplifier circuit can be effectively reduced, the signal voltage output from the memory cell to the bit line can be reduced, and the width of the offset voltage distribution of the sense amplifier circuit can be reduced. can be made smaller. Therefore, according to the present invention, it is possible to increase the density of the memory circuit.

[Brief explanation of the drawing]

Figure 1 is a configuration diagram of a row circuit of a conventional memory circuit.
2 is a circuit diagram of a memory cell, FIG. 3 is a circuit diagram of a dummy cell circuit, FIG. 4 is a circuit diagram of a sense amplifier circuit, and FIG. 5 is a configuration diagram of a row circuit according to the first embodiment of the present invention. 6 and 7 are circuit diagrams showing specific examples of the correction circuit, FIG. 8 is a configuration diagram of the row circuit of the second embodiment of the present invention, and FIG. 9 is a circuit diagram of the third embodiment of the present invention. FIG. 3 is a configuration diagram of a row circuit. MC ₁ , MC ₂ ,…, MC〓, MC〓 ₊₁ ,…MC _N …
...Memory cell, DC ₁ , DC ₂ ...Dummy cell circuit,
SA...Sense amplifier circuit, PC ₁ , PC ₂ ...Precharge circuit, DIO...Data input/output circuit, BL ₁ ,
BL ₂ ...Bit line, C _M , C _D ...Capacitor, N
_M , N _D ... Node, V _DD , V _SS ... DC voltage, φ
_R , φ _D , φ ₁ ...Clock signal, Q _M , Q _D1 , Q _S
1 , Q _S2 , Q ₁ ... field effect transistor, CL ₁ ,
CL ₂ , CL ₃ , CL ₄ ... Correction circuit, G ₁ , G ₂ , G ₃ , G ₄
... Signal generation circuit, M ₁ , M ₂ , M ₃ , M ₄ ... Correction memory cell.

Claims (1)

[Claims] 1. A sense amplifier comprising a large number of memory cells (referred to as main memory cells) for storing information input from the outside and detecting electrical signals output from the main memory cells. A memory circuit including a memory cell other than the above (referred to as a correction memory) that stores information for correcting the sense amplification circuit, and a memory cell that stores information for correcting the sense amplification circuit, and the sense amplification circuit based on the information stored in the correction memory cell. A means for correcting to reduce the absolute value of the offset voltage of the circuit, and a means for correcting to reduce the absolute value of the offset voltage of the circuit, and a means for applying information to the storage node of the main memory cell corresponding to two logical values when inputting information input from the outside to the main memory cell. Information is stored in the correction memory cell by generating a voltage lower than one of the two voltages and higher than the other at the storage node of the main memory cell, and outputting an electrical signal from the main memory cell to the sense amplifier circuit. A memory circuit characterized in that it is provided with means for obtaining.