JPS61287171A - Insulated gate field-effect type semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To remove overlap capacitance and a surface stepped section by overlapping, and to increase density and improve performance by burying a gate electrode into a region surrounded by first polysilicon as source-drain electrodes and a thick oxide film. CONSTITUTION:A photo-resist layer 14 is formed onto the surface of a gate electrode material 10 on oxide films 8, 9 through high-speed rotary application, and a photo-resist 15 is left only on the surface of the electrode material 10 in a lowermost gate region by etching the whole surface under conditions, in which the etching rate of the gate electrode material 10 is the same as or faster than others, through a reactive ion etching method. Etching is continued and the electrode material except the upper section of the gate region is removed, and a gate electrode material 16 is buried onto the gate region surrounded by the oxide films 8, 9 in a self-alignment manner, thus manufacturing structure having no overlapping. The whole surface is coated with an intermediate insulating film 17, contact holes 18-20 from gate, source and drain electrodes are bored and metallic wiring layers 21 are shaped, and a passivation insulating film 22 is formed onto the whole surface.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to an insulated gate field effect semiconductor device such as MO8ff1 that can be integrated at high density and a manufacturing method thereof.

[Conventional technology]

Figure 3 shows a conventional MO8 type semiconductor device, (a
) is a cross-sectional view of a pLOCO8 structure formed by the conventional method.
Thick oxide film A, 3 impurities in substrate 1 and reflective layer 102
0 to 1 (p1/- is the doped first polysilicon layer. This polysilicon layer serves as a source/drain diffusion source and prevents it from being diffused under the gate region. For example, as shown in the figure, Separate the upper layer A, which does not contact the substrate 1, and the lower layer B, which contacts the substrate 1, and dope only the upper layer with impurities.The impurity doping of the upper layer A is carried out using an implanter, and the layer thickness is the same as that of polyethylene. silicon layer 3 to 30
In the case of 0 OA, the upper layer A is within 1000λ, and the impurities to be doped are As and P, but As has a slow diffusion coefficient and is advantageous.

Figure 3) shows a field sio including the source/drain regions, a substrate 1 formed with seven turns extending over it, and a source/drain electrode 4.5 doped with impurities of a reflective layer diffused. As a source, for example, the source/drain diffusion layer 6,
7 is formed, and then oxide films 8 and 9 are formed on the entire surface. Here, 8 is a gate oxide film of, for example, 100 to 5 ooA, which is formed on the gate region from which the first polysilicon layer has been removed, and 9 is a gate oxide film formed on the impurity-doped source/drain electrodes 4.5. 10!0 to 1021 in the first polysilicon layer when the oxide film is formed by thermal oxidation.
/- impurity doping amount, oxidation temperature SOO~1000℃
Depending on the dry and wet atmospheres, the film thickness ratio t 9 of the films 8 and 9 can be increased to about 1, 2 to 4.5.

Thereafter, the conductive gate electrode material 10 is applied to the oxide film 8,
9, and a photoresist 11 is applied on the electrode material 10. The electrode material may be 10-wire second polysilicon, 7-wire metal, silicide or polycide. Thus, the photoresist other than the region 12 that will become the gate is removed by normal exposure and development (FIG. 3(a)), and then the dirt electrode material 10 is patterned using the region 12 as a mask material to form the gate electrode 13. , area 12 is removed (FIG. 3(e)). After that, an insulating film is applied using normal manufacturing methods, and contact holes, metal wiring, and hashing are completed.

[Problem that the invention seeks to solve]

However, the above manufacturing method requires a margin for alignment of the gate electrode 13 with the source-drain electrodes 4, 5, and overlap with the source-drain occurs as shown in FIG. This causes an overlap capacitance with the source and drain, degrading the performance of the MO8 element, and creating unnecessary surface steps at the overlapped portions.

As described above, this invention eliminates the automatic overlap between the gate electrode and the source and drain electrodes, eliminates the overlap capacitance and the surface level difference caused by the automatic overlap, and provides a high-density and high-performance MO3 semiconductor device. A manufacturing method is provided.

[Means for solving problems]

In order to solve the above-mentioned problems, the present invention provides an edge-gate field effect semiconductor device in which a gate electrode is buried in a region surrounded by a first polysilicon serving as a source/drain electrode and a thick oxide film. It is something.

In addition, in the method for manufacturing the semiconductor device described above, a photoresist is buried and coated on the gate region surrounded by the first polysilicon and the oxide film, and the gate electrode material is left in a self-aligned manner only on the gate electrode using a dry etching method. It is something that

In addition, regarding the method of opening the gate electrode contact hole, if the gate electrode is made of silicide or polysilicon, a nitride film is formed on it, and the entire surface is oxidized using this as a mask until the thickness of the gate electrode material is not exceeded. Then, the nitride film used as a mask was removed to form a contact hole for the gate electrode.

[For production]

According to the present invention, as described above, the gate electrode material is embedded in the electrode region surrounded by the first polysilicon and the thick oxide film in a self-aligned manner, so that the gate electrode material and the source/drain Overlapping can be eliminated and a high-density, high-performance semiconductor device with no surface steps can be obtained.

In addition, when opening the gate electrode contact hole, a nitride film is formed on the gate electrode, and selective oxidation is performed using this as a mask.
The nitride film used as a mask is removed by etching to form an electrode contact hole.Dry etching with the gas used for etching partially etches the electrode material because the etching rate of the polysilicon electrode material and the nitride film are approximately the same. A nitride film can be left behind, and electrode contact holes can be formed by removing this nitride film.

[Embodiments of the invention]

Embodiments of the present invention will be described below with reference to FIGS. In the present invention, the steps up to FIG. 3(a) which were previously explained in connection with the conventional semiconductor lining method are the same, but the steps starting from FIG. 1(-) are different from the conventional manufacturing steps. In other words, in Figure 1-),
First, a photoresist layer 14 is formed on the surface of the gate electrode material 10 on the oxide films 8 and 9 by spin-coating a photoresist having a relatively low viscosity (15 cp or less) at high speed (3000 rpm or more). Thereafter, the entire surface of the photoresist layer 14 is etched using a reactive ion etching method.
4) Etch the entire surface of the gate electrode material 10 at the same or faster etching rate to expose the surface of the electrode material,
The photoresist 15 remains only on the surface of the electrode material in the lowest gate region (FIG. 1). Further etching is continued to form an electrode material 16 in which the electrode material other than the area on the gate region is removed (FIG. 1(C)).

In this way, by embedding the gate electrode material 16 in a self-aligned manner onto the gate region surrounded by the oxide film 8.9, a structure without overlap can be manufactured. Thereafter, the entire surface of the intermediate insulating film 17 is covered by the usual method, and contact holes 18, 19, and 20 from the gate, source, and drain electrodes are opened (
Figure 1(d)).

Then, a metal wiring layer 21 is formed on the gate, source, and drain electrodes, and a passivation insulating film 2 is formed on the entire surface.
2 (Fig. 1(e)).

FIG. 2 shows another embodiment of the present invention, which differs from the process shown in FIG. 1(c) in the same way as the embodiment described above. That is, first, in the above embodiment, a relatively thin film (100 ~
100o1) A nitride film 23 is deposited on the entire surface, and a first
Photoresist 14 is formed in the same manner as in Figure 2 (Figure 2).
a)). Thereafter, as in FIG. 1(b), the photoresist 15 is left partially (see FIG. 2)), and the electrode material 10 and nitride film 23 other than on the gate area are removed by etching (see FIG. 2(C)). . Dry etching using a carbon heptide-based gas, which is generally used for etching, has substantially the same etching rate for polysilicon and nitride film, so nitride film 23 can be left partially as shown in (C). This point is a feature of this embodiment. Thereafter, the entire surface is oxidized under conditions such that the portion of the gate electrode material 10 on the gate region that is not covered with the nitride film 23 is not entirely oxidized in the film thickness direction. This is done by selective oxidation using the nitride film 23 of the gate electrode material 10 as a mask on the region 1, and a partial selective oxidation portion 24 of the gate electrode material is formed.

Further, the source/drain electrodes 4 and 5 are further oxidized, and the silicon oxide film 9 becomes a thick film 25 (FIG. 2(d)).
. In this way, the nitride film 23 is removed by dry etching using a carbon heptide-based gas or by hot rinsing, and the contact hole 26 of the gate electrode material 10 is exposed. After that, the source/drain electrode extraction holes 19 and 20 are opened by the usual process,
A metal wiring 21 is formed, and a notch 22 is formed (FIG. 2(e)). As described above, in this embodiment, the gate electrode contact hole 26 can be formed in a self-aligned manner by selectively oxidizing the gate electrode material, which is an effective means for fine device structures.

〔Effect of the invention〕

As explained in detail above, according to the present invention, the gate electrode remains and is embedded in the region surrounded by the polysilicon and oxide film that will become the source/drain electrodes, so that the gate electrode and the source/drain It is possible to eliminate autoclap of electrodes, eliminate autolap capacitance and overlap level difference. Further, by using conductive polysilicon or silicide as the gate electrode material, the contact hole on the gate electrode can be formed in a self-aligned manner. As a result, a high-performance and high-density semiconductor device can be obtained.

Furthermore, the present invention is not limited to MO8 type semiconductor devices, but also applies to LSI
, it is widely applicable to VLSI in general.

[Brief explanation of drawings]

1(a) to (e) are process diagrams showing the manufacturing process of the semiconductor device of the present invention, FIGS. 2(a) to (e) are manufacturing process diagrams showing other embodiments of the present invention, and FIG. ) to (·) are conventional semiconductor manufacturing process diagrams. 1...Substrate, 2...Field oxide film, 4, 5...
- Source train tffl, 6, 7... Source fist drain diffusion layer, 8, 9... Oxide film, 10... Gate electrode material, 14.15... Photoresist, 16...
・Gate electrode material, 23... Nitride film, 24.25...
Oxide film, 26... contact hole. No. 151 $-Aji N Needle Akame Kaba Ineto G&'Hair 1 Step Diagram Figure 1 Figure 2 vA Volume 11-Moe M! Let> Actual Example Diagram 2

Claims (3)

[Claims] (1) A conductive gate electrode material is left in a self-aligned manner and embedded in the electrode region surrounded by the first polysilicon and thick oxide film formed on the semiconductor substrate to become the source/drain electrodes. An insulated gate field effect semiconductor device characterized by: (2) In a MOS semiconductor device, source and drain electrodes are formed in a self-aligned manner on a conductive gate electrode material, and the gate is surrounded by a field oxide film and source and drain electrodes extending over the field. A highly fluid photoresist is buried and coated on the area, and the entire surface is etched back using a dry etching method in which the etching ratio of the photoresist and the gate electrode material is approximately equal, or the photoresist is slower, and the gate is self-aligned only on the gate area. A method for manufacturing an insulated gate field effect semiconductor, characterized in that an electrode material remains. (3) The gate electrode material is made of conductive polysilicon or silicide, and a nitride film is deposited on the entire surface of the gate electrode material,
After that, a photoresist is applied on the nitride film and the entire surface is etched back using a dry etching method, leaving the nitride film only on the area that should become the gate electrode contact hole on the gate electrode area that was formed in a self-aligned manner on the gate area. The nitride film is then used as a mask to oxidize the entire surface, selectively oxidize until the thickness does not exceed the thickness of the gate electrode material, and then the nitride film used as the mask is removed to form a contact hole for the gate electrode. A method for manufacturing an insulated gate field effect semiconductor.