JPS61283223A - Digital-analog converter - Google Patents

Abstract

PURPOSE:To improve the accuracy of D/A conversion by converting once a binary signal inputted to a bit input terminal group into a PWM wave and then converting it into an analog signal being the state of signal before converted into the binary signal. CONSTITUTION:A pulse width signal generator P is provided with output terminals for the 1st pulse width signal P1 synchronously with a period T and having a minimum pulse width T/2N<-1>, the 2nd pulse width signal P2 synchronous ly with the trailing of the signal P1 and having a pulse width T/2N<-2>, the 3rd pulse width signal P3 synchronously with the trailing of the signal P2 and having a pulse width T/2N<-3>,..., the N-th pulse width signal PN synchronously with the trailing of the (N-1)-th pulse width signal PN-1 and having a maximum pulse width T/2, and generates the 1st...N-th pulse width signals P1...PN. Then the pulse width signal generator P generates pulse width signals with high accuracy by using a flip-flop circuit and a counter circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION Object of the Invention: [Industrial Application Field] The present invention is used in the field of converting natural binary digital signals into analog signals.

[Prior Art] Conventionally, D/A converters are referred to as (a) weighted resistance type, (b) resistance ladder type, (c>DEM type, (d) current source parallel type, and (e) integral type. There are things to do.

[Problems to be Solved by the Invention] The resistance type D/A converter and the resistance ladder type D/A converter described above are not suitable for mass production because the accuracy of the D/A converter is determined by the accuracy of the resistor. Furthermore, the DEM type D/A converter requires a large number of capacitors, resulting in high cost. In addition, current source parallel type D/A
The converter requires a large number of current sources, resulting in high cost. Further, the integral type D/A converter is not suitable for mass production because it is affected by the characteristics of the capacitor.

This invention was made in view of the above points, and
This was done with the aim of providing a D/A converter that has excellent accuracy, is suitable for IC implementation, and can be downsized by IC implementation.

Structure of the Invention: As shown in the circuit block diagram of FIG. 1, the D/A converter of the present invention has an input terminal for a binary signal obtained by encoding sampling values every cycle T into binary numbers, and has a minimum bit. 1
Bit input terminal group I (−I+
, Ij2. 13 , . . . , IN> and a pulse width signal generator with = 1.2, 3 . ...°, N, and generally the 1st pulse width signal rises at the falling edge of the (k-1)th pulse width signal, and the pulse width Wk is expressed as Wk = T/2N-(k - 1). a pulse width signal generator P that outputs the pulse width signal of the pulse width signal generator P to the bit input terminal I of the bit input terminal group (2);

A gate circuit group G (-Gt, G2.

G3. ..., GN), an OR circuit S that calculates the state sum of only one digit of each gate output of this gate circuit group G, and an OR circuit S that integrates the output of this OR circuit S and cuts off high-frequency components. It is characterized by comprising a low-pass filter circuit F.

The bit input terminal group I has a binary signal of 1 which is obtained by encoding the sampling value of the analog signal every period T into a binary number.
The bit is sent to the 1-bit input terminal 11, the 2-bit to the 2-bit input terminal I2, the 3-bit to the 3-bit input terminal I3,
..., and a binary signal is input to its predetermined bit input terminal.

The pulse width signal generator P generates a first pulse width signal Pt which is synchronized with the period T and has a minimum pulse width T/2N-'.

Synchronized with the falling edge of the first pulse width signal P1, the pulse width becomes T/
2N-2 second pulse width signal P2. Second pulse width signal P
2 and has a pulse width of T/2N-3. ..., (N-1)th pulse width signal P
Synchronized with the falling edge of N-1, the N-th pulse width has the maximum width T/2.
An output terminal for a pulse width signal PN is provided, and a first pulse width signal P1. Second pulse width signal P2. 3rd pulse width signal @P3.
....

Generate the Nth pulse width signal @PN. The pulse width signal generator P can generate a pulse width signal with an accurate pulse width by using a flip-flop circuit, a counter circuit, or the like.

The gate circuit group G includes first gate circuits G1 . A second gate circuit G2 that opens and closes the second pulse width signal P2 depending on the presence or absence of a 2-bit input signal at the 1-bit input terminal I2. A third gate circuit G31 which opens the third pulse width signal P3 depending on the presence or absence of the 3-bit input signal at the 3-bit input terminal I3..., converts the N-th pulse width signal PN into the 1-bit input signal at the N-bit input terminal IN. It is equipped with an Nth gate circuit GN that opens and closes depending on the presence or absence of the gate.

The OR circuit S is connected to the first gate circuit G1. Second gate circuit G
21 Third gate circuit G3 r..., calculates the state sum of only one digit of each gate output of the N-th gate circuit GN,
The output is the binary signal input to the bit input terminal group (2) converted into a PWM wave.

The low-pass filter circuit F performs PWM of the output of the OR circuit S.
The wave is integrated and high-frequency components are cut off, and the output becomes an analog signal of the binary signal input to the bit input terminal group I before being converted to a binary signal.

In this way, the D/A converter of the present invention converts the binary signal input to the bit input terminal group I into a PWM wave, and then converts it into an analog signal before being converted into a binary signal. It is.

Effects of the invention: The D/A converter of the present invention not only can perform D/A conversion, but also the pulse width signal generator P, which influences the accuracy of the D/A converter, generally uses a flip-flop circuit, a counter circuit, etc. It is possible to obtain a signal with a highly accurate pulse width by using the D/A converter, and therefore the conversion accuracy of the D/A converter is excellent. Moreover, it is easy to integrate into an IC and can be miniaturized.

[Brief explanation of drawings]

FIG. 1 is a circuit block diagram for explaining the present invention, and FIG. 2 is a diagram for explaining a pulse width signal. ■...Bit input terminal group, P...Pulse width signal generator,
G: Gate circuit group, S: OR circuit, F: Low-pass filter circuit.

Claims (1)

[Claims] A group of bit input terminals that are input terminals for binary signals obtained by encoding sampling values every cycle T into binary numbers, where the minimum bit is 1 and the maximum bit is N, and a pulse width signal generator. Assuming that k=1, 2, 3,..., N, generally the th pulse width signal rises at the falling edge of the (k-1)th pulse width signal, and the pulse width W_k is W_k=T/2^ A pulse width signal generator that expresses N^-^ (^k^-^1^) and the k-th pulse width signal generator of the pulse width signal generator.
a group of gate circuits that express a pulse width signal by a k-th gate circuit that opens and closes according to a signal of a k-th bit input terminal of the bit input terminal group; and a gate output of each of the gate circuit groups. D characterized in that it is equipped with an OR circuit that calculates a state sum of only one digit, and a low-pass filter circuit that integrates the output of the OR circuit and blocks high-frequency components.
/A converter.